IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 12, DECEMBER 2006 981
Analysis of Poly-Si TFT Degradation Under Gate
Pulse Stress Using the Slicing Model
Ya-Hsiang Tai, Shih-Che Huang, and Chien-Kwen Chen
Abstract—The device degradation of polycrystalline-silicon
thin-film transistors stressed with different gate pulse waveforms is investigated. It is first observed that the degradation is depen-dent on the rising time of the gate pulses for the gate voltage swing below the threshold voltage. The degradation ratio of the mobility is analyzed with respect to two factors, namely, the magnitude of the lateral transient electric field and the change in the numbers of the carrier near the edges of the channel. A new index considering these two factors is proposed to depict the device degradation. It shows good linearity between the degradation in mobility and the proposed index.
Index Terms—AC stress, dynamic stress, poly-Si thin-film
tran-sistors (TFTs), reliability.
I. INTRODUCTION
P
OLYCRYSTALLINE-SILICON (poly-Si) thin-film tran-sistors (TFTs) have been widely used in active-matrix displays [1]. The higher mobility of poly-Si TFTs allows the fabrication of the pixel array and peripheral circuits on the same glass substrate. TFTs in driver circuits, unlike those in the pixels, are subjected to high-frequency voltage pulses [2], [3]. Therefore, the degradation mechanism under dynamic operation should be understood in detail. However, the studies about ac stress of the poly-Si TFTs are very few. In this letter, correlations between experiments and simulation results were made to evaluate the degradation of poly-Si TFTs under ac stress.II. EXPERIMENTS
Top-gate n-type poly-Si TFTs with lightly doped drain (LDD) were used in this letter. First, the buffer oxide and a-Si:H film with a thickness of 50 nm were deposited on glass substrates with plasma enhanced chemical vapor deposition (PECVD). The samples were then put in the oven for dehydrogenation. The XeCl excimer laser with a wavelength of 308 nm and energy density of 400 mJ/cm2was applied. The laser scanned the a-Si:H film with the beam width of 4 mm and 98% overlap to recrystallize the a-Si:H film to poly-Si. The Manuscript received August 15, 2006; revised September 21, 2006. This work was supported in part by the MOEA Technology Development for Academia under Project 94-EC-17-A-07-S1-046. The review of this letter was arranged by Editor J. Sin.
Y.-H. Tai and C.-K. Chen are with the Department of Photonics and Display Institute, National Chiao-Tung University, Hsinchu 30010, Taiwan, R.O.C. (e-mail: [email protected]).
S.-C. Huang is with the Department of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan, R.O.C.
Color versions of all figures are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2006.886416
Fig. 1. Waveform of the ac signal applied to the gate electrode of the TFTs, whereVGH,VGL,VTH,T , T_VGH,T_VGL,TR, andTF are, respectively, the high and low voltages of the pulse, the threshold voltage of the TFT, the period of the pulse, the duration of the high and low voltages, and the rising time and falling time of the gate pluses.
average grain size of the poly-Si film is about 0.5 µm. After
poly-Si active area definition, 80-nm SiO2and 40-nm SiNxwas
deposited with PECVD as the gate insulator. Next, the metal gate was formed by sputter and then defined. The LDD and the n+source/drain doping were formed by PH3implantation with a dosage of 2× 1013 cm−2 and 2× 1015 cm−2 of PH3, respectively. The LDD implantation was self-aligned, and the n+ regions were defined with a separate mask. Then, the interlayer of SiNx was deposited. Subsequently, the rapid thermal annealing was conducted to activate the dopants. Meanwhile, the poly-Si film was hydrogenated. Finally, contact hole formation and metallization were performed to complete the fabrication work. The typical values of the threshold voltage and the mobility of the samples are 1.68 V and 77.8 cm2/V · s. In this letter, the TFTs having a channel
width of 20 µm and a channel length of 5 µm with an LDD
structure length of 1.2µm are stressed and measured.
Waveform of the ac signal applied to the gate electrode of TFTs is shown in Fig. 1. Pulses with high-voltage VGH of
15 and 0 V, low-voltage VGL of 0 and−15 V, and period T
of about 2–3µs were applied to the gate electrode. The source
and drain were grounded to avoid the dc effect [4].
III. RESULT ANDDISCUSSION
The rising and falling time dependences for the mobility degradation of the device after dynamic stress are shown in Fig. 2(a) and (b), respectively. The mobility degradation is 0741-3106/$20.00 © 2006 IEEE
982 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 12, DECEMBER 2006
Fig. 2. Mobility degradation versus the number of repetitions of the gate pulses for: (a) different rising timeTRfor a fixedTFand (b) different falling timeTF
for a fixedTR, with the gate voltage swing from−15 to 15 V (dash lines) and −15 to 0 V (solid lines). defined as (1 − µ/µ0), where µ0 and µ are the field-effect
mobility derived from the maximum transconductance at the drain voltage of 0.1 V before and after stress. For the gate voltage swing from−15 to 15 V, the rising time TRexhibits no significant effect on the degradation, as shown in the dash lines in Fig. 2(a). On the other hand, the mobility degradation de-pends strongly on the falling timeTF, as shown in the dash lines
in Fig. 2(b). The shorterTF the gate pulse applied, the worse
degradation the device would suffer. A previous reported model claimed that, as the gate voltage swung from theONregion to theOFFregion, the induced electrons in the channel would rush to the source and drain regions [5]–[7]. At this time, there would be some trapped electrons, and they are exposed to the high electric field. For shorter pulse fall times, more electrons are exposed to the high electric field and become hot carriers [7].
However, for the gate voltage swings from −15 to 0 V, it is first observed that the degradation is obviously dependent on both the rising time and falling time, as shown by the solid lines in Fig. 2(a) and (b). Since there are no induced electrons for these applied gate voltages, it reveals that the previously proposed model may be incomplete.
In order to universally describe the aforementioned phenomena, two factors are taken into consideration, that is, the transient electric field in the lateral direction and the changes in the number of the channel electrons under the lateral voltage difference. To understand the transient fields and charge distributions in the channel, a slicing method is used on the device for simulation. A whole TFT is sliced into many shorter ones in series, as shown in the inset of Fig. 3. In this letter, the original TFT with a channel length of 5µm is sliced into ten
TFTs in series, with a channel length of 0.5µm. The ten TFTs
are of the same model, and the model parameters of the sliced TFTs are carefully adjusted such that the simulated transfer characteristics of the sliced devices are very similar to that of the original unstressed device. Using a commercially available circuit simulator SPECTRE, the transient voltage distribution of different nodes under dynamic stress can be calculated. The voltage difference between the edge node and the grounded source/drain of the sliced TFTVeis found to be the largest for
all stages of the applied gate voltage. Referring to the previous
Fig. 3. Lateral voltage difference Ve for: (a) Vg= −15 ∼ 15 V and
(b)Vg= −15 ∼ 0 V, respectively, wherein Vgis the applied gate voltage and
Veis the voltage difference of the sliced TFT at the edge.
report, the emission image of the TFT under dynamic stress indicates that the degradation is the worst at the edges of the channel [7]. It also accords with the simulation results that Ve is the largest voltage difference than the voltage
differences for other nodes in the channel. Therefore, in the following discussion, only the voltage difference Ve is taken
into consideration.
ForVgswinging from−15 to 15 V, the simulation result of
Ve is shown in Fig. 3(a). The operation of TFT can roughly be separated into the channel and the depletion regions by threshold voltageVTH, as shown in Fig. 1. WhenVg rises in the depletion region, Ve follows the change of Vg owing to
TAI et al.: ANALYSIS OF POLY-Si TFT DEGRADATION UNDER GATE PULSE STRESS USING SLICING MODEL 983
carrier number. As the gate voltage goes above VTH, the
channel is formed, and Ve is quickly discharged to zero,
such that the lateral field is too low to speed up the carriers. Therefore, although for differentTRthe coupling effect would
lead to the different Ve in the channel, once the gate voltage
goes aboveVTH, the voltage in the channel would be quickly
discharged regardless of the value ofTR. Hence, the mobility
degradation is independent of TR. For the period of gate
voltage aboveVTH, the channel is of low resistance, and thus,
Ve remains zero. As the gate voltage falls to the depletion region, Ve is coupled to a large negative value by Vg. The negativeVe is then slowly charged toward the ground during
T_VGL. The lateral voltage difference at the TFT edge may be
so high that the carriers can gain energy to become hot carriers, resulting in the mobility degradation. The coupling magnitude of this transient electrical field becomes larger with shorterTF,
resulting in theTF dependence of the mobility degradation.
On the other hand, for the gate voltage swinging from
−15 to 0 V, since the gate voltage is all below VTH, TFT
is always in the depletion region. Consequently, as the gate voltage swings for both rise and fall,Veis coupled byVG, as
shown in Fig. 3(b). Because the gate voltage is always below
VTH and the channel voltage cannot be quickly discharged, this coupled Ve would be discharged slowly during T_VGH
and T_VGL, such that carriers may obtain high energy and cause the device degradation. Since the coupled magnitude of
Ve is concerned with the changing speed ofVg, the mobility
degradation is accordingly dependent onTRandTF.
The aforementioned discussion takes two factors into consideration: the transient lateral electrical field at the edge of the sliced TFTVeand the current flow through the edge of the
sliced TFT under the voltage differenceVe. In order to describe
the degree of the degradation, a new indexΠ calculated from the simulation result is further introduced, which is given as
Π = 1 Ti Ti Ve• Cox • d(Vg− Ve) dt • dt
where Ti corresponds toTR,TF,T_VGH, andT_VGL, and Cox
is the gate capacitance per unit area. This index accounts for two factors mentioned above. The term Cox∗d(Vg− Ve)/dt
rep-resents the displacement current of the capacitor. Because the devices are fabricated on the glass substrate, the current could not flow to the bulk electrode and may only therefore flow to the source/drain region, becoming the lateral current along the channel. ForTRandTF in the depletion region,Vefollows the
change ofVg; thus,Vg− Veis kept constant, and its time
differ-entiation is zero. Therefore, in the timeT_VGHandT_VGL, the
coupling magnitude ofVeand its duration dominate the value ofΠ. The mobility degradation (1 − µ/µ0) versus the index Π
under different ac stress conditions are plotted in Fig. 4. The fair linearity exhibits the validity of the proposed mechanism.
IV. CONCLUSION
For ac stress with the gate voltage toggling between
−15 and 15 V, it is observed that the degradation depends on
Fig. 4. Mobility degradation(1 − µ/µ0) versus the proposed index Π.
the falling time TF of the gate pulse but does not depend on the rise timeTR. However, for the gate voltage swinging from
−15 to 0 V, it is observed that the degradation is both influenced
byTRandTF. A slicing method is used for the simulation of channel voltage distribution and charge change at the edge to explain the degradation behaviors. A new indexΠ is introduced to estimate the degree of the degradation. The mobility degra-dation and the index Π show linear dependence universally for various gate pulse stress conditions. The linear dependence gives the indexΠ a potential modeling for reliability simulation and lifetime prediction of poly-Si TFT circuitry.
ACKNOWLEDGMENT
The authors would like to thank Cadence for the technical support in the usage of simulation tools.
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