Abstract—A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic per-formance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 750 m2. It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply.
Index Terms—Background calibration, current-steering, D/A converters, digital random return-to-zero (DRRZ), digital-analog conversion, digital-to-analog converter (DAC), return-to-zero (RZ).
I. INTRODUCTION
T
HE current-steering digital-to-analog converts (DACs) can achieve high sampling rate, and thus are com-monly used in generating high-frequency signals [1]–[8]. Fig. 1 shows a generic current-steering DAC. It consists of equally-weighted current cells. Each current cell contains a current source of output current, a MOSFET pair functioning as a current switch, and a digital latch controlled by a clock CK. The complementary outputs of the latch control the current switch, directing the current to either the load at or the one at . A decoder converts the DAC digital input into thermometer-code signals , where . We define the signal as a binary value of either or . Fig. 1 illustrates the DAC differential non-return-to-zero (NRZ) output waveform . The has a step size of and a voltage range between and . The DAC static linearity, specified as differential nonlinearity (DNL) and integral nonlinearity (INL), is mainly determined by the matching of among different current cells and theManuscript received April 07, 2011; revised May 30, 2011; accepted July 29, 2011. Date of publication September 19, 2011; date of current version November 23, 2011. This paper was approved by Guest Editor Yiannos Manoli. This research was supported by the National Science Council of Taiwan, R.O.C., under Grant NSC-98-2221-E-009-131-MY2.
W.-H. Tseng was with the Department of Electronics Engineering, National Chiao-Tung University, Chu, Taiwan, and is now with Mediatek Inc., Hsin-Chu, 30078, Taiwan (e-mail: buz.ee91g@nctu.edu.tw).
C.-W. Fan was with the Department of Electronics Engineering, National Chiao-Tung University, Hsin-Chu, Taiwan, and is now with Mediatek Inc., Hsin-Chu 30078, Taiwan.
J.-T. Wu is with the Department of Electronics Engineering, National Chiao-Tung University, Hsin-Chu 300, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2011.2164302
Fig. 1. Current-steering DAC.
output resistances of the current sources. The cascode technique is usually used to increase the output resistance of a current source. The dimension of the transistors in the current sources must be large enough to ensure good matching [9]. There are techniques that can relax the device matching requirements, including calibration [10]–[15] and the dynamic element matching [16].
Besides static linearity, dynamic performance is also crucial for a high-speed DAC. The DAC dynamic performance is manifested as spurious-free dynamic range (SFDR) degrada-tion shown in the output spectrum of when the input is a single-tone sinewave. As for a DAC with poor dynamic performance, its SFDR decreases rapidly with increasing input frequency. The DAC dynamic performance is related to the switching operation of the internal current switches. It induces the code-dependent switch transient (CDST) effect [17]–[19] and the code-dependent loading variation (CDLV) effect [7], [8], [20], [21].
This paper describes a 12-bit 1.25-GS/s current-steering DAC [22]. We employ the digital random return-to-zero (DRRZ) technique [23] to mitigate the CDST effect and relax the matching requirement for current switches. The DRRZ operation also enables a current-cell background calibration. The calibration relaxes the device matching requirements for the current sources, allowing a more compact design of the current cells. The compact current cell design directly reduces the CDLV effect. The DAC was fabricated using a standard 90 nm CMOS technology. At 1.25 GS/s sampling rate, this DAC chip achieves a SFDR better than 70 dB up to 500 MHz input frequency.
Fig. 2. Code-dependent switching transient (CDST).
The rest of this paper is organized as follows. Section II discusses the design considerations for the DAC. Section III describes the DAC architecture and the current cell design. Section IV introduces the proposed current-cell background calibration and its related circuits. Section V shows the experimental results. Section VI draws conclusions. The Appendix analyzes the calibration operation under a finite DAC output-port bandwidth.
II. DESIGNCONSIDERATIONS
Consider the DAC shown in Fig. 1. Its static linearity, as man-ifested by DNL and INL, is determined by the matching of the current sources among the current cells. Its dynamic perfor-mance, as manifested by SFDR versus input frequency, is de-graded by the CDST and CDLV effects. In the following sub-sections, CDST and CDLV are explained. Techniques to miti-gate their effects are proposed.
A. Code-Dependent Switching Transient (CDST)
Fig. 2 shows the operation of a single current cell. The current cell contains a current source and a MOSFET current switch M1–M2. Upon the rising edge of clock CK, the binary input is loaded into the latch. Its two complementary outputs, and , drive the current switch, directing the current to either output node or output node . Fig. 2 also shows the transient response of the differential output current
. The output current is a combination of an ideal tran-sient response and switching trantran-sients. Switching trantran-sients occur only when varies. There are several sources for switching transients [17], including switch feedthrough through the current switch, timing skew of CK, finite rise/fall time of and , and voltage fluctuation at the common-source node .
Current cells exhibit mismatches in switching transients due to 1) device variations in both the current switch and the latch; 2) CK timing skew mismatches among current cells. The switching transients from all current cells are summed up at the DAC port. Depending on the sequence, the sum-mation of the switching transient mismatches becomes a non-linear term, resulting in harmonic distortions. This is called the code-dependent switching transient (CDST) effect.
Fig. 3. Digital random return-to-zero (DRRZ) operation.
To reduce the switching transient mismatch, the and waveforms must be carefully designed. Adding a cascode stage to the current switch is also a common practice to reduce the feedthrough of and to the outputs. Matching among current switches, latches, and CK routes must be considered in the design. Voltage return-to-zero (RZ) techniques [12], [14], [17], [24] or current RZ techniques [4], [5], [16], [25] can hide the switching transients from the DAC output; thus, lessen the CDST effect. Modifying the current-cell switching operation can also mitigate the CDST effect. These tech-niques decouple the sequence of the switching transients from the input sequence. The switching transients then ap-pear as noise instead of distortions at the DAC output [16], or they become out-of-band signals [2], [26]. Another tech-nique is dynamic-mismatch mapping [27] which optimizes the cell-selecting sequence to minimize the CDST effect without increasing the random noises.
This work employs the digital random return-to-zero (DRRZ) technique [23] to eliminate the CDST effect. The DRRZ ran-domizes the switching transient sequence by forcing a RZ oper-ation. Fig. 3 shows its operoper-ation. When CK is high, the DAC is in the data phase. The DAC decodes the digital input , sets up its internal current switches through , and generates an analog output corresponding to . When CK is low, the DAC is in the zero phase, in which the DAC arranges its internal current switches in such a way that the output . When the DAC is in phase, the output current of each current cell is dictated by a binary signal
. A pseudo random number generator (PRNG) gener-ates such that . Due to the insertion of the zero phases, the switching transients no longer have dependency, and they no longer induce harmonic distor-tion [23].
Comparing to other techniques, the overhead of the DRRZ is entirely in the digital domain. The DRRZ arranges the DAC cur-rent cells such that the total DAC output curcur-rent is zero during the phases. It does not demand the DAC output voltage returning to zero in every phase. The DRRZ random-izes the operations of current switches regardless of . The
Fig. 4. Code-dependent loading variation (CDLV).
switching transients are not hidden from the output. The re-sulting sequence of switching transient mismatches appear as random noise instead of distortion at the DAC output.
B. Code-Dependent Loading Variation (CDLV)
Fig. 4 shows another source of harmonic distortion. Each cur-rent cell is modeled as an ideal switch on top of an ideal curcur-rent source in parallel with a resistor and a capacitor . The resistor and capacitor represent the resistance and capac-itance variations by looking into one of the current cell output terminal while the current switch switches from one position to the other. Both and are connected to either the node or the node, depending on the state of the switch. As a result, the total loadings for output nodes and vary with dig-ital input . This code-dependent loading variation (CDLV) effect introduces harmonic distortion in the differential output . When is a sinewave, the third-order har-monic distortion caused by the CDLV effect is [7], [8], [20], [21] (1) where is the total number of current cells, is the differential resistance of the DAC output loads, and is the output impedance of a single current cell, where
.
Increasing and reducing can mitigate the CDLV ef-fect. Adding cascode stage to a current source increases . In most high-speed designs, the CDLV effect at high frequencies is dominated by . The capacitance is determined by the device dimensions of the current switch and the current source, while the device dimensions are governed by the matching re-quirements. The CDLV effect can be mitigated by adding a cas-code stage to the current switch in each current cell [3], [7], [28]. Adding constant bias currents to the cascode stage can further reduce the code-dependent effect [7].
For this work, instead of adding additional cascode stages, we simply use smaller devices for both the current sources and the current switches to reduce . Smaller devices lead to larger mismatches. However, due to the use of DRRZ, the matching requirement for the current switches is relaxed. The mismatches among the current sources are corrected by the current-cell background calibration described in Section IV.
Fig. 5. Segmented 12-bit DAC.
III. DAC ARCHITECTURE
Fig. 5 shows the 12-bit DAC architecture. The DAC is seg-mented into a 6-bit equally-weighted MSB DAC (M-DAC) and a 6-bit binary-weighted LSB DAC (L-DAC). The differential output currents from both the M-DAC and the L-DAC are tied together and connected to two external resistive loads and to produce the differential output voltage . The M-DAC comprises 63 identical current cells. Each current cell is designed to output a nominal current of , where is the DAC unit current. The L-DAC comprises 7 current cells which output a current of , , , , , , and respectively. There are two current cells in the L-DAC so that a differen-tial output of zero can be realized. In our design, . If , and then has a voltage range of 0.8 .
The DAC employs the DRRZ operation described in Section II-A. As shown in Fig. 5, each current cell contains a multiplexing latch (MUX-Latch). When CK is high, the DAC is in the data phase. The th M-DAC current cell selects the control signal from the decoder, and the th L-DAC current cell selects the control signal. The combination of the equally-weighted and
Fig. 6. Pseudo random number generator (PRNG).
Fig. 7. Schematic of thejth M-DAC current cell.
binary-weighted reflects the value of . When CK is low, the DAC is in the zero phase. The th M-DAC current cell selects the control signal from a pseudo-random number generator (PRNG). The entire L-DAC is treated as a single MSB current cell. Its current cells select the same control signal. Since , the DAC differential output current is zero during the zero phase.
Fig. 6 shows the PRNG schematic. It is a 32-bit linear feed-back shift register. The 32 outputs from the register, where , and their complementary outputs, , form the 64 control signals, such that . The switch box shown in Fig. 6 is used to rearrange the connections from and to . The rearrangement is required by the background calibration described in Section IV.
As shown in Fig. 5, there are two separate current sources in each M-DAC current cell. One current source provides an output current of . The current may vary due to device mismatches. The other current source provides an output current of . The calibration described in Section IV adjusts so that the total output current of a M-DAC current cell is .
Fig. 7 shows the circuit schematic of the th current cell in the M-DAC. MOSFETs M11–M18 and four inverters form a level-sensitive MUX-Latch. When CK is high, the input is loaded into the latch. When CK is low, the input is loaded into the latch. The MUX-Latch is operated under a 1.2 V supply. MOSFETs M5 and M6 together function as a current switch. MOSFETs M1 and M3 form a cascode current source with a
TABLE I
DIMENSIONS OFMOSFETS IN THEM-DAC
fixed current of . MOSFETs M2 and M4 form another cas-code current source whose output current is mirrored from the current input. Both current sources are operated under a 2.5 V supply. M1–M6 are MOSFETs with thick gate oxide. Device dimensions are listed in Table I. Current mirrors MC1–MC6 are also thick-gate MOSFETs. The level converter shown in Fig. 7 converts the MUX-Latch complementary outputs of 1.2 V swing into signals of 2.5 V swing to drive the M5–M6 current switch. Each signal path in the level converter is a cascade of three in-verters. The supply voltage for the last inverter is 2.5 V.
Fig. 8 shows the M-DAC current cell layout. The dimension is 80 15 m . From post-layout simulations, we obtain
and fF. Note that M5 and M6 of the current switch are biased in the saturation region when they are turned on. From (1) with and , the HD3 due to the CDLV effect is less than 70 dB if the input frequency is lower than 560 MHz.
Consider only the M1 and M2 current sources of the current cell shown in Fig. 7. Its total output current exhibits a stan-dard deviation of due to device variation, where is the LSB current of the DAC. To achieve 12-bit resolution
Fig. 8. M-DAC current cell layout.
Fig. 9. Zero-phase current-mismatch modulation.
and an INL less than 0.5 LSB, is required. The calibration described in the next section is used to meet the re-quirement.
IV. CURRENT-CELLBACKGROUNDCALIBRATION
The output current variation of the M-DAC current cell shown in Fig. 7 with the device dimensions listed in Table I does not meet the resolution requirement due to the device variation. In this work, we use background calibration to correct the current variation.
Fig. 9 shows the proposed calibration principle. The total L-DAC current is . There are 63 M-DAC current cells whose currents are to , respectively. The calibration chooses as a reference and adjusts to make , where . The M-DAC and the L-DAC execute the regular DRRZ operation described in Section II-A. During the zero phase, all M-DAC current cells and the L-DAC are controlled by from the PRNG. The output current of the entire L-DAC is . The output current of the th M-DAC current cell is . When the th M-DAC current cell is under cali-bration, the switch box shown in Fig. 6 rearranges its zero-phase control such that
(2) The DAC total output current in the zero phase can be expressed as
(3)
The current mismatch is modulated by . The calibration can extract from by using cor-relation. Once is acquired, it is used to correct . The goal is to make approach zero. The calibration proceeds se-quentially. It calibrates all 63 M-DAC one cell at time.
Fig. 10 shows the block diagram of the entire DAC, including its calibration signal path. The differential output currents from
both M-DAC and L-DAC are tied together and connected to and to generate the differential output voltage
. When the th M-DAC current cell is under calibra-tion, the modulated current mismatch is embedded in during the zero phase. The DAC output is sampled and processed by a chopper followed by a low-pass filter (LPF)
to extract , yielding . The voltage
is digitalized by an incremental delta-sigma modulator (DSM) [29]. The resulting digital code is used to adjust the th calibra-tion DAC (C-DAC). Its output current adjusts the th current cell in the M-DAC, , to make approach zero.
Fig. 11 illustrates various signal waveforms in the calibra-tion signal path. When CK is low, the DAC output voltage during the zero phase is sampled, yielding . And when CK is high, . Voltage is correlated with by a chopper. The output of the chopper can be expressed as
. A LPF produces the averaged value of , yielding . A continuous-time DSM is used to digitize . The DSM operates at 1/16 of the CK frequency. It produces an one-bit digital stream . The dec-imation filter (DF) following the DSM is an accumulator that dumps its content every samples. The DF output is a digital representation of . The digital code is then scaled into . The value of is . Fig. 12 shows the -to- mapping function. The is added to the content of the th accumulator (ACC). There are 63 ACCs. Their outputs, , control 63 calibration DACs (C-DACs) respectively. Each C-DAC is a 7-bit current-steering DAC with a resolution of . For the th C-DAC, its output is . The current
adjusts the output of the th M-DAC current cell, . Fig. 13 shows the schematic of the calibration analog signal path. MOSFETs M1–M4 form the sampler. When CK is high, the and nodes are connected to a common-mode voltage, . MOSFETs M5–M8 form the chopper. The RC pairs, – and – , are the LPFs with a band-width of 26.5 kHz. The LPF output, , is converted to cur-rent by a transconductor , and then integrated by the following DSM. Both the transconductor and the opamp are simple folded-cascode opamps. The DSM is operated at a clock frequency of 78.125 MHz. The internal feedback in the DSM is a one-bit current-steering DAC with an output current of . The DSM can resolve a current mismatch
as large as . A of corresponds
to a .
The calibration path shown in Fig. 13 includes a transcon-ductor and an opamp. They exhibit offsets due to device mismatches, which introduce errors in the DSM measurements. Assume the 1st M-DAC current cell is under calibration. During
Fig. 10. DAC block diagram.
the zero phase, is modulated by and is mod-ulated by . Neglecting the DSM conversion gain, the cor-responding digital output can be expressed as
(4) The offset must be removed from the measurement data. To find the offset, an additional calibration measurement is performed at the beginning of each calibration cycle. During the zero phase of this measurement, is modulated by and is modulated by . The resulting digital output can be expressed as
(5) Thus, the offset is obtained by applying . This acquired offset is subtracted from the subsequent measurement data. Every calibration cycle includes one offset measurement and 63 mismatch measurements. The acquired offset is updated in every calibration cycle.
As shown in Fig. 11, due to the finite bandwidth of the port, the sampled signal contains the return-to-zero tails of . They are scrambled by and suppressed by the following LPF and DF. The effects of finite output-port bandwidth on the calibration are analyzed in the Appendix. The return-to-zero tails are treated as noise that induce calibration errors. The cal-ibration errors can be reduced by increasing the DF down-sam-pling ratio. For this design, consecutive data are accu-mulated for every . This DF down-sampling ratio allows an output-port bandwidth as low as 100 MHz.
With a DF down-sampling ratio of , one calibration mea-surement takes 3.34 msec. Since one calibration cycle requires 64 measurements, it takes 214 msec to complete one calibra-tion cycle. During power up, it takes 9 calibracalibra-tion cycles or 1.93 sec for the calibration to converge if the initial M-DAC current cell mismatches are as large as . After that, the cali-bration only needs to track the environmental variations, such as supply voltage and temperature variations. Although not imple-mented in this design, the calibration time for the initial power up can be reduced by setting input . And then the DF down-sampling ratio can be reduced.
V. EXPERIMENTALRESULTS
The DAC was fabricated using a standard 90 nm CMOS tech-nology. All functional blocks shown in Fig. 10 are integrated, except the resistive loads and . Fig. 14 shows the chip photograph. The DAC core area is 1100 750 m . The chip also includes a direct digital frequency synthesizer (DDFS) to generate digital inputs for DAC dynamic testing. The synthe-sizer also generates ramp waveforms for DNL and INL mea-surements.
The measured DNL and INL before calibration is shown in Fig. 15. In our design, the device dimensions and bias condi-tions for the L-DAC current cells are different from those for the M-DAC current cells. In addition, this DAC floor plan does not employ common-centroid scheme to reduce the gradient ef-fects. As a result, the raw DNL and INL are poor. The DNL is / LSB and the INL is / LSB. Fig. 15 shows the measured DNL and INL after current-cell calibration. The DNL is improved up to / LSB and the INL is im-proved up to / LSB.
Fig. 17 shows the measured DAC full-scale transient re-sponse. The 10%-to-90% rising time is 0.5 nsec, which corresponds to an output-port bandwidth of 700 MHz. This bandwidth does not hinder the DRRZ and the current-cell calibration.
The DAC output spectra are measured during the single-tone tests. The DAC is operated at 1.25 GS/s sampling rate. Fig. 18 shows the output spectrum when the input frequency is 40 MHz. The DAC is calibrated, and the DRRZ is turned off. The SFDR is 73.3 dB. At low input frequency, the CDST effect is low. The SFDR is dictated by the DAC static linearity. In this design, the static linearity is achieved by calibration. Fig. 19 shows the DAC output spectrum with the input frequency increased to 477 MHz. The SFDR is degraded to 58.8 dB by the CDST effect. Fig. 20 shows the DAC output spectrum with the DRRZ enabled. The SFDR recovers to 73.6 dB. The DRRZ mitigates the CDST ef-fect.
Our DAC is designed to operate with each of its outputs con-nected to a 25 resistive load. However, in the above output spectrum measurements, a spectrum analyzer (SA) is connected to the DAC via a transformer, similar to the output-port con-figuration of [16]. In this setup, each of the two DAC output
Fig. 11. Various waveforms in calibration signal path.
Fig. 12. D -to-D mapping function.
terminals is connected to a 25 resistor. The other end of the resistor is connected to the supply. The SA adds an additional 50 load connected to the DAC differen-tial output. The DAC can deliver a full-range current of 16 mA to either of its output terminals. In the non-return-to-zero (NRZ) configuration, the DAC can generate a low-frequency full-range sinewave of 4 dBm power to the SA, as shown Fig. 18. In the DRRZ configuration, the DAC can only generate a sinewave of 10 dBm to the SA. However, the sinc droop of a DRRZ DAC is less severe than that of a NRZ DAC [17]. In Figs. 19 and 20, the input frequency is 477 MHz, the resulting signal power is 8.5 dBm for the NRZ DAC and 12.5 dBm for the DRRZ DAC. The power loss due to the NRZ sinc droop is 2.2 dB, and the loss due to the RZ sinc droop is 0.5 dB. The loss due to the 700 MHz output-port bandwidth is 1.6 dB.
Several sources contribute to the random noise at DAC output. They are estimated as follows. 1) The total quantization noise power is . Assume the signal bandwidth is 625 MHz. The current power
den-sity is Hz. The
corre-sponding noise spectral density (NSD) received by the SA is dBm/Hz. 2) The current sources in the DAC exhibit device thermal noise. From
simula-tion, the total DAC output current thermal noise density is Hz. The corresponding NSD received by the SA is dBm/Hz. 3) Com-paring Figs. 19 and 18, the power increase in the harmonics is as input frequency is increased. As-sume is induced entirely by the CDST effect, and it is spread from 0 Hz to by the DRRZ. The resulting NSD
is dBm/Hz. The SA in our
measurement setup has a noise floor of 140 dBm/Hz by itself. As detailed in the Appendix, once settled, the current-cell calibration in our design does not introduce noise to the DAC output.
Fig. 21 shows the measured SFDR versus input frequency. If the DAC is not calibrated, the SFDR exhibits no significant change when varying the input frequency. The DAC static lin-earity dominates the SFDR performance. Once the DAC is cal-ibrated, and if the DRRZ is turned off, the CDST effect is the main source of SFDR degradation. When the DAC is calibrated and the DRRZ is turned on, the SFDR is better than 70 dB for input frequencies up to 500 MHz. Also shown in Fig. 21 is the CDLV effect calculated with (1). In this design, the CDLV ef-fect becomes relevant only when the input frequency is higher than 550 MHz.
Fig. 13. Schematic of the calibration analog signal path.
Fig. 14. Microphotograph of the DAC.
Fig. 15. Measured DNL and INL before current-cell calibration.
Fig. 22 compares the SFDR performance of several high-speed DACs of which the sampling rate is higher than 0.5 GS/s and the resolution is better than 12 bits. Table II lists their speci-fications. In Table II, is the sampling rate, is the maximum output current, is the low-frequency sinewave power de-livered to the DAC output load, is the SFDR at low
Fig. 16. Measured DNL and INL after current-cell calibration.
Fig. 17. Measured DAC full-scale transient response.
input frequency, and is the SFDR at input fre-quency. The figure of merit (FOM) is defined as
(6)
where and
Fig. 18. Measured DAC output spectrum after calibration but without DRRZ. Sampling rate is 1.25 GS/s. Input frequency is 40 MHz.
Fig. 19. Measured DAC output spectrum after calibration but without DRRZ. Sampling rate is 1.25 GS/s. Input frequency is 477 MHz.
for DAC comparison [8]. None of the existing definitions is uni-versally endorsed. The FOM of (6), first defined in [30], includes the DAC dynamic performance at high input frequency.
VI. CONCLUSION
The static linearity of a current-steering DAC is governed by the matching of its internal current sources. Its dynamic perfor-mance is degraded by both the code-dependent switching tran-sient (CDST) effect and the code-dependent loading variation (CDLV) effect. The random return-to-zero (DRRZ) operation can eliminate the CDST effect. Adopting a compact current cell design can mitigate the CDLV effect. The DRRZ also facili-tates a current-cell background calibration scheme that can
cor-Fig. 20. Measured DAC output spectrum after calibration and with DRRZ. Sampling rate is 1.25 GS/s. Input frequency is 477 MHz.
Fig. 21. Measured SFDR versus input frequencies.
Fig. 22. SFDR performance comparison.
rect the mismatches among DAC internal current sources due to device variations. We designed a CMOS 12-bit 1.25-GS/s cur-rent-steering DAC to demonstrate the above design techniques. As a result, the DAC achieves a SFDR better than 70 dB up to 500 MHz input frequency.
APPENDIX
CALIBRATIONUNDERFINITEOUTPUT-PORTBANDWIDTH
Consider the current-cell background calibration scheme shown in Fig. 10 and the related waveforms shown in Fig. 11. Let two capacitors and be in parallel with the two output resistors and respectively, resulting in a finite
output-port bandwidth of , where ,
, and . The differential
DAC output is tracked in every zero phase, yielding . Assume the DAC is switched from the data phase to the zero phase when . Then, for can be expressed as
(7) where is the steady-state value in the zero phase and is the value at . In (7), con-tains the current mismatch information , while
is the calibration noise to be suppressed by the calibration. If the output-port bandwidth is reduced by increasing , the mis-match information embedded in is decreased and the calibra-tion noise is increased.
As shown in Figs. 10 and 11, the pulses are modulated by the chopper, yielding . Let nsec be the DAC sampling interval and be the zero-phase interval with 50% duty cycle. The average of is the desired mismatched information, which can be expressed as
(8) where
(9) is the calibration conversion gain for the mismatch . If the output-port bandwidth is 700 MHz, then nsec
and .
Fig. 23 shows the worst-case calibration noise, in which are pulses to approximate the term in (7). Let
in every zero phase as the worst-case scenario. The pulse magnitude illustrated in Fig. 23 is
found by equating the pulse power to the averaged power of . We have
(10) where
(11)
If nsec, then .
The pulses are randomized by the sequence, yielding the pulses. The power spectral density of , denoted as , can be found in [31]. As shown in Fig. 10, the pulses are filtered by a low-pass filter (LPF) with a band-width kHz. The residual power of the calibration noise at the LPF output can be found as
(12)
where is the LPF transfer function.
This is further reduced by the decimation filter (DF) shown in Fig. 10. Let be the DF down-sampling ratio. To make the measurement perturbation caused by the calibration noise less than the DAC resolution, , we want
(13) Thus, the requirement for is
(14) If the output-port bandwidth is 700 MHz and nsec, then the calibration requires a DF down-sampling ratio
. In our design, . Thus, the calibration can still function under nsec, i.e., an output-port bandwidth as low as 100 MHz.
The calibration noise yields a variation in the DF output, de-noted as in Fig. 10. From (12), with , the vari-ance of can be found as
. As shown in Fig. 10, is the transconductance converting to current and
The authors thank Faraday Technology Corp., Hsin-Chu, Taiwan, for engineering support and United Microelectronics Corp., Hsin-Chu, Taiwan, for chip fabrication.
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Wei-Hsin Tseng received the B.S. degree in elec-trical engineering from National Cheng-Kung Uni-versity (NCKU), Tainan, Taiwan, in 2002. From 2002 to 2011, he pursued the M.S. and Ph.D. degrees in electronics engineering at National Chiao-Tung Uni-versity (NCTU), Hsinchu, Taiwan. He received the Ph.D. degree in 2011.
Since 2010, he has been working at MediaTek Inc. where he is responsible for the design of analog and mixed-signal ICs. His current research interest is high-speed high-resolution data converters.
Chi-Wei Fan was born in Hsin-Chu, Taiwan. He re-ceived the B.S degree in electrical engineering from the National Central University, Chung Li, Taiwan, in 2000. From 2001 to 2010, he worked toward the Ph.D. degree in electronics engineering at National Chiao-Tung University, Hsin-Chu.
His research interests are mixed-signal, high-speed, and high-resolution integrated cir-cuits. Since 2010, he has been working at MediaTek Inc. where he is engaged in the design of analog and mixed-signal ICs.
