Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode

Low temperature MOSFET technology

with Schottky barrier source/drain, high-K gate dielectric

and metal gate electrode

Shiyang Zhu

, H.Y. Yu

, J.D. Chen

, S.J. Whang

, J.H. Chen

, Chen Shen

,

Chunxiang Zhu

, S.J. Lee

, M.F. Li

, D.S.H. Chan

, W.J. Yoo

,

Anyan Du

, C.H. Tung

, Jagar Singh

, Albert Chin

, D.L. Kwong

a

Silicon Nano Device Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, Singapore, 119260 Singapore

b

Institute of Microelectronics, Singapore 117685 Singapore c

Department of Microelectronics, Fudan University, Shanghai, 200433, China d

Department of Electronics Engineering, National Chiao Tung University, Hsinchu, 300 Taiwan, ROC e_{Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712, USA}

Received 10 December 2003; accepted 15 March 2004

Abstract

Both P- and N-channel MOSFETs with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420
C. PMOSFETs with PtSi S/D show excellent electrical performance of an Ion=Ioff
107108

and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi2xS/D have
3 orders of magnitude larger Ioffthan that of PMOSFETs and show two slopes in

the subthreshold region, resulting in the Ion=Ioff
105at low drain voltage. It can be attributed to the relatively higher

barrier heightðUnÞ of DySi2x/n-Si than that of PtSi/p-SiðUpÞ and the rougher DySi2xfilm. Adding a thin intermediate

Ge layer (
1nm) between Dy and Si can improve the film morphology significantly. As a result, the improved per-formance of N-MOSFET is observed.

 2004 Published by Elsevier Ltd.

1. Introduction

To scale down metal-oxide-semiconductor field effect transistors (MOSFETs) to tens of nanometers, several essential problems should be overcome or lessened, such as the large direct tunneling current of ultra-thin gate oxide, the depletion and boron diffusion of the poly-Si gate electrode, and the difficulty to form ultra-shallow source/drain (S/D) junctions with low resistance, etc.

High-K gate dielectric [1] and metal gate [2] have been used to overcome the first two problems. For the third problem, Schottky barrier silicide S/D structure [3,4] is a potential solution because silicide/Si has an atomic abrupt interface, the ultra-shallow S/D Schottky junc-tion can be easily and accurately formed, and the par-asitic resistance of the totally silicidized S/D is much lower than that of conventional heavily doped S/D. Moreover, the Schottky barrier Source/Drain Transistor (SSDT) eliminates S/D doping and subsequent anneal-ing procedures, the fabrication process is inherent low temperature and simple, those are benefit for high-K dielectrics and metal gate electrodes because they may be degraded by high temperature treatment [5]. Therefore,

*

Corresponding author. Tel.: +65-6874-2559; fax: +65-6779-1103.

E-mail address:elelimf@nus.edu.sg(M.F. Li).

0038-1101/$ - see front matter  2004 Published by Elsevier Ltd. doi:10.1016/j.sse.2004.05.045

it is very attractive to integrate high-K dielectric, metal gate and silicide S/D using a low temperature process.

However, SSDT usually suffers from a large leakage current and a low Ion=Ioff ratio [6–8]. Carriers from

source to channel should transport over a Schottky barrier height ðUn for NSSDT, and Up for PSSDT),

which behaves as an additional resistance between source and drain, thus reduces the drain on currentðIonÞ.

Higher Ion needs smaller barrier height. On the other

hand, drain to substrate forms a reverse-biased Schottky diode. The diode reverse current dominates the MOS-FET off currentðIoffÞ, which depends exponentially on

the barrier height (Upfor NSSDT, and Unfor PSSDT).

Smaller off current needs higher barrier height. Because the sum of Un and Up equals approximately to the

en-ergy bandgap Eg, i.e., Unþ Up Eg (1.12 eV for Si),

requirements to increase Ion and decrease Ioff need a

silicide with barrier height Un as low as possible for

NSSDT, and vice versa for PSSDT. In literature, erbium and platinum silicides are usually used for N and P-channel MOSFETs, respectively, [6,7,9,10] because rare earth (RE) metal silicides have the lowest barrier height while PtSi has the second highest barrier height among the known silicides [11]. However, the electrical perfor-mance of the reported NSSDT is not as good as that of PSSDT because the barrier height of ErSi2xis not low

enough and the formed RE silicide film by solid-state reaction of deposited RE metal and sub-Si is quite rough [12]. This is the critical obstacle of the usage of SSDT technology.

2. Device fabrication

Si (1 0 0) wafers of both n- and p-type with resistivity of 4–8 X cm were used as the starting substrates. After a standard RCA clean and diluted HF (DHF) solution dipping, a
6 nm HfO2 film was deposited at 400
C

using Hf[OC(CH3)3]4 and O2 in a MOCVD system,

followed by an in situ post-deposition annealing in N2

ambient at 700
C to improve the film quality. Then, a HfN (
50 nm)/TaN (
100 nm) stack was deposited as a metal gate in a sputtering system with a base pressure of
1.4 · 107 _{torr at room temperature, where TaN is}

used as a capping layer to reduce the gate sheet resis-tance (
10 X/sq.). The wafers were patterned using standard photolithography and reactive ion etching (RIE) procedures to etch the TaN/HfN/HfO2 stack.

Immediately after DHF dipping to remove the native oxide in the S/D region, the patterned wafers were loaded into the sputtering system again to deposit Pt (
100 nm, for PSSDT) or Dy (
100 nm)/HfN (
70 nm) stack (for NSSDT). Silicidation of Pt or Dy was per-formed by a furnace forming gas anneal at 420
C for 1 h. Since Dy, as well as other RE metals, can be easily oxidized during ex situ anneal, a capping layer of

ther-mally stable HfN [2] is used to prevent Dy oxidization during the annealing. The un-reacted Pt was etched in a hot diluted aqua regia solution, while the HfN capping layer and the un-reacted Dy were removed by DHF and diluted HNO3solutions sequentially.

3. Results and discussion

Fig. 1(a)–(c) show the cross sectional transmission electron microscopy (XTEM) image, the gate leakage current and the C–V curves of the HfN/HfO2/Si stack,

respectively. The effective oxide thickness (EOT) can be deduced using the quantum mechanical (QM) model from the C–V curves. The EOT is between 1.5 and 2.0 nm for all of the MOS-capacitor samples measured where the XTEM image shows that HfO2 has been

partly crystallized. For comparison, the gate leakage of a MOS-capacitor device which has the same stack made by the same process but with an additional 950
C 30 s anneal is shown in Fig. 1(b). It has a higher gate leakage and its EOT is
2.4nm. According to gate leakage simulation [13], when scaled up to the same EOT, the device without the high temperature anneal has a 4–5 orders of magnitude lower gate leakage than that with high temperature anneal. The benefit of the low tem-perature fabrication process to the high-K dielectric quality has also been reported by other authors [5].

Fig. 2 shows the schematic and XTEM image of the cross-sectional SSDT structure formed by a simplified one-mask process. There is a ‘‘hole’’ between S/D and gate, which acts as a sidewall spacer to separate them. The ‘‘hole’’ is formed during the DHF dipping before the Pt or Dy deposition because the bottom layer (HfN) of the gate stack is horizontally etched by the DHF solution slightly, while the top layer (TaN) is not etched. The electrical characteristics of a PSSDT are shown in Fig. 3. It has excellent electrical performance with an Ion=Ioff
107 108 and a subthreshold slope of 66 mV/

dec. The off current is mainly attributed to the reverse leakage of the PtSi/n-Si Schottky contact because the drain to substrate Si forms a PtSi/n-Si diode which is always reverse biased. The I–V and C–V characteristics of the PtSi/n-Si diode are shown in Fig. 4, from which the barrier height can be deduced to be 0.84 eV (I–V ) and 0.86 eV (C–V ), respectively, with an I–V ideality factor of 1.02 and a doping concentration ðNDÞ of

1.1· 1015_cm3_{. The calculated diode saturation current}

at zero bias is about 3.8· 1012_{A for a diode with area}

of 1.0· 104 _cm2_{, in close agreement with the transistor}

off current (Fig. 3(b)).

The ‘‘hole’’ size in Fig. 2 influences the PSSDT on current significantly. Fig. 5 shows that Ionat Vds¼ 0:05

V and Vg¼ 1:5 V decreases from 0.18 to 0.10 mA with

an increase in the DHF dipping time from 60 to 105 s. A device with DHF dipping time of 5 min reduces Ionby

about 3 orders of magnitude, where a big ‘‘hole’’ be-tween S/D and gate is really observed in this case by TEM. For comparison, SSDT devices were also fabri-cated using a normal process (four-masks) with sidewall spacer thickness of 20, 50 and 100 nm, respectively. The electrical characteristics of the device with 20 nm spacer are shown in Fig. 6. Its electrical performance is similar to that fabricated by the simplified one mask process (Fig. 3) and the drain drivability decreases dramatically

with increasing the spacer thickness. Ion at Vg¼

Vd¼ 1:75 V for the device with a 50 nm spacer is only

Fig. 1. HRTEM image (a), gate leakage I–V curves (b) and C–V curves (c) of the TaN/HfN/HfO2/sub-Si MOSC structure. An additional high temperature anneal increases the gate leakage significantly.

Fig. 2. Schematic (a) and XTEM image (b) of a SSDT fabri-cated by a simplified low temperature process. A ‘‘hole’’ be-tween S/D and gate acts as a sidewall spacer to separate them.

0.0 -0.5 -1.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0

Drain current -I (A)

d Gate voltage V (V)g V_g=-0.75 V V_g=-1.00 V Vg=-1.25 V V_g=-1.50 V PtSi-PSSDT W/L=400 µm/4m

Drain current I (mA)

d Drain voltage V (V)_ds 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 V_ds=-1.0 V V_ds=-0.05 V 66 mV/dec (a) (b)

Fig. 3. Id–Vd(a) and Id–Vg(b) curves of PSSDT with PtSi S/D. The channel width and length are 400 and 4 lm, and EOT¼ 2.0 nm.

about 0.4 lA, a reduction of about 4 orders of magni-tude compared with that for the device with the 20 nm spacer. A device with 100 nm spacer shows even a smaller Ion. In summary, the above results confirm the

feasibility of our simplified low temperature process for fabrication of SSDTs.

N-SSDTs with DySi2xsilicide were also fabricated

using the same simplified one-mask process. However, the DySi2xfilm as well as other RE silicides produces a

rougher surface because the RE silicides are not formed through the layer-by-layer mode, but by the islanded-preferred mode during the solid-state reaction with the substrate Si [12]. In practice, many small square pits in the silicide surface are observed and atomic force microscope (AFM) data show that the roughnesshRmsi

of the DySi2xis about 6.5 nm for a 1· 1 lm area. No

improvement of the DySi2xfilm morphology was found

by using other capping layers, such as Pt, Ti, Ta, Ru and Al, etc., or by in situ vacuum anneal without a capping layer. Fig. 7 illustrates the I–V and C–V properties of the DySi_2x/n-Si diode. The deduced barrier heights are 0.66 and 0.88 eV from I–V and C–V , respectively. The significant difference in the barrier height values and the larger than unity ideality factorðn ¼ 1:10Þ from the I–V data imply a large barrier height inhomogeneity for the DySi2x/p-Si contact [14]. The reverse leakage current is

0.0 -0.5 -1.0 -1.5 0.00 0.05 0.10 0.15 0.20 x100 Vds=50 mV PtSi-PMOS W/L=200/2.5 µm DHF dipping time before metal-deposition: 60 sec 75 sec 90 sec 105 sec 5 min Id (mA) Vg (V)

Fig. 5. Effect on the drain drivability with an increase in the DHF dipping time. The current decreases about 3 orders of magnitude after 5 min DHF dipping.

0.0 -0.5 -1.0 -1.5 -2.0 -2.5 0 -2 -4 -6 -8 VgS (V) IDS (mA) Vd=-0.75 V Vd=-1.25 V Vd=-1.75 V IDS (A) V_DS (V) Vd=-0.25 V P-SSDT with 20 nm spacer W/L=100 µm/1 µm 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 69 mV/dec V_ds=-0.05 V V_ds=-1 V (a) (b)

Fig. 6. Id–Vd(a) and Id–Vg(b) curves of PSSDT with PtSi S/D which is fabricated using a normal 4-mask process with a sidewall spacer of 20 nm. The channel width and length are 100 and 1 lm, respectively. -1.2 -0.8 -0.4 0.0 0.4 0.8 10-5 10-4 10-3 10-2 10-1

100 DySi2-x/p-Si diode

I-V J (A/cm 2) 0.2 0.4 0.6 0.8 V (V) Φ Φ BP C-V_{=0.880 eV} N_A=2.1e15 cm-3 BP I-V_{=0.657 eV} n=1.10 100 KHz 500 KHz 1 MHz linear fit 1/C 2 (x10 8 F -2 m -4 )

Fig. 7. I–V and C–V curves for the DySi2x/p-Si diode, the barrier heights are deduced to be 0.66 and 0.88 eV from I–V and C–V , respectively, with corresponding an ideality factor n¼ 1:10 and doping concentration NA¼ 2:1  1015cm3.

-1.2 -0.8 -0.4 0.0 0.4 0.8 1.210 -8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 J (A/cm 2) I-V PtSi/n-Si diode Vg (V) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 100KHz 500KHz 1MHz linear fit 1/C 2 (x10 8 F -2 m 4 )

Fig. 4. I–V and C–V curves of the PtSi/n-Si diode, where the barrier heights are deduced to be 0.84 and 0.86 eV from I–V and C–V , respectively, with corresponding an ideality factor n¼ 1:02 and doping concentration ND¼ 1:1  1015cm3, close to the expected value.

much larger than that for the PtSi/n-Si contact and in-creases faster with increasing reverse bias voltage, showing the poor rectifying property of the DySi2x/p-Si

contact. The transistor properties for the NSSDT are shown in Fig. 8. The drain off current is about 3 orders of magnitude larger than that of PSSDT, resulting in an Ion=Ioff ratio of about 105 at the low drain bias region

(Vds¼ 0:2V). Moreover, the subthreshold curve has two

slopes,
80 mV/dec at Vg<0:23 V and
340 mV/dec at

Vg>0:23 V. These phenomena can be attributed to the

relatively large electron barrier height of DySi2x and

the rough surface morphology. The key point for the development of the N-SSDT is to reduce the electron barrier height and to improve the silicide quality.

It was reported that the RE silicide formed by co-evaporation of Si and RE metal has a good surface morphology [15]. However, it cannot be used in our process because it is not compatible with a self-aligned S/D fabrication process (the silicide above gate cannot be selectively etched). For our process, we find that adding a thin intermediate Ge layer can improve the Dy silicide film morphology significantly. No square pits were found on the surface of DySi2x formed by the

solid-state reaction of the HfN/Dy/Ge/sub-Si multilayer. The deposited amorphous Ge layer may obstruct the crystallization of DySi2x during its growth. Fig. 9

shows the I–V curves of the DySi2x/p-Si diodes with

three different thickness of Ge intermediate layer
1,
6 and
30 nm. For devices with a thin Ge intermediate layer, the barrier height is close to the reported value (0.74 eV [11]) with the ideality factor near 1, implying an improvement of the Schottky contact with the interme-diate Ge layer. However, a thick intermeinterme-diate Ge layer

0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.5 1.0 1.5 0.50 V 0.75 V 1.00 V 1.25 V V_g=1.50 V DySi_2-x-NSSDT W/L=400 m/4µm Id (A) Id (mA) V_ds (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 10-9 10-8 10-7 10-6 10-5 10-4 10-3 V_ds = 0.05 V V_sbfb 340 mV/dec 80 mV/dec V_ds = 0.20 V V_g (V) (a) (b)

Fig. 8. Id–Vd(a) and Id–Vg(b) curves of NSSDT with DySi2xS/ D. The channel width and length are 400 and 4 lm, respec-tively, and EOT¼ 1.5 nm. The subthreshold slope is S ¼ 80 mV/dec at Vg<0:23 V and 340 mV/dec at Vg>0:23 V.

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 10-5 10-4 10-3 10-2 10-1 100 Ge thickness I-V n 1 nm 0.728 eV 1.01 6 nm 0.723 eV 1.04 30 nm 0.602 eV 1.62 linear fit J (A/cm 2) Voltage (V)

Fig. 9. I–V curves of DySi2x/gp-Si diode formed from the solid-state reaction of HfN/Dy/Ge/sub-Si multilayer with dif-ferent thickness of intermediate Ge layer (
1,
6 and
30 nm) where a thinner Ge intermediate layer shows better rectifying.

0.0 0.5 1.0 1.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Ids (A) V_gs (V) Vg=0.75 V Vg=1.00 V Vg=1.25 V V_g=1.50 V N-SSDT with DySi2-x

formed with 1nm intermediate Ge layer W/L=400 m/5 µm Ids (mA) Vds (V) 0.0 0.5 1.0 1.5 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 Vds=0.20 V Vds=0.10 V Vds=0.05 V Vds=0.50 V (b) (a)

Fig. 10. Id–Vd(a) and Id–Vg(b) curves of NSSDT with DySi2x S/D, which was formed with an intermediate Ge layer (
1 nm). The channel width and length are 400 and 5 lm, respectively, the device has a lower Ioff and a higher Ion as compared to Fig. 8.

(
30 nm) will degrade the diode performance signifi-cantly as seen in Fig. 9. In addition, the sheet resistance of the silicide film increases significantly with an increase in the Ge thickness because the Ge intermediate layer delays the reaction of Dy and Si. Therefore, the inter-mediate Ge thickness should be kept small and opti-mized. The electrical performance of NSSDT with DySi2x formed by
1 nm intermediate Ge layer is

shown in Fig. 10. It has a smaller Ioff and a higher Ion

than those of the NSSDT without the Ge intermediate layer (Fig. 8). The total Ion=Ioff ratio at Vds¼ 0:2V

im-proves about 5–6 times. Further studies on the detailed effects of Ge on DySi_2xare proceeding.

4. Conclusion

A simplified low temperature process is reported integrating the use of a high-K gate dielectric, a metal gate and a Schottky barrier silicided S/D structure. A ‘‘hole’’ which is formed by the side etching of the HfN layer during DHF dipping acts as a sidewall spacer to separate the S/D and gate. PSSDTs with PtSi S/D have shown excellent electrical performance, similar to devices fabricated by a normal process with an opti-mized sidewall thickness. For NSSDTs with DySi2xS/

D, the relatively large electron barrier height ðUnÞ and

the poor silicide surface morphology result in worse electrical performance than that of the PSSDT. Adding a thin intermediate Ge layer can improve the DySi2x

silicide film, as well as the N-SSDT electrical perfor-mance.

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