Early detection of successful decoding for
dual-diagonal block-based LDPC codes
C.-Y. Lin and M.-K. Ku
A fast, successful decoding detection mechanism is proposed for dual-diagonal block-based low-density parity-check (LDPC) codes. The algorithm eliminates unnecessary parity check computation by exploit-ing the structure of dual-diagonal LDPC codes. The average number of decoding iterations can be reduced for both two-phase decoders and layered decoders with no performance degradation on the AWGN channel. Simulation results show that the proposed mechanism reduces average iterations by 10 – 15% at 1025bit error rate compared with standard parity-check equations.
Introduction: Low-density parity-check (LDPC) codes [1] have attracted much attention in the last decade owing to their capacity-approaching performance. LDPC codes with a dual-diagonal block-based structure can be encoded in linear time with lower encoder hardware complexity[2]. This class of LDPC codes is adopted by a number of standards such as wireless LAN (IEEE 802.11n)[3], wireless MAN (IEEE 802.16e, WiMAX) [4]and satellite TV (DVB-S2) [5]. LDPC codes are commonly decoded by the iterative belief-propagation (BP) algorithm. The decoder checks the parity-check equations to detect successful decoding at the end of the iteration. The Tanner graph of an irregular LDPC code consists of nodes with different degrees such that coded bits have unequal error protection[6]. Coded bits associated with higher degree nodes tend to converge to the correct answer more quickly. Hence, in order to give better protection to the transmitted data, data bits are always mapped to higher degree nodes whereas parity bits are mapped to lower degree nodes in the encoding process.
The commonly used parity-check equations Hct¼ 0twill be satisfied after all the coded bits are correctly decoded. However, as discussed above, data bits converge to the correct answer much more quickly than parity bits, so some unnecessary iterations are wasted waiting for the parity bits to be decoded. In this Letter, a new set of low-complexity check equations are derived for dual-diagonal block-based LDPC codes. Early detection of successfully decoded data can be achieved by exploit-ing the structure and degree of distribution of the dual-diagonal parity check matrix. The decoder power, speed and complexity can be improved by adopting these equations. Simulation shows that the coding gain performance is little changed.
Dual-diagonal based LDPC codes: The dual-diagonal block-based matrix H of size m n in IEEE 802.11n and 802.16e is defined as
H ¼ ½ðHsÞmkjðHpÞmm ¼ P0;0 P0;1 P0;2 P0;nb1 P1;0 P1;1 P1;2 P1;nb1 P2;0 P2;1 P2;2 P2;nb1 .. . .. . .. . . . . .. . Pmb1;0 Pmb1;1 Pmb1;2 Pmb1;nb1 2 6 6 6 6 6 6 6 4 3 7 7 7 7 7 7 7 5 ð1Þ
where Hscorresponds to data bits and Hpcorresponds to parity bits. Pi,jis either a circulant permutation matrix or a zero matrix of size z. A circulant permutation matrix is formed by circularly shifting the rows of an identity matrix to the right by several times. The matrix H is expanded from a base matrix Hb:
Hb¼ ½ðHbsÞmbkbjðHbpÞmbmb ð2Þ
where mb¼ m/z and kb¼ k/z. Each element in Hbis a nonnegative number or 21 to represent the shift quantity of the permutation matrix or a zero matrix. The structure of Hbpis further defined as
Hbp¼ ½ðtÞmb1jðhÞmbðmb1Þ ¼ d 0 d 0 0 0 0 .. . . . . . . . . . . 0 0 0 0 3 7 7 7 7 7 7 7 7 7 7 7 5 2 6 6 6 6 6 6 6 6 6 6 6 4 ð3Þ
where t is a weight-3 column and h is a dual-diagonal structure (note that d is a positive number and all blank entries are elements of 21). By exploit-ing this structure, the codeword can be encoded recursively in linear time and the encoder complexity can be reduced significantly.
Proposed early detection mechanism for successful decoding: Let s ¼ [a0a1. . .ak21] denote the data block and si¼ [aizaizþ1. . . a(iþ1)z 2 1] for i ¼ 0, 1, . . ., kb2 1 denote the data sub-block. Also, let p ¼ [b0 b1. . .bm21] denote the parity block and pi¼ [bizbizþ1. . . b(iþ1)z 2 1] for i ¼ 0, 1, . . ., mb2 1 denote the parity sub-block. All operations dis-cussed below are modulo-2 operations. By definition, a valid codeword c ¼ [sjp] must satisfy the following equations:
Hct¼ ½ðHsÞmkjðHpÞmm½sjpt¼0t ð4Þ Replacing Hsand Hpby the dual-diagonal matrix definition, we get
P0;0 P0;1 P0;2 P0;kb1 P1;0 P1;1 P1;2 P1;kb1 P2;0 P2;1 P2;2 P2;kb1 .. . .. . .. . . . . .. . Pmb1;0 Pmb1;1 Pmb1;2 Pmb1;kb1 2 6 6 6 6 6 6 6 6 6 6 6 4 3 7 7 7 7 7 7 7 7 7 7 7 5 st 0 st 1 st 2 .. . st kb1 2 6 6 6 6 6 6 6 6 6 6 6 4 3 7 7 7 7 7 7 7 7 7 7 7 5 þ Id I Id I I I I .. . . . . . . . . . . I I I I 3 7 7 7 7 7 7 7 7 7 7 7 7 5 pt 0 pt 1 pt 2 .. . pt mb1 2 6 6 6 6 6 6 6 6 6 6 6 4 3 7 7 7 7 7 7 7 7 7 7 7 5 ¼0t 2 6 6 6 6 6 6 6 6 6 6 6 6 4 ð5Þ
where I is the identity matrix and Idis the circulant permutation matrix with d-position right shifting. After submatrix and sub-block multipli-cation, we obtain Skb1 j¼0 P0;jstj Skb1 j¼0 P1;jstj .. . Skb1 j¼0 Pmb1;js t j 2 6 6 6 6 6 6 6 6 6 6 4 3 7 7 7 7 7 7 7 7 7 7 5 þ ðp0Þtdþpt1 pt 1þpt2 .. . pt x1þptx pt 0þptxþptxþ1 pt xþ1þptxþ2 .. . pt kb2þp t kb1 ðp0Þtdþptkb1 2 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 4 3 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5 ¼0t ð6Þ
where (p0)dis p0with d-position left shifting. By summing all mbrows in (6), we obtain the following equations:
Smb1 i¼0 S kb1 j¼0 Pi;jstjþp t 0¼0 t ð7Þ The z equations in (7) can be used to replace the standard parity-check equations to detect successful decoding with all data blocks and only one parity block participating in the check. All parity bits corresponding to degree-2 nodes in the Tanner graph (equivalently, weight-2 columns in H) are excluded from the equations. Once all data bits are successfully decoded, the decoder can stop immediately without waiting for the remaining parity bits to converge. The proposed method requires a slightly lower number of shifting and XOR operations than the original parity-check equations to declare successful decoding. The mechanism can be applied to irregular repeat accumulate (IRA) codes, such as codes in the DVB-S2 standard[5]or OFDM-based UWB systems[7]. Results: A BP decoder combined with the proposed early detection method is compared with standard parity-check equations. Three codes defined in IEEE 802.16e with different code rates (1/2, 3/4) and block lengths (2304, 576) are used in the simulation. All results are simulated on the binary-input AWGN channel. Fig. 1shows the results of layered BP decoding, which converges twice as fast as two-phase decoding[8], with a maximum of 15 iterations. As shown in
ELECTRONICS LETTERS
6th November 2008
Vol. 44
No. 23
Fig. 1a, the proposed early detection mechanism achieves the same bit error rate (BER) performance as the standard parity-check equations.
Fig. 1bcompares the average number of iterations to declare a block
suc-cessfully decoded. The proposed mechanism requires 10 – 15% fewer iterations than the standard parity-check equations at BER ¼ 1025. The iteration reduction is greater for higher SNR situations. Simulation results show that applying our algorithm to two-phase decod-ing exhibits similar iteration reduction.
15 10 5 0 n umber of iter ations 1.0 1.5 2.0 2.5 3.0 3.5 E b/N0, dB 10–1 10–2 10–3 10–4 10–5 10–6 10–7 BER (576,384) Standard (576,384) Proposed (2304,1536) Standard (2304,1536) Proposed (2304,1152) Standard (2304,1152) Proposed a b Fig. 1 Performance of layered decoding algorithm a Bit error rate
b Average number of iterations to declare block successfully decoded
Conclusions: A novel stopping mechanism for dual-diagonal block-based LDPC codes is proposed for a standard iterative BP decoder. The proposed check equations exclude all parity bits corresponding to degree-2 nodes for the dual-diagonal portion in the matrix. Simulations show that the average number of iterations can be reduced by 10 – 15% at the operating point with no performance loss. The appli-cation of this mechanism reduces LDPC decoder power consumption at no coding gain and hardware complexity cost.
#The Institution of Engineering and Technology 2008 31 July 2008
Electronics Letters online no: 20082236 doi: 10.1049/el:20082236
C.-Y. Lin and M.-K. Ku (Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan 106, Republic of China)
E-mail: f93084@csie.ntu.edu.tw References
1 Gallager, R.G.: ‘Low-density parity-check codes’ (MIT Press, Cambridge, MA, USA, 1963)
2 Cai, Z., Hao, J., Tan, P.H., Sun, S., and Chin, P.S.: ‘Efficient encoding of IEEE 802.11n LDPC codes’, Electron. Lett., 2006, 42, (25), pp. 1471 – 1472
3 IEEE P802.11n/D2.00: ‘Draft standard for local and metropolitan area networks, specific requirements Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: enhancements for higher throughput’, February 2007
4 IEEE Std 802.16e-2005: ‘IEEE standard for local and metropolitan area networks Part 16: Air interface for fixed and mobile broadband wireless access systems’, February 2006
5 European Telecommunications Standards Institute (ETSI): ‘Digital video broadcasting (DVB) second generation framing structure for broadband satellite applications; EN 302 307 V1.1.1’, www.dvb.org
6 Li, Y., and Ryan, W.E.: ‘Bit-reliability mapping in LDPC-coded modulation systems’, IEEE Commun. Lett., 2005, 9, (1), pp. 1 – 3 7 Brack, T., Alles, M., Lehnigk-Emden, T., Kienle, F., Wehn, N., Berens,
F., and Ruegg, A.: ‘A survey on LDPC codes and decoders for OFDM-based UWB systems’. Proc. IEEE 65th Vehicular Technology Conf. (VTC2007-Spring), April 2007, pp. 1549– 1553
8 Goldberger, J., and Kfir, H.: ‘Serial schedules for belief-propagation: analysis of convergence time’, IEEE Trans. Inf. Theory, 2008, 54, (3), pp. 1316 – 1319
