3-Disjoint gamma interconnection networks
Ching-Wen Chen
a,*, Neng-Pin Lu
b, Chung-Ping Chung
caDepartment of Information and Communication Engineering, Chaoyang University of Technology, Wufeng 413, Taichung County, Taiwan, ROC bDepartment of Information Management, Chang Gung University, Kwei-Shan, Tao-Yuan 333, Taiwan, ROC
cDepartment of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, ROC Received 4 March 2001; received in revised form 29 August 2001; accepted 12 November 2001
Abstract
In this paper, we propose a new multistage interconnection network, called 3-disjoint gamma interconnection network (3DGIN). The 3DGIN is a modified gamma interconnection network that provides 3-disjoint paths to tolerate two switch or link faults be-tween any source and destination pairs. The 3DGIN has lower hardware cost than GIN; furthermore, the routing and rerouting tags to generate 3-disjoint paths can be obtained in Oðlog N Þ time. To show the advantage features of 3DGIN, we also make a com-parison between the gamma-related networks, the GIN, enhanced IADM, and 3DGIN.
Ó 2002 Elsevier Science Inc. All rights reserved.
Keywords: Gamma networks; Disjoint paths; Fault tolerance
1. Introduction
Interconnection networks are critical to parallel sys-tems because their performances are closely related to the latency and throughput of the network. Multistage interconnection networks are well suitable for commu-nication systems in terms of their tightly coupled com-ponents and can offer a good balance between cost and performance. For a complex system, assuring its high reliability is a challenging task. Therefore, in regard to the large-scale multiprocessor systems, fault tolerance is of crucial importance in term of fulfilling the commu-nication needs for MINs (Adams et al., 1987).
To enhance the capability of fault tolerance, gamma interconnection network (GIN) (Parker and Ragha-vendra, 1984) provides multiple paths between any source and destination pairs except that if the source and destination are identical. Furthermore, to improve the fault-tolerant capability of GIN, several schemes have been introduced, such as extra stage gamma
net-work (Yoon and Hegazy, 1988), CGIN (Chuang, 1996), composite banyan (Seo and Feng, 1995), PCGIN, FCGIN (Chen et al., 2000), B-network (Lee and Yoon, 1990) and enhanced IADM (McMillen and Siegel, 1982). Among them, extra stage gamma, CGIN, com-posite banyan network, FCGIN and PCGIN can pro-vide at least 2-disjoint paths. On the other hand, FCGIN and B-network use dynamic rerouting to tol-erate faults, but B-network cannot guarantee one-fault tolerant whereas FCGIN is one-fault tolerant. Although enhanced IADMhas the capability to tolerate two-faults, it needs higher hardware cost, one stage look-ahead technique and dynamic rerouting (McMillen and Siegel, 1982).
In this paper, we propose a new 3-disjoint paths network; namely, 3-disjoint GIN (3DGIN). This 3DGIN can also tolerate two links or switch faults, and its hardware cost is almost equal to GIN. The remainder of this paper is organized as follows. In Section 2, we shall introduce the GIN, and routing scheme in GIN. In Section 3, we shall present the 3DGIN, and the routing algorithm. In Section 4, the comparison between gam-ma-related networks and how to use disjoint paths to reduce hot spots are discussed. Finally, Section 5 con-cludes this paper.
*
Corresponding author.
E-mail addresses: chingwen@mail.cyut.edu.tw (C.-W. Chen), nplu@mail.cgu.edu.tw (N.-P. Lu), cpchung@csie.nctu.edu.tw (C.-P. Chung).
0164-1212/03/$ - see front matterÓ 2002 Elsevier Science Inc. All rights reserved. doi:10.1016/S0164-1212(02)00070-5
2. Gamma interconnection network and enhanced IADM
2.1. Topology of gamma interconnection network
A GIN of size N ¼ 2n has nþ 1 stages being labeled
from 0 to n and each stage involves N switches (Parker and Raghavendra, 1984). Basically, switches of sizes 1 3 and 3 1 are coupled with the first and last stage respectively. Moreover, each switch located at interme-diate stages is a 3 3 crossbar. And each switch number j at stage i has three output links connecting to switches at stage (iþ 1) according to the plus-minus-2i function.
In other words, the jth switch at stage i has three output links to switches [ðj 2iÞ mod N ], j, and [ðj þ 2iÞ mod N ]
at each consecutive stage. Fig. 1 illustrates a GIN net-work with size 8.
In GIN, an n-digit tag determines the path connecting the source to its destination. Each tag digit can be 1, 0, or 11. An n-digit tag T represents the difference between D and S, i.e., T ¼ ðD SÞ mod N . Digit tiis used at stage
i in such a way that the lower connection is selected when ti is equal to 1, and the straight connection is
se-lected when ti is 0, where the distance T ¼ t0t1. . . tn1.
Moreover, a non-zero tag T has multiple representa-tions, that is, there are multiple paths between source S and destination D if S6¼ D. For example, in the case when N ¼ 8, source node S is 2, and destination node D is 0, the tag T can be 0 1 1, 0 1 11 or 0 11 0 as shown in Fig. 1.
2.2. Topology of enhanced IADM
The enhanced IADM (McMillen and Siegel, 1982) is a revised version of IADMwith topology equivalent to GIN. There are two frameworks of enhanced IADM. One of them is designed to provide redundant straight links that allows fault links to be avoided by using the second straight link, but not the switch faults. The other arrangement is to add half links to each stage from stage 1 to n 1. Half links are used to connect a switch m at stage i with switch ðm þ 2i1Þ mod N and
ðm 2i1Þ mod N at stage i þ 1 as shown in Fig. 2.
Adding half links provides single-fault tolerance to any intermediate switch or link fault since there exist at least two links for distinct switches to connect to each other at the successive stage, and each one can be used to satisfy the routing requirement. However, the network cannot be two-fault tolerant unless a single-stage look-ahead technology and dynamic routing are engaged. For ex-ample, in the present case when S¼ 6 and D ¼ 6, and the routing path may be 6! 6 ! 6 ! 6, however, as the straight link from stage 1 to stage 2 is faulty, the path can be 6! 6 ! 4 ! 6. If the link from switch 4 to switch 6 is faulty (the second fault), the routing algorithm must use the look-ahead technique to overlook one stage further to get the information from switch 4 at stage 2. Conse-quently, the algorithm will take the link to switch 0 at stage 2. As a result, the path will change to 6! 6! 0 ! 6. This example is illustrated in Fig. 2.
Fig. 1. GIN with N¼ 8 and its three paths between nodes 2 and 0.
Fig. 2. The routing condition in enhanced IADMwith S¼ 6, D ¼ 6 and two links faults. The dash lines mean faulty links.
3. 3-Disjoint paths gamma interconnection network
Enhanced IADM, although it is two-fault tolerant, needs higher hardware cost, one stage look-ahead technique, and dynamic rerouting capability to complete the operation of networking. In this section we dem-onstrate the proposed 3-disjoint paths GIN (3DGIN), which is comparable to GIN in terms of the lower hardware cost and two-fault tolerant capability.
3.1. Topology
A 3DGIN, 3-disjoint paths GIN of size N¼ 2n, is
similar to GIN in many respects except that switches 2i and 2iþ 1 are combined into one 2 4 switch at stage 0 with the rest of stages being the same as GIN. Fig. 4 shows the 3DGIN with N¼ 8. The naming scheme at stage 0 is described as follows. The four associated links are named to be 0 0, 0 1, 1 0, and 1 1 as shown in Fig. 3. And the links at other stages are denoted as GIN.
Theorem 1. There are 3-disjoint paths between any source and destination pair in 3DGIN.
Proof. There are two sections in this proof: one of them is ðD SÞ mod 2 ¼ 0, and the other one is ðD SÞ mod 2¼ 1.
(a) In the part ofðD SÞ mod 2 ¼ 0, let us consider a path which automatically takes the straight link from switch S at stage 0 to switch S at stage 1 in GIN because ðD SÞ mod 2 ¼ 0.
1. IfjD Sj 6¼ N =2, there is at least one path P in GIN routing through the straight link between final two stages since jD Sj or (N jS DjÞ is less than N =2. We apply this path P to the proposed 3DGIN. In this regard, the remaining 2-disjoint paths will tra-verse the switch [ði þ 1Þ mode n] and [ði 1Þ mode n] if the path P traverse the switch i between stage 1 to stage n 1, whereas the first and final stages are (plus and minus)/(minus and plus) one as shown in Fig. 4. 2. IfjD Sj ¼ N =2 and S is odd/even; where the slash in-dicates a state of either the former or the latter within
a time domain. Let P1, P2 and P3 be the 3-disjoint
paths taking the links (0 0, 0 1, 1 1)/(0 0, 1 0, 1 1) at stage 0. From stage 1 to destination, (P2; P3Þ=ðP1; P2)
always take non-straight upward and downward links respectively. However, P1=P2 is paralleling P2=P3
ex-cept for the stage n 1 to stage n by straight link. P2=P1and P3=P2go through different switches because
the sum of the vertical length to stage n 1 is less than N 2. Finally, two non-straight links are taken to destination as shown in Fig. 4.
(b) WhenðD SÞ mod 2 ¼ 1 and S is even/odd, the 3-disjoint paths are the same as those ofðS þ 1Þ=ðS 1Þ to D, because the input of S and ðS þ 1Þ=ðS 1Þ are combined in the same switches.
There are 3-disjoint paths in 3DGIN between any source and destination pair.
3.2. Routing and rerouting tags
In this section, we shall demonstrate the algorithm to compute routing and rerouting tags. The algorithm needs source and destination tags as input to produce three routing tags. Because there are four links from stage 0 to stage 1, the binary representation of the routing tags, Ta, Tb, and Tc, occupyðn þ 1Þ bits. Also, the notation of the first two bits is Tx0 and Tx1 and of
other bits is Tx2; Tx3; . . . ; Txn. Let us discuss the
condi-tions for generating routing and rerouting tags.
Fig. 3. The naming scheme of links at stage 0 in 3DGIN.
Fig. 4. 3-Disjoint paths GIN with size 8. (Two routing conditions in 3DGIN. Solid lines meanðD SÞ mod 2 6¼ N =2, and dash lines mean ðD SÞ mod 2 ¼ N =2.)
1. Input source S and destination D.
2. Calculate the distance T. Because the distance T ¼ ðD SÞ must be less than N =2.
(a) The distance T ¼ ðD SÞ mod N if ððD SÞ mod NÞ < N =2.
(b) The distance T ¼ N ððD SÞ mod N Þ if ððD SÞ mod N Þ > N =2.
3. Find the first routing tag Ta under T is not equal to N =2 and we do not care stage 0 to 1 because the link needs 2 bits.
(a) T ¼ N =2 1,
(i) If S is odd, the path goes up-direction or straight links only. We can find the path from ðS 1Þ mod N to D and the bits of tag Ta are composed of 0 or 11 only.
(ii) If S is even, the path goes down-direction or straight links only. We can find the path from ðS þ 1Þ mod N to D and the bits of tag Ta are composed of 0 or 1 only.
(b) T < N =2 1,
(i) If T is even and the direction is down-ward/up-ward, the Ta is calculated by T only by 0 or 1/11. (ii) If T is odd, we calculate the distance
ðS 1Þ=ðS þ 1Þ to D if S is odd/even.
(c) From the result of procedure 3(a) and 3(b), the first and last links take the straight, that is, the first two bits of Ta are 0 1 or 1 0 and the last bit of Ta is 0.
4. Find two more rerouting tags Tb and Tc
(a) The bits of Tb and Tc are the same as Ta between bit 1 to bit n 1, and the first two bits are 0 0/0 1 and 1 0/1 1 if the first two bits of Ta is 0 1/1 0, and last bits are 11 and 1.
5. Find Ta, Tb and Tc under T ¼ N =2
(a) If (T ¼ N =2 1 and S is odd and direction is down), we let S¼ S 1 because the inputs of S and S 1 connect the same switch at stage 0. (b) If (T ¼ N =2 1 and S is even and direction
is up), we let S¼ S þ 1 because the inputs of S and Sþ 1 connect the same switch at stage 0.
(c) If T ¼ N =2 (the condition is the same as previous two after procedure (d) and (e) are processed), Ta and Tb could be 0 0 11 11 11 . . . 1=0 1 1 11 11 11 . . . 11 and 1 0 1 1 1 . . . 1=1 1 1 1 1 . . . 1 respectively. And the third tag Tc is 1 1 1 1 . . . 1 1 0=0 0 11 11 11 . . . 0.
To be specific, Algorithm 1 describes the details of this routing algorithm. Some examples are given below to provide the methods of calculation. Three examples of 3DGIN are illustrated for comparison; and their ex-pressions are listed as follows:
1. ðS DÞ mod N < N =2, 2. ðS DÞ mod N ¼ N =2, 3. ðS DÞ mod N > N =2.
The first and third condition are similar, we just present the instance for condition 1. For example, if S ¼ 2, D ¼ 3=4, and N ¼ 8, the routing tags can be de-rived as 0 1 1 0=1 0 0 0, 0 0 1 1=0 1 0 1, and 1 0 1 11=1 1 0 11 after the distance T ¼ 2=1 is calculated, as shown in Fig. 5. In the second example: if S ¼ 4, D ¼ 0=1, and N ¼ 8; the routing tags can be derived as 0 0 11 11=0 0 11 0, 1 0 1 1=0 1 11, and 1 1 1 0=1 1 1 1 after the distance T ¼ 4=5 is calculated, as shown in Fig. 5.
Algorithm 1. Calculate the routing and rerouting tags of 3DGIN
Input: Source tag S ¼ s0s1s2. . . sn1, destination node
D¼ d0d1d2. . . dn1
Output: Routing tags Ta¼ ta0 0ta0 1ta1ta2. . .tan1,
Tb¼ tb0 0tb0 1tb1tb2. . .tbn1, Tc¼ tc0 0tc0 1tc1tc2. . .tcn1 Begin Up¼ False; T ¼ ðD SÞ mod N ; If T > N =2 then T ¼ N T ; Up¼ True; End If
If T < N =2 1 or (T ¼ N =2 1 and S is odd and Up¼ True) or (T ¼ N =2 1 and S is even and Up¼ False)
then
If (T is even and S is even) or (T is odd and S is odd) then
Fig. 5. The 3-disjoint paths in 3DGIN with S¼ 2 and D ¼ 4 for the D S < N =2 case with bold line and S ¼ 4 and D ¼ 0 for the D S < N =2 case with bold dash line.
Ta0 0¼ 0 1; Tb0 0 ¼ 0 0; Tc0 0¼ 1 0;
Else
Ta0 0¼ 1 0; Tb0 0 ¼ 0 1; Tc0 0¼ 1 1;
End If
T ¼ T =2; /* take the integer part */ For i¼ 1 to n 2
Tai¼ T %2; /*get the remainder*/
If Up¼ True then Tai¼ Tai; T ¼ T =2; Tbi¼ Tai; Tci¼ Tai; End for Tan1¼ 0; Tbn1¼ 1; Tcn1¼ 11 Else
If (T ¼ N =2 and S is even) or (T ¼ N =2 1 and S is odd) then Ta0 0¼ 0 0; Tb0 0 ¼ 1 0; Tc0 0¼ 1 1; For i¼ 1 to n 2 Tai¼ 11; Tbi¼ 1; Tci¼ 1; End For Tan1¼ 11; Tbn1¼ 1; Tcn1¼ 0; Else Ta0 0¼ 0 0; Tb0 0 ¼ 0 1; Tc0 0¼ 1 1; For i¼ 1 to n 2 Tai¼ 11; Tbi¼ 1; Tci¼ 1; End For Tan1¼ 11; Tbn1¼ 1; Tcn1¼ 0; End If End If End 4. Discussion
3DGIN provides 3-disjoint paths for two-fault tol-erant and the same network latency Oðlog2NÞ in light traffic under no fault occurring. When a fault occurs, a packet backtracks to source node and takes another path to destination by rerouting tag. However, the net-work latency will be
log2Nþ 1 3n Xn1 i¼0 2i¼n 1 3 þ log2N ;
but GIN will be log2N or1 because GIN has no
alter-native path when straight link is fault shown in Table 1. Although 3DGIN has the characteristics of 3-disjoint paths and the same network latency Oðlog2NÞ in light traffic under no fault occurs and lower hardware cost than GIN, its feature of redundant links is lost. However, the redundant links in GIN can help a packet go either upward or downward as it encounters a non-straight link (Rau et al., 1992). For example, S¼ 2, D ¼ 0, and N ¼ 8, the packet can go up-direction, 2! 2 ! 0 ! 0, or go down-direction, 2! 2 ! 4 ! 0, because of the redun-dant properties of GIN as shown in Fig. 1. If the prop-erty of redundancy is needed, a plus/minus-2n1link can
be added to final stage and the hardware cost will in-crease. Yet this brings the following additional advan-tage: Alternative path when a non-straight link is taken. In our design, we choose not to have the feature though. Additionally, more disjoint paths can reduce the ef-fects of hot spots in a MIN (Wang et al., 1995; Chuang and Tu, 1999). The reducing hot spot scheme is de-scribed as follows:
1. The packets can be synchronous or asynchronous and with hot spots or not.
2. We find 3-disjoint paths by the preceding procedure. 3. When tree saturation occurs, the routing path is se-lected according to the request pattern (synchronous or asynchronous) and the current network traffic (with or without hot spots).
(A) If the pending request is a synchronous request, we set the routing to use the upper routing path. (B) For an asynchronous request, the routing path should be chosen following the current network traffic.
I(I) If the destination of the pending asynchronous request is not a hot spot, the lower or middle path is chosen as the routing path and the up-per path is released for the after pending syn-chronous request.
(II) If it is a hot spot, the upper path is chosen as the routing path and the middle and lower paths are reserved for the other pending asyn-chronous requests. (If the asynchronous
Table 1
The comparison of GIN, 3DGIN, and enhanced IADM
Network Fault-tolerance method Fault tolerant ability Routing method Hardware cost (total switchÕs crossing points)
Fault penalty
GIN Multiple paths Faults robust Distance tag 9N log N 3N 0 or1
3DGIN Disjoint paths 3-Disjoint paths Distance tag and
rero-uting tags
9N log N 6N ðn 1Þ=3
Enhanced IADM
Dynamic rerouting and look-ahead one stage method
3-Disjoint paths Distance tag with look-ahead one stage infor-mation
request still traverses the network by the mid-dle or lower path, the path will be blocked since the target port is a hot spot.)
As a result, if the asynchronous transmission constitutes the majority of communication in the network traffic, such a static routing scheme will be able to reduce av-erage delay time.
5. Conclusion
A new multipath multistage interconnection network called 3DGIN is proposed in this paper. The 3DGIN can provide 3-disjoint paths between any source and destination pairs by converting two switches into one at stage 0. In addition, without one stage look-ahead technique, 3DGIN still offers the capabilities of two-faults tolerance, less hardware cost, and 3-disjoint paths, as compared with enhanced IADM. Table 1 summarizes the comparison of GIN, 3DGIN and enhanced IADM. In conclusion, 3DGIN distinct from other schemes has been demonstrated in this work with innovative fea-tures, including low hardware cost, 3-disjoint paths ca-pability, and an Oðlog N Þ algorithm of getting routing and rerouting tags.
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Ching-Wen Chen is an assistant professor of Department of Informa-tion and CommunicaInforma-tion Engineering, Chaoyang University of Technology, Wufeng, Taichung County, Taiwan, Republic of China. He received the B.E. degree in information engineering and computer science from Feng Chia University, Taiwan, Republic of China in 1993, and the M.E. degree in Department of Computer Science from National Tsing Hwa University, Taiwan, Republic of China in 1995 and the Ph.D. degree in Department of Computer Science and Infor-mation Engineering from Chiao Tung University, Taiwan, Republic of China in 2002. His research interests include computer architecture, interconnection network and parallel processing.
Neng-Pin Lu is an assistant professor of Department of Information Management, Chang Gung University, Kwei-Shan, Tao-Yuan, Tai-wan, Republic of China. Before joined Chang Gung University, he has been an assistant processor of Chihlee Institute of Commerce, Pan-chiao, Taipei, Taiwan, Republic of China. He received the B.E., M.E., and Ph.D. degrees of Computer Science and Information Engineering from the National Chiao Tung University, Hsinchu, Taiwan, Republic of China in 1989, 1991, and 2000, respectively. His research interests include computer architecture, interconnection network, parallel pro-cessing, and cluster computing.
Chung-Ping Chung received the B.E. degree from the National Cheng-Kung University, Taiwan, Republic of China in 1976, and the M.E. and Ph.D. degrees from the Texas A&MUniversity in 1981 and 1986, respectively, all in electrical engineering. He was a lecturer in electrical engineering at the Texas A&MUniversity while working towards the Ph.D. degree. Since 1986 he was been with computer science and in-formation engineering at the National Chiao Tung University, Tai-wan, Republic of China, where he is a professor. From 1991 to 1992, he was a visiting associate professor of computer science at Michigan State University. Currently, he is on leave and served as the director of Advanced Technology Center, Computer and Communications Re-search Laboratories, Industrial Technology ReRe-search Institute (CCL, ITRI), ROC, and then the consultant of CCL, ITRI. His research interests include computer architecture, parallel processing, and par-allel compiler design.
