Trend transformation of drain-current degradation under drain-avalanche hot-carrier stress for CLC n-TFTs

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Trend transformation of drain-current degradation under drain-avalanche

hot-carrier stress for CLC n-TFTs

Zhen-Ying Hsieh

a

, Mu-Chun Wang

a,d,*

, Chih Chen

b

, Jia-Min Shieh

c

, Yu-Ting Lin

b

, Shuang-Yuan Chen

a

,

Heng-Sheng Huang

a

Institute of Mechatronic Engineering, National Taipei University of Technology, Taipei, Taiwan

b

Department of Material Science and Engineering, National Chiao Tung University, Hsin-Chu, Taiwan

c

National Nano Device Laboratories, Hsin-Chu, Taiwan

d

Department of Electronic Engineering, Ming-Hsin University of Science and Technology, No. 1 Hsin-Hsing Road, Hsin-Fong, Hsin-Chu 304, Taiwan

a r t i c l e

i n f o

Article history: Received 5 March 2009

Received in revised form 10 May 2009 Available online 17 June 2009

a b s t r a c t

Continuous-wave green laser-crystallized (CLC) single-grain-like polycrystalline silicon n-channel thin-film transistors (poly-Si n-TFTs) demonstrate the higher electron mobility and turn-on current than exci-mer laser annealing (ELA) poly-Si n-TFTs. Furthermore, high drain voltage accelerates the flowing elec-trons in n-type channel, and hence the hot-carriers possibly cause a serious damage near the drain region and deteriorate the source/drain (S/D) current. In this study, at high drain stress voltage, it appears that CLC TFT was degraded in the initial stress time (before 50 s), but the drain current was enhanced after 50 s. After 50 s stress time, the amount of grain boundary trap states near the drain side was getting large and the reflowing holes damaged the source region or injected into gate oxide near source side as well.

1. Introduction

One of the cardinal constraints for scaling down TFT’s dimen-sions is the device reliability. Degradation of TFTs can be caused by bias temperature stressing (BTS)[1], Fowler–Nordheim tunnel-ing injection[2]and the hot-carrier stressing[3]. The hot-carrier stressing and Fowler–Nordheim tunneling can cause degradation both near the SiO2/Si interface [4] and the grain boundary [5]

and in the bulk of gate oxide [6]. In the recent stage, a mature and low-cost fabrication technology in liquid–crystal-display (LCD) panel is that the gate channel of TFT device is formed with amorphous silicon (a-Si) type. Comparing the driving current be-tween a-Si TFT and low-temperature-poly-silicon (LTPS) TFT

[7,8], the later exhibits higher electron-and-hole mobility charac-teristics. Moreover, LTPS TFT can be fabricated with self-alignment process and is similar to the process of metal–oxide-semiconduc-tor ﬁeld-effect transismetal–oxide-semiconduc-tor (MOSFET)[9,10]. Hence, the implemented integration of TFT drivers and TFT devices on glass substrate is pos-sible to fabricate in one set of processes. Additionally, laser crystal-lization providing the local heating and avoiding the melting glass around 600 °C will be a key technology to improve the driving per-formance of TFT panel, due to the good annealing quality of TFT channel. In the meantime, a large size of LTPS TFT LCD is a trend in global market need. Thus, a higher driving speed of TFT device

is strongly expected. Although an excimer laser system[11] possi-bly produces 100–500 nm grain size in gate channel, the interfaces of grain boundaries[12]are too dense, causing the carrier mobility decreases and the channel leakage increases. To solve these disad-vantages, the continuous-wave laser crystallization technology

[13–15] demonstrates excellent single-grain-like polycrystalline silicon thin ﬁlm because of the low crystallization rate. Further-more, CLC system is more efﬁcient than excimer laser system in cost, and produces high reliability and high-performance charac-teristics of TFTs for the application of active matrix LCDs and sys-tem-on-panel (SOP) on optical glass or quartz substrate.

In this study, this CLC poly-Si TFT[16]demonstrates that excel-lent electron mobility, up to 530 cm2_{/V s}1_{, is greater than that}

with low-temperature poly-silicon fabrication technology. Although the gate dielectric with TEOS–SiO2 [17]was deposited

with 100 nm thickness by plasma-enhanced chemical vapor depo-sition (PECVD), the current-driving capability of CLC poly-Si n-TFT was sufﬁciently obtained instead of high-k gate dielectric [18]. Hence, the thick gate dielectric provides the good immunity against gate leakage current. Undoubtedly, while poly-Si n-TFT was stressed with drain-avalanche hot-carrier (DAHC) stress, inter-face states and defects near drain region, and electrons injecting into gate dielectric were obviously observed.

2. Experimental procedure

After substrate clean, the fabrication of devices started by depositing a buffer silicon-nitride layer and a thin buffer oxide

*Corresponding author. Address: Department of Electronic Engineering, Ming-Hsin University of Science and Technology, Ming-Hsin-Chu, Taiwan. Tel.: +886 3 5593142; fax: +886 3 5591402.

E-mail address:[email protected](M.-C. Wang).

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Microelectronics Reliability

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layer to capture the mobile ions and release the stack stress, respectively. Then, a 200 nm undoped amorphous Si layer at 550 °C in a low-pressure chemical-vapor-deposition (LPCVD) sys-tem on quartz substrate capped with a 100-nm thick TEOS oxide layer with plasma-enhanced chemical-vapor-deposition technol-ogy at 300 °C was deposited. The CLC poly-Si n-TFT device was then fabricated by a green laser annealing system, deﬁning as con-tinuous-wave laser crystallization, to produce a grain-like silicon channel. Finally, the active region of a TFT transistor was fabricated on the CLC poly-Si. The test-key pattern of CLC grailike poly-Si n-TFT[16,19]is shown inFig. 1a and b describes the A–A0

cross-sec-tion proﬁle inFig. 1a.

The steeper subthreshold swing (SS) presents the less traps in the grain[18]. After green laser crystallization, furnace annealing or green laser annealing can be accessed to activate the single-grain-like polycrystalline silicon thin film and dopant atoms. In some lecture [19], the process of green laser annealing to acti-vate the impurity after implantation exhibited excellent electron mobility. Adopting a typical hot-carrier stress called drain-ava-lanche hot-carrier (DAHC) stress on CLC n-TFTs is a good metrol-ogy to verify the confident reliability of CLC TFTs. In this research, the thermal furnace activation in source/drain, and poly-gate implantation was accessed to firstly discuss the CLC poly-Si TFTs under DAHC stress. Before stress, Fig. 2 displays the great electrical characteristics of CLC poly-Si n-TFTs. The turn-on current (ION) is around 870

l

A/

l

m at VDS= VGS= 16 V.

The ﬁeld-effect mobility (

l

FE) [20] is about 406 cm2/V s1 at

maximum trans-conductance for a width/length (W/L) = 25/15 (

l

m/

l

m) n-TFT device.

3. Test results and discussion

The selected device was 25

l

m at width and 15

l

m at length, and the threshold voltage was about 1.75 V which was deﬁned by maximum trans-conductance method (max Gm method) at VDS= 0.1 V. For the DAHC stress conditions on CLC n-TFTs, the

forced drain and gate voltages, and temperatures were shown in

Table 1. In the meantime, the source terminal was grounded. With regard to DAHC stress on conventional nMOSFETs, the stress condition is usually deﬁned at the speciﬁed gate and drain voltages while the maximum substrate current appears. For a long channel-length device, the maximum substrate current will appear as the applied gate voltage is located at the half or one-third of forced drain voltage. In this study, the selected TFT device was a long channel-length device as 15

l

m, so that the worst degrada-tion of DAHC stress can be approximately employed when the forced gate voltage is equal to the half of the forced drain voltage. The characteristic curves of drain current and gate current with and without electrical stress involving room temperature and high temperature are presented inFig. 3. The CLC poly-Si n-TFTs were dealt by DAHC-1 test and DAHC-2 test labeled in theTable 1.

For DAHC-1 and DAHC-2 stresses, the degradation in drain cur-rent is obviously observed, especially at high temperature, and a deterioration of gate current is found, too. In the meantime, the subthreshold swing (SS) is also degraded. The drain current at the saturation region is usually deﬁned as[21,22]

IDS;sat:¼

W

2L

l

nCoxðVGS VTHÞ2 ð1Þ

where

l

n is the electron mobility, Cox the gate dielectric

capaci-tance, and VTHis the threshold voltage.

Therefore, the degradation of drain current may be attributed to the degradation in electron mobility, gate dielectric capacitance, or threshold voltage (VTH). In the worst case, all these three factors

contribute the degradation for S/D current together. Before, at ﬁrst, while temperature increases from 25 °C to 50 °C, the electron 5 m Grain boundaries 20 m Source Drain Gate 5 m Grain boundaries 5 m Grain boundaries 20 m Source Drain Gate A’ A

a

b

Fig. 1. Schematic proﬁles of (a) test-key pattern[16,19] and (b) A–A0

cross-sectional view of CLC poly-Si n-TFT structure with the bottom-ﬂoating conﬁguration.

Fig. 2. Initial electrical characteristics of IDSvs. VDSand IDSvs. VGSfor CLC poly-Si n-TFT.

Table 1

The stress conditions of DAHC tests.

DAHC-1 DAHC-2

Gate voltage (V) 7 9

Drain voltage (V) 14 18

Temperature (°C) 25 and 50 Stress time (s) 0–3000

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mobility reduces due to the lattice vibration, and hence the degra-dation of drain current is more obvious at high temperature than at room temperature, as shown inFig. 3a–d. After DAHC stress, the oxide-trap charges, grain boundary traps, bulk grain traps and interface traps inﬂuenced the degradation of device performance. The electrons occupied the oxide trap forming negative trapped charges in the oxide layer. The negative trapped charges repelled the continuous jumping electrons that reduced the gate leakage current[23], presented in Fig. 3a–d. One model with connected equivalent resistance, as shown in Fig. 4, is suitable to interpret the reduction of gate leakage. The trapped charges, occupying the oxide trap and repelling the continuous jumping electrons, reduce the gate leakage current[23]. However, the gate capacitance integ-rity with PECVD TEOS-SiO2exhibited lower performance than that

with thermal oxidation SiO2. The resistance phenomenon was

obviously observed. Therefore, the resistance model was consider-ably adopted and adequate to explain the gate current decrease after stress.

Additionally, the relationship between gate leakage and gate voltage with room temperature can be expressed as

IG;Total 25_C¼ A lnðV_GSÞ B ð2Þ

where A and B are constant and A extracted by linear regression is 1 1012 _{for DAHC-1 at 25 °C, and 2 10}12 _{for DAHC-2 at}

25 °C. Again, the value of B extracted by the same calculated method is 3 1012 _{for DAHC-1 at 25 °C, and 4 10}12 _for

DAHC-2 at 25 °C. There are several physical mechanisms com-posing for gate current [20]. Referring Ref.[20], the gate current was theoretically attributed to exp(Ei). However, in this work,

the proposed equation of gate current was related to ln(VGS)

due to the LPCVD TEOS oxide which contained a lot of oxide trapped states and easily provided the tunneling path. Thus, the gate current rapidly increased at the initial time, but gradu-ally saturated at a long-term operation. At high temperature, the total gate current can be considered as liner dependence and represented as

IG;Total 50_C¼ CV_GS D ð3Þ

Fig. 3. Drain current and gate current with and without (w/o) DAHC stresses under temperature effect. The CLC poly-Si n-TFTs were processed with (a) DAHC-1 at 25 °C, (b) DAHC-1 at 50 °C, (c) DAHC-2 at 25 °C, and (d) DAHC-2 at 50 °C.

Fig. 4. Dependence of gate leakage of CLC poly-Si n-TFT w and w/o DAHC-1 stress. The inset plot demonstrates the reduction of gate current with an equivalent resistance model.

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where the values of C and D for DAHC-1 and DAHC-2 stresses at 50 °C extracted by linear regression are 2 1013 _{and 3 10}13

with DAHC-1, and 3 1013 _{and 2 10}12 _{with DAHC-2,}

respectively.

From Eqs.(2) and (3), we ﬁnd while temperature has been in-volved, the total gate leakage current exhibits a non-linear distri-bution, especially in low vertical electrical ﬁeld (low VGS).

Furthermore, the degradation of drain current after DAHC-1 or DAHC-2 stress can be simply correlated to IG,Total with different

temperatures by

ID; deg radation/ IG;Total Temperature ð4Þ

When the difference of total gate current increases, based on Eq.

(4), a serious degradation of drain current can be measured. The degradation of drain current under DAHC-1 with the increase in stress time is attributed to the generation in grain boundary trap states and interface trap states, as shown in Fig. 5. The power law numbers at room temperature and high temperature are 0.157 and 0.285, respectively. While the TFT device was stressed with DAHC-2 condition, the forced gate and drain voltages were in-creased so that some holes injecting into gate oxide and the other reflowing to source terminal were occurred. The schematic dia-gram of hole-injection and oxide damage with hole flow is dis-played inFig. 6. The threshold voltage shift in this work, because of the poly-Si channel, is not chiefly evident to realize the hole-injection at the source side. Using gate-to-source capacitance vs. gate voltage (CGS–VGS curve) could be better to illustrate the

hole-injection mechanism, shown inFig. 7.

In addition to the TFT device stressed by DAHC-1, the device un-der DAHC-2 stress appears the amount of interface trap states and grain boundary trap states was larger than that with DAHC-1 stress. The grain boundary trap states were possibly generated from the broken bonds of Si–H. However, there are a large number of grain boundaries in the channel[24], and hence the contribution

of interface states in degradation of electrical characteristics was acceptably ignored. Furthermore, the hole carriers injecting into gate oxide caused an increase in inversion charges at the channel. At this meantime, the electrical field near the drain region was so high that the dangling bonds formed by Si–H bond hardly capture the flowing electrons. Thus, the generated holes not only inject into the gate oxide, but reflow from the drain side to source terminal as well. Finally, at low stress time, the interface trap states and grain boundary trap states near the drain side were dominated. After 50 s stress time, the amount of grain boundary trap states near the drain side was getting large and the reflowing holes damaged the source region or injected into gate oxide near source side as well.

4. Conclusions

A comprehensive investigation of the DAHC reliability mecha-nism of high-performance CLC n-TFT is reported for the first time. Various stress conditions, including electrical fields and tempera-ture impact, are performed to differentiate the degradation mech-anisms. For the low-field stress (DAHC-1) plus temperature effect, it is found that degradation of drain current showing the increase trend is due to impact ionization at the drain site. Higher temper-ature provides more sufficient thermal energy to energize the moving electrons to gain more kinetic energy to impact the drain site, inducing the worse degradation. For the high-field stress (DAHC-2) with temperature contribution, the degradation of drain current after a short-term stress dramatically depicts a turning point and gets healing because of the attraction of high drain field. The captured electrons in boundary traps and interface states were released.

The study of DAHC effect on CLC poly-Si n-TFT device with tem-perature effect is necessary to be revealed that it impacts on TFT devices from different performance required not only in LCD mon-itor, but in system-on-panel consideration. Through this experi-ment, the degradation of electrical characteristics of CLC poly-Si n-TFT under DAHC stress is similar to the logic nMOSFET device and the worst reliability case may be occurred in high temperature, not low temperature.

Acknowledgment

The authors thank National Chiao Tung University in Taiwan for providing the precious CLC poly-Si n-TFT substrate.

y=0.5155x0.157

y=0.0899x0.2853

Fig. 5. Time history of 4Id/Id0degradation under DAHC-1 stress. An increased

trend of drain-current degradation with either 25 °C or 50 °C was observed.

Interface states VG=9V

Impact ionization

VD=18V

Drain Hole trap states

Source VS

Oxide damage

Electron trap states Hole drift

Fig. 6. Schematic cross-section of drain-current degradation under DAHC-2 stress. Two possible ﬂow paths of hole carriers are pointed out.

y= 1.0728x0.3553

y=5.6512x-0.2051 y=5.249x-0.0493

y= .4169x0.1636

Fig. 7. Degradation of drain current 4Id/Id0vs. stress time under DAHC-2 high-ﬁeld

stress. A turning point is observed with either 25 °C or 50 °C before and after 50 s of stress time.

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