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國 立 交 通 大 學

電 信 工 程 學 系 碩 士 班

碩 士 論 文

單晶片溫度感測器的高線性度參考電壓

之設計與製作

The Design and Implementation of High Linear

Voltage References for System-on-Chip

Temperature Sensors

研究生:蔡佐昇

指導教授:闕河鳴 博士

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單晶片溫度感測器的高線性度參考電壓之設計與製作

The Design and Implementation of High Linear Voltage References for

System-on-Chip Temperature Sensors

研 究 生:蔡佐昇

指導教授:闕河鳴 博士

Student:Joseph Tzuo-sheng Tsai Advisor:Dr. Herming Chiueh

國立交通大學

電信工程學系碩士班

碩士論文

A Thesis

Submitted to Institute of Communication Engineering College of Electrical Engineering and Computer Science

National Chiao Tung University in Partial Fulfillment of the Requirements

for the Degree of Master of Science in Communication Engineering July 2006 Hsinchu, Taiwan. 西元二零零六年七月

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單晶片溫度感測器的

高線性度參考電壓之設計與製作

學生:蔡佐昇

指導教授:闕河鳴

國立交通大學電信工程學系碩士班

摘要

高線性度電壓參考電路以 TSMC 0.13μm 及 TSMC 0.18μm 複合式金氧 矽製程來設計及實現。先前研究已經提出在傳統上正比絕對溫度的電路 裡,金氧矽電晶體操作在弱反轉區可以用來取代雙極性裝置。然而這樣的 方法,在現今深次微米及奈米複合式金氧矽技術下,常因元件的漏電流效 應,使得在高溫時會有線性度之問題。本論文所提出的電路,利用溫度補 償技術用在正比絕對溫度及與絕對無度無關這兩個參考電壓下,來加強線 性度並產生一個較為穩定的無關溫度之參考電壓。模擬結果中,在55°C 到 170°C 的溫度範圍下,R-quares 都可達到 0.999 以上。此論文設計了一個溫 度範圍廣的溫度感測器,並且能夠容易整合於現今的系統晶片設計之中。

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The Design and Implementation of High Linear Voltage

References for System-on-Chip Temperature Sensors

Student: Joseph Tzuo-sheng Tsai Advisor: Dr. Herming Chiueh

Institute of Communication Engineering National Chiao Tung University

Hsinchu, Taiwan 30050

Abstract

High linear voltage references circuitry is designed and implemented in TSMC 0.13μm and 0.18μm CMOS technology. Previous research has proposed the use of MOS transistors operating in the weak inversion region to replace the bipolar devices in conventional PTAT(proportional to absolute temperature) circuits. However such solutions often have linearity problem in high temperature region due to the current leaking devices in modern deep sub micron and nano-scale CMOS technology. The proposed circuit utilized temperature complementation technique on two voltage references, PTAT and IOAT (independent of absolute temperature) references, to enhance the linearity and produce a more stable IOAT voltage reference. Base on the simulation results, the R-squares of both circuitries are better than 0.999 in a considerable wider temperature range from -55°C to 170°C. Thus, a fully integrated temperature sensor with wider temperature range is designed and easily to integrate to modern system-on-chip designs with minimal efforts.

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Acknowledgements

本篇論文可以完成,首先要感謝我的指導教授,闕河鳴博士,在論文遇到瓶頸 時,闕老師都能夠適時的解決我的疑惑,給我寶貴的意見及正確的方向,在他的 指導下,不僅僅是學術研究能力上的成長,更讓我學習到生活上該有的一些觀念。 其次,要感謝同實驗室的學弟們,在生活及研究上都給了我許多幫助以及靈 感,並在平常給予我許多的打氣,也讓我的碩士生活過的更加多采多姿。 最後,我要感謝我的家人,我的父母,姐姐及弟弟,雖然家境有點清寒,但是 因為有家人的支持,我也才能順利完成學業,也才能成就現在的我。

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CONTENTS

Chinese Abstract ... I

English Abstract... II

Acknowledgements ... III

Contents ... IV

List of Tables... VI

List of Figures...VII

Chapter 1 Introduction...1

1.1 Motivation...1

1.2 Organization...2

Chpater 2 Temperature Sensing...4

2.1 CMOS Smart Temperature Sensors ...4

2.2 Temperature Sensing...5

2.3 Summary ...13

Chpater 3 CMOS Voltage References...15

3.1 Introduction...15

3.2 CMOS Voltage References ...16

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3.4 Summary ...24

Chpater 4 Simulation and Experimental Results ...25

4.1 Pre-layout Simulation ...25

4.2 Layout Consideration and Post-layout Simulation ...30

4.3 Discussion ...34

Chpater 5 Conclusions and Future Works ...35

5.1 Conclusions...35

5.2 Future works ...36

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List of Tables

Table 2.1 The linearity summary of

VGS

...11

Table 3.1 Ratio List ...20

Table 4.1 Summary of TSMC 0.18

μm CMOS technology simulation

results ...26

Table 4.2 Sizing of resistor-based circuit in TSMC 0.18

μm CMOS

technology...27

Table 4.3 Aspect of all-MOS-based circuit in TSMC 0.18

μm CMOS

technology...27

Table 4.4 Summary of TSMC 0.13

μm CMOS technology simulation

result...28

Table 4.5 Aspect of all-MOS-based circuit in TSMC 0.13

μm CMOS

technology...29

Table 4.6 Simulation summary of all-MOS-based circuitry architecture 34

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List of Figures

Figure 1.1 Block diagram of a thermal aware system ...2

Figure 2.1 Communication between a temperature sensor and a computer

...5

Figure 2.2 The block diagram of conventional smart temperature sensor

...5

Figure 2.3 Generation of PTAT voltage with bipolar transistors ...8

Figure 2.4 The simulation prototypes ...9

Figure 2.5 The simulation results done in TSMC 0.13μm CMOS

technology...10

Figure 2.6 The simulation results done in TSMC 0.18μm CMOS

technology...10

Figure 2.7 Generation of PTAT voltage with subthreshold MOSFETs....12

Figure 3.1 Low-voltage CMOS PTAT references (resistor-based)...16

Figure 3.2 Low-voltage CMOS PTAT references (all-MOS-based) ...17

Figure 3.3 Resistor-based CMOS PTAT and IOAT references...18

Figure 3.4 All-MOS CMOS PTAT and IOAT references ...19

Figure 3.5 Path 1 ...19

Figure 3.6 Low-frequency small-signal model of the resistor-based PTAT

reference shown in Fig. 3.3...22

Figure 3.7 Low-frequency small-signal model of the resistor-based IOAT

reference shown in Fig. 3.3...23

Figure 4.1 The simulation result of PTAT references simulated in TSMC

0.18μm CMOS technology ...26

Figure 4.2 The simulation result of IOAT references simulated in TSMC

0.18μm CMOS technology...27

Figure 4.3 The simulation result of PTAT reference simulated in TSMC

0.13μm CMOS technology...28

Figure 4.4 The simulation result of IOAT reference simulated in TSMC

0.13μm CMOS technology...29

Figure 4.5 The simulation results of both PTAT and IOAT references

simulated in TSMC 0.13μm CMOS technology ...30

Figure 4.6 The block diagram of our design flow ...31

Figure 4.7 The all-MOS-based layout of TSMC 0.18

μm 1P6M CMOS

technology...31

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Figure 4.8 Post-layout simulation of PTAT reference before tuning...32

Figure 4.9 Post-layout simulation of IOAT reference before tuning ...32

Figure 4.10 Post-layout simulation of PTAT reference after tuning...33

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Chapter 1 Introduction

CHAPTER

1

Introduction

1.1 Motivation

Increases in circuit density and clock speed in modern VLSI systems have brought thermal issues into the spotlight of high-speed VLSI design. Large gate-count and high operating frequency in modern system-on-chip integration escalate the problem. Previous research has indicated that the thermal problem can cause significant performance decay [1] as well as reducing of circuitry reliability [2]-[5]. In order to avoid thermal damages, early detection of overheating and properly handling such event are necessary. For these reasons, temperature sensors are widely used in modern VLSI systems.

Recent research has indicated that the best candidate for a fully-integrated temperature sensor is the proportional-to-absolute temperature (PTAT) circuit [6] and independent-of-absolute-temperature (IOAT) circuit with the sigma-delta modulator and digital filter. Figure 1.1 shows the block diagram of this on-chip thermal aware system. In such design, the PTAT sources are usually implemented using parasitic vertical BJTs in any standard CMOS technology [7], [8]. These circuits require resistors which may vary from different technology. Also, the power consumption of the BJT based references is relatively high for low power applications. However, in deep sub micron CMOS technology, the characteristic of vertical BJT is getting worse. So, the design of temperature sensor has become a major challenge in deep sub micron technology.

The PTAT generator of Vittoz and Fellrath [9] takes advantage of MOS transistors operating in the weak inversion region; the power consumption is minimal due to the

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Chapter 1 Introduction PTAT signal Reference signal Sigma-delta modulator Interface bus Decimation filter + control

Figure 1.1 Block diagram of a thermal aware system.

inherently low currents in that region. However, this circuit does not allow strong supply voltage scaling.

Serra-Graells and Huertas [10] introduce an all-MOS implementation exhibiting enough low-voltage capabilities by the use of MOS sub-threshold techniques. However, in this circuit, the current leaking device in modern deep sub-micron CMOS technology has cause the linearity problem of the PTAT and IOAT signals in high temperature range.

These nonlinearity behaviors are crucial effect to implement a complete thermal management system within a digital circuit since such circuitries require more efforts and costs for after process calibration. Thus, linearity and power issues are the key factors for design a fully integrated temperature sensor in the deep sub micron CMOS technology.

In this thesis, both PTAT and IOAT voltage references are redesigned by utilizing sub-threshold MOSFETs and temperature complementation technique to enhance the linearity and produce a more stable output. The propose design has extend the linear temperature rage of on-chip temperature sensor to -55°C to 170°C which provides a practical solution for modern system-on-chip’s thermal management systems.

1.2 Organization

Chapter 2 begins with the review of the temperature sensing, from mercury-in-glass thermometers to very low power and low cost smart temperature sensors. Then the temperature sensing methods both with bipolar transistors and subthreshold MOSFETs are described. For the low-power consideration, subthreshold MOSFETs

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Chapter 1 Introduction are more suitable than bipolar transistors. We also demonstrated the nMOS is better than pMOS for the design.

Chapter 3, first, introduces the MOS PTAT reference circuitry architecture which has been proposed in [11]. Then the new PTAT and IOAT reference circuitry architectures have been proposed. The first version is resistor-based reference circuitry architecture. For the area consideration, the second version, all-MOS reference circuitry architecture, has been proposed. The all-MOS reference circuitry architecture also enhances the compensative mechanism. All the detail design concepts will be described in this Chapter.

In Chapter 4, the simulation and experiment results are introduced. First, the resistor-based reference circuitry architecture has been simulated in TSMC 0.18μm 1P6M CMOS technology. Then, the simulation results of all-MOS version which are simulated with both TSMC 0.18μm and 0.13μm CMOS technology have been shown. All-MOS version’s layout consideration is also described. Finally, the experiment results and discussion are discussed.

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Chapter 2 Temperature Sensing

CHAPTER

2

Temperature Sensing

This Chapter begins with the introduce of smart temperature sensors. Following the brief introduce, the methods of temperature sensing both with bipolar transistors and subthreshold MOSFETs are described. For the low power applications, the n-type subthreshold MOSFETs are more suitable than p-type, this result is demonstrated on a deep-submicron technology. A brief conclusion is made in the end of the Chapter.

2.1 CMOS Smart Temperature Sensors

As time goes by, due to the remarkable market growth portable systems nowadays, the demand for very low power and low cost but high performance temperature sensors is becoming much stronger than ever. To reduce the cost of a system that consists of both a temperature sensor and a computer interface, integration of the temperature sensor and the analog-to-digital converter was attempted. This new system family was called integrated smart temperature sensors. Figure 2.1 shows this system.

The important nowadays applications of smart temperature sensors include: 1) the power consumption control in VLSI chips; 2) the thermal compensation in single-chip systems and micro systems with built-in sensors; 3) the environment temperature monitor in automatic fabrication factories; and 4) the temperature control of consumer electronics. However, temperature sensing with bipolar transistor do not exhibit enough low-power capabilities [12]-[14]. This disadvantage is a very fatal reason for the low power portable applications. Nowadays researches have some solutions for this problem, such as temperature sensing with subthreshold MOSFETs and time-to-digital-converter-based CMOS smart temperature sensors [15].

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Chapter 2 Temperature Sensing

Analog-to-Digital converter Temperature signal

(analog) Temperature signal(digital)

Figure 2.1 Communication between a temperature sensor and a computer.

applied are getting more and more complex. The future trend for smart temperature sensors will be low power and low cost. Cheaper temperature sensors will also increase the number of applications.

Figure 2.2 shows the block diagram of conventional smart temperature sensor. In the figure, we know the temperature is sensed by two voltage references, PTAT and reference signal (such as bandgap reference or independent-of-absolute-temperature reference). So to improve the linearity of PTAT or to reduce the variance of bandgap reference (or independent-of-absolute-temperature reference) will make the sensor produce a more accurate temperature output. This thesis will force on the topic of how to improve these reference signals.

In order to attain our goal, knowing the principle of PTAT and bandgap reference will be necessary. In the next session, we will introduce how to produce both positive and negative temperature coefficients with bipolar transistors and MOSFETs. Then to combine pTC and nTC, we will get independent-of-absolute-temperature reference. some improvements will be presented in the following chapters.

PTAT signal Reference signal Sigma-delta

modulator Interface bus Decimation

filter + control

Figure 2.2 The block diagram of conventional smart temperature sensor.

2.2 Temperature sensing

In this section, the temperature sensing method with both bipolar transistor and subthreshold MOSFETs will be described. In order to convert temperature to a digital value, both a well-defined temperature dependent signal and a temperature independent reference signal are required. There are two voltage that we interesting, one requires a positive temperature coefficient (pTC), and another requires a negative

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Chapter 2 Temperature Sensing temperature coefficient (nTC). A quantity which requires a positive temperature coefficient is used to measure the temperature. If two quantities having opposite temperature coefficients (TCs) are added with proper weighting, the result displays a temperature-independent quantity which requires a zero TC. As follow, the two interesting quantities, one requires a negative temperature coefficient and another requires a positive one, are discussed.

(A) Bipolar transistor

(i) Negative temperature coefficient (nTC)

The base-emitter voltage of bipolar transistors exhibits a negative TC. For a bipolar device, ) ( T BE S C V V EXP I I = ⋅ (2.1)

Where UT = k T /q and I is the saturation current of the transistor which is S

temperature dependent. Rewrite Equation (2.1), we can get:

) ln( ) ( S C C BE I I q kT I V = ⋅ (2.2)

Where k is Boltzmann’s constant (1.380710−23J/K), T the absolute temperature

(in Kelvin), and q the electron charge (1.602210−19C). Because we want to

know the TC of the base-emitter voltage, we take the derivative of VBE with

respect to T. We can get:

T I I q kT I I q k T V S S S C BE ∂ ∂ − ⋅ = ∂ ∂ 1 ) ln( (2.3)

The saturation current is I is proportional to (S ukTni2), where u is the

mobility of minority carries and n is the intrinsic minority carries i

concentration of silicon. The temperature dependence of these quantities is

represented as m

T u

u0⋅ , where m is a constant about -3/2, and

] / exp[ 3 2 kT V T

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Chapter 2 Temperature Sensing can write I as follows: S

kT V T IS m g − ⋅ ⋅ =β 4+ exp (2.4)

β is a proportionality factor. We take the derivative of I with respect to T to S

know its temperature characteristic. We can get:

kT V k V T kT V T m T IS = ⋅ + ⋅ m⋅ − g + ⋅ mg ⋅ − g ∂ ∂ β (4 ) 3+ exp β 2+ exp (2.5)

With the aid of (2.3) and (2.4), we can write

qT V m q k I I q k T V g S C BE = ⋅ − ⋅ + − ∂ ∂ ) 4 ( ) ln( (2.6) T q V U m VBE−(4+ ) Tg/ = (2.7)

From Equation (2.7), the temperature coefficient of the base-emitter voltage at a given temperature T is gotten and it is clear negative. For example, with

mV

VBE ≈750 and T =300oK, ∂VBE/∂T ≈−1.5mV/oK.

(ii) Positive temperature coefficient (pTC)

When two bipolar transistors operate at two different collector currents I1 and

2

I , the difference between their base-emitter voltage will be a proportional to

absolute temperature quantity. Figure 2.2 is illustrates this idea. As follows, we describe in detail. 2 1 BE BE BE V V V = − Δ (2.8) S T S T I I U I I U ln 1 − ln 2 = (2.9) 2 1 ln I I UT = (2.10)

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Chapter 2 Temperature Sensing Q Q11 QQ22 V VDDDD I I11 II22 + + ΔΔVVBE BE -

-Figure 2.3 Generation of PTAT voltage with bipolar transistors.

If the two collector currents have this relation, I1 = pI2, where p is a constant.

From Equation (2.10), we get:

) ln( p q kT VBE = ⋅ Δ (2.11)

Taking the derivative of Equation (2.11) with respect to T, we get:

) ln( p q k T VBE ⋅ = ∂ Δ ∂ (2.12)

According to Equation (2.12), we know clear the difference of the base-emitter voltage operated in different collector currents is a PTAT quantity.

(B) Subthreshold MOSFETs

(i) Negative temperature coefficient (nTC)

Previous research [16] has shown the gate-source voltage of an nMOS which operated in weak inversion has a negative temperature coefficient (nTC) and can be modeled as: ) 1 / ( ) ( ) (TV T0 +KT T0VGSn GSn Gn (2.13)

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Chapter 2 Temperature Sensing Where OFFn THn GSn Tn Gn K V T V T V K ≅ + ( 0)− ( 0)− (2.14)

Where K is the temperature coefficient for nMOS threshold voltage and Tn T 0

is room temperature (=300 K). The gate-source voltage of a pMOS transistor can also been modeled as:

) 1 / ( ) ( ) (TV T0 +KT T0VGSp GSp Gp (2.15) Where OFFp THp GSp Tp Gp K V T V T V K ≅ + ( 0) − ( 0)− (2.16)

In order to verify the linearity of VGS operated in deep sub micron simulations

based on both TSMC 0.13μm and 0.18μm technology are conduced, the gate-source voltage of an nMOS diode-connected transistor biased with a 100-nA current and the diode aspect ratio was set to 50/2 are simulated. The same simulations are also done with a pMOS diode-connected transistor. Figure 2.3 shows the simulation prototypes. The results are shown in Figure 2.4 and Figure 2.5. Basing on the results shown in Figure 2.4 and Figure 2.5, we can know that the linearity of nMOS gate-source voltage is better than pMOS source-gate voltage in both TSMC 0.18μm and 0.13μm CMOS technology. Table 2.1 shows the summary. So, if we want to get much better linearity in wider range, for the case, [-55, +170] C0 , the gate-source voltage of an nMOS transistor is the best

choice.

nMOS pMOS

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Chapter 2 Temperature Sensing −40 −20 0 20 40 60 80 100 120 140 160 50 100 150 200 Temperature = −55 to 170 DEG−C V(T) mV

Temperature VS. NMOS Gate−Source Voltage (TSMC 0.13um CMOS technology)

−40 −20 0 20 40 60 80 100 120 140 160 50 100 150 200 250 Temperature = −55 to 170 DEG−C V(T) mV

Temperature VS. PMOS Gate−Source Voltage (TSMC 0.13um CMOS technology)

Simulation Result Linear Regression

Figure 2.5 The simulation results done in TSMC 0.13μm CMOS technology.

−40 −20 0 20 40 60 80 100 120 140 160 100 150 200 250 300 Temperature = −55 to 170 DEG−C V(T) mV

Temperature VS. NMOS Gate−Source Voltage (TSMC 0.18um CMOS technology)

−40 −20 0 20 40 60 80 100 120 140 160 50 100 150 200 250 300 350 400 Temperature = −55 to 170 DEG−C V(T) mV

Temperature VS. PMOS Gate−Source Voltage (TSMC 0.18um CMOS technology)

Simulation Result Linear Regression

Simulation Result Linear Regression

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Chapter 2 Temperature Sensing

Table 2.1 The linearity summary ofVGS.

R-square NMOS PMOS

TSMC 0.13μm CMOS technology 0.99976 0.99214

TSMC 0.18μm CMOS technology 0.99971 0.87315

Above all, a linear negative temperature coefficient voltage based on subthreshold MOSFETs has been presented.

(ii) Positive temperature coefficient (pTC)

The positive temperature coefficient quantity can be gotten in several kinds of MOS PTAT generators. The idea of MOS PTAT generators is like the bipolar transistor PTAT generators. When two MOSFETs operate at two different collector currents I1 and I2, the difference between their gate-source voltage

will be a proportional to absolute temperature quantity. Figure 2.5 is illustrates this idea. As follows, we describe in detail.

According to the references [11] and [17], the drain currents of M1 and M2 are given by ( ) T S t G U n V n V V T w D K U e I ⋅ ⋅ − − − ⋅ ⋅ ⋅ = 1 1 1 , 0 1 1 2 1 1 1 β (2.17) ( ) T S t G U n V n V V T w D K U e I ⋅ ⋅ − − − ⋅ ⋅ ⋅ = 2 2 2 , 0 2 1 2 2 2 2 β (2.18)

Where n is the slope factor, φf is the substrate Fermi potent, and

T f +severalU = φ φ0 2 (2.19) T f U w n e K φ φ0 2 ) 1 ( − ⋅ − = (2.20)

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Chapter 2 Temperature Sensing V VDDDD + + ΔΔVVGS GS - -I I11 II22 M M11 MM22

Figure 2.7 Generation of PTAT voltage with subthreshold MOSFETs.

2 , 1 2 , 1 2 , 1 , 2 , 1 , 2 , 1 ' L W C unox ⋅ = β (2.21) 0 0 2 , 1 , 0 = FB+φ +γ ⋅ φ t V V (2.22)

Where VFB is the flat-band voltage.

Because the source is connected to ground, Equations (2.17) and (2.18) can be derived to ) ln( 1 1 1 1 , 0 1 C I U n V V D T t G = + ⋅ ⋅ (2.23) ) ln( 2 2 2 2 , 0 2 C I U n V V D T t G = + ⋅ ⋅ (2.24) Where 2 2 , 1 2 , 1 2 , 1 Kw UT C = ⋅β ⋅ (2.25)

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Chapter 2 Temperature Sensing If M1 and M2 are matched, the PTAT voltage can be obtained from the difference in V and G1 VG2: ) ln( 1 2 2 1 2 1 S S I I U n V V V D D T G G GS = − = ⋅ ⋅ ⋅ Δ (2.26)

Where S1and S2 are the W/L ratios of M1 and M2 respectively. Taking the

derivative of Equation (2.26) with respect to T, we get:

) ln( 1 2 2 1 S S I I q k n T V D D GS = ⋅ ⋅ ⋅ ∂ Δ ∂ (2.27)

If the drain currents have the relation,ID1 = pID2, and S2 =rS1, where p and

q are constants, we get:

) ln(p r q k n T VGS ⋅ ⋅ ⋅ = ∂ Δ ∂ (2.28)

According to Equation (2.28), we know clear the difference of the gate-source voltage operated in different drain currents is a PTAT quantity.

2.3 Summary

In this Chapter, the history of the temperature sensing is introduced. And we also describe the smart temperature sensor. As time goes by, much cheaper, low power, and high performance temperature sensors will be demanded for many applications. In the section 2.3, we describe how to generate two voltage references which one has a negative temperature coefficient and another is a proportional-to-absolute-temperature with both bipolar transistors and subthreshold MOSFETs. However, for the low power consideration, the bipolar transistor is more difficult to implement. Because the MOSFETs operated in the weak inversion region will have minimal power consumption, subthreshold MOSFETs are more suitable for the low power design. But when we use subthreshold MOSFETs, we still have many challenges, such as [7]:

¾ The behaviors are more complicated for designers.

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Chapter 2 Temperature Sensing ¾ The performance is significantly affected by the variations of manufacture

process.

These problems affect the performance significantly. Leakage current has become a serious problem in modern VLSI. It also affects the linearity of PTAT. As to smart temperature sensors, many dynamic offset-cancellation techniques can be used to enhance the performance, such as autozero techniques, chopper techniques, and nested chopper technique. However, for the linearity of PTAT or the variation of the independent-to-absolute-temperature (IOAT), we still can do more efforts to improve their performance.

In next Chapter, PTAT and IOAT of our design will be proposed. Some compensation methods to improve the linearity of PTAT and the variation of IOAT are presented. All the details will be described later. Based in this Chapter’s backgrounds, it is useful for us to get guidelines in our proposed design.

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Chapter 3 CMOS Voltage References

CHAPTER

3

CMOS Voltage References

In this Chapter, both proportional-to-absolute-temperature (PTAT) and independent-of-absolute-temperature (IOAT) voltage references are redesigned by utilizing sub-threshold MOSFETs and temperature complementation technique to enhance the linearity and produce a more stable output. The propose design has extend the linear temperature rage of on-chip temperature sensor to -55°C to 170°C which provides a practical solution for modern system-on-chip’s thermal management systems. The design concept of proposed circuit will be described in this Chapter, and the experimental results are presented in Chapter 4.

3.1 Introduction

Various on-chip PTAT and IOAT references have been extensively implemented using parasite BJTs because of the ease of design. In some CMOS process, however, obtaining reliable BJTs is very costly and desirable performance from these parasitic devices is hard to expect. Also, the power consumption of the BJT based references is relatively high and an alternative approach is preferred, especially in low power applications.

Several PTAT and IOAT references based on the subthreshold MOSFETs have been studied and applied in low power low voltage design. As we mention in the Chapter 2, these circuits take the advantages of the MOS transistors operated in weak inversion region in the respects: the power consumption is made minimum due to the inherent low currents in this region. The power issues are overcome by taking the advantage of the MOS transistors operated in weak inversion region. Another issue is the accuracy. For the PTAT references, linearity is the most important performance index we concern about. For the IOAT references, various must be as low as possible. Some

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Chapter 3 CMOS Voltage References Our design concepts are described in detail as follow. And some design issues are also described in following sections.

3.2 CMOS Voltage References

In the Chapter 2, we know the gate-source voltage of an nMOS transistor operated in the weak inversion region has a linear negative temperature coefficient (nTC) and is suit for the design. So if we put PTAT core and the gate-source voltage which operated in weak inversion region (VGS) together, the IOAT voltage reference will be

achieved by sum up both out. According to previous researches [8], a PTAT voltage reference circuit based on subthreshold MOSFETs has been developed. Figure 3.1 and figure 3.2 illustrate the condensed scheme of two low-voltage CMOS PTAT references [11]. In these circuits,M1 and M2 operate in weak inversion region, while transistors M3-M8 ensure the current ratio of M1-M2 pair. The transistor Mc which operated in weak inversion region compensates the leakage current to enhance the linearity of PTAT reference. Above all, the PTAT references will be written as:

P U

VPTAT = T ln (3.1)

Where UT = k T /q and P is the aspect ratio of M6 to M3.

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Chapter 3 CMOS Voltage References

Figure 3.2 Low-voltage CMOS PTAT references (all-MOS-based).

The proposed circuitry architectures are shown in Fig. 3.3. The design concept is that using current mirror combines positive and negative temperature coefficients.

The first part circuit, M1-M8, Mc, and R1, will produce a PTAT voltage reference. The slope of PTAT reference is determined by the aspect ratio of M6 and M3. And function of Mc is to compensate the leakage current. The quantity of the PTAT reference is as the same as equation (3.1). The second part of this circuit is made up of M9, R2, and a diode-connected transistor, Mn. A negative temperature coefficient will be produced in the gate-source voltage of Mn. The target of our design is to make two different temperature coefficient sum up, so we use a current mirror to make them sun up in current type. In this architecture, the IOAT voltage can be expressed as:

GSn PTAT IOAT V S S R R V V = ⋅ ⋅ + 3 9 1 2 (3.2)

Where S and 3 S are the aspect ratios of M3 to M9. 9

In order to get a zero temperature coefficient, we take the derivative of equation (3.2) with respect to temperature (T).

0 3 9 1 2 = ∂ ∂ + ⋅ ⋅ ∂ ∂ T V S S R R T VPTAT GSn (3.3) According to equations (3.1), (2.13), and (2.14), we can get:

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Chapter 3 CMOS Voltage References

Figure 3.3 Resistor-based CMOS PTAT and IOAT references.

0 ] ) ( ) ( [ 1 ln 0 0 0 3 9 1 2 + + = OFFn THn GS Tn V T V T V K T p q k S S R R (3.4) Where K is the temperature coefficient for nMOS threshold voltage and Tn T is 0

room temperature (=300 K). We rewrite equation as:

)] ( ) ( [ ln 0 0 0 3 9 1 2 V T V K V T p T k q S S R R GSn Tn OFFn THn + − − ⋅ ⋅ = ⋅ (3.5)

Because the right side of equation (3.5) is constant, the ration

3 9 1 2 S S R R ⋅ is determined.

For the area consideration, we also develop all-MOS PTAT and IOAT voltage reference. Figure 3.4 shows the all-MOS architecture. R1 exchanges with M9, M10, and M11. R2 is exchanges with M14, M15, and M16. Both M11 and M12 are operated in strong inversion conduction region. In order to ensure each current ratio, we add another feedback path M17, M18, M19, and M20. Following equations (3.6), (3.7), (3.8), and (3.9), the details are described:

) ( )] ( 2 [ GB TO DB SB DB SB D V V V V n V V I =β⋅ − − + ⋅ − s.i.cond. (3.6) 2 ) ( 2 GB TO SB D V V nV n I = β ⋅ − − s.i.sat. (3.7)

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Chapter 3 CMOS Voltage References M2 Mc M1 VPTAT M8 M5 M6 M4 M3 M7 Vdd M9 M10 M11 M17 M19 M18 M20 M12 M14 M13 VIOAT M15 M16 Figure 3.4 All-MOS CMOS PTAT and IOAT references.

T SB T TO GB U V nU V V S D I e e I − − ⋅ ⋅ = ( ) w.i.sat. (3.8) 2 2 T S n U I = ⋅ ⋅β⋅ (3.9)

WhereVTO, β, n, and I stand for the threshold voltage, current factor, subthreshold S

slope, and specific current, respectively, as defined in the EKV model [17]. We assume that there is no current the path 1 as shown as follow:

M2 Mc M1 VPTAT M8 M5 M6 M4 M3 M7 Vdd M9 M10 M11 M17 M19 M18 M20 M12 M14 M13 VIOAT M15 M16 PATH 1 Figure 3.5 Path 1.

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Chapter 3 CMOS Voltage References Table 3.1 Ratio List

NMOS PMOS

M7 M8 M10 M11 M3 M4 M5 M6 M9

1 1 N 1 1 1 1 P M

M15 M16 M18 M20 M12 M14 M17 M19

S 1 1 1 1 Q 1 1

The ratios of transistors are shown in Table 3.1and Table 3.2. According to the equations (3.6) to (3.9), we can write:

12 2 10 10 10 ( ) 2 GB TO PTAT D D V V nV M I n N I = ⋅β − − = ⋅ (3.10) 12 11 11 11 ] ( 1) 2 ) [( GB TO PTAT PTAT D D V V M I n V V I =β ⋅ − − ⋅ = + ⋅ (3.11)

Set the bodies of M10 and M11 connect to ground. Because the gates of M10 and M11 are connected together, we can get:

2 2 2 11 12 (1 1 ) ) 1 ( 4 2 M N N N M M V n I PTAT D ⋅ ⋅ + + + + ⋅ = β (3.12)

The same idea is applied in the right side of this circuitry.

12 2 15 15 15 2 ( GB TO X) D D V V nV Q I n S I = ⋅ β − − = ⋅ (3.13) 12 16 16 16 ] ( 1) 2 ) [( GB TO X X D D V V Q I n V V I =β ⋅ − − ⋅ = + ⋅ (3.14)

Where VX =VD16 =VS15 =VS13. Set the bodies of M15 and M16 connect to ground.

Because the gates of M15 and M16 are connected together, we can get:

2 2 2 16 12 (1 1 ) ) 1 ( 4 2 Q S S S Q Q V n I X D ⋅ ⋅ + + + + ⋅ = β (3.15)

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Chapter 3 CMOS Voltage References 2 2 2 2 2 2 ) 1 1 ( ) 1 ( ) 1 1 ( ) 1 ( Q S S S Q Q V M N N N M M VPTAT x ⋅ ⋅ + + + + = + + + ⋅ ⋅ + (3.16)

Simplify equation (3.16), we can get:

PTAT X V Q S N M Q S S M N N M Q V ⋅ ⋅ ⋅ + + + + + + ⋅ + + = 1 1 1 1 1 1 (3.17)

From equation (3.17), the VIOAT can be written as:

PTAT GSn IOAT V K V V = 13+ ⋅ (3.18) Where Q S N M Q S S M N N M Q K ⋅ ⋅ + + + + + + ⋅ + + = 1 1 1 1 1 1 (3.19)

K is a design parameter which composed of transistor ratios. Because M, N, S, and Q are ratios, they will make K more accurate when the manufacturing process varies. In order to get a zero temperature coefficient, we take the derivative of equation (3.18) with respect to temperature (T).

0 ln 13 + = ∂ ∂ p q k K T VGSn (3.20)

According to equation (2.13) and (2.14), we can rewrite equation (3.20) as:

0 ] ) ( ) ( [ 1 ln 0 0 0 = − − + + ⋅ ⋅ KTn VGS T VTHn T VOFFn T p q k K (3.21)

From equation (3.21), we can get the design constant K will be:

)] ( ) ( [ ln 0 0 0 T V K V T V p T k q K THn + OFFnTnGSn ⋅ ⋅ = (3.22)

Above all, two PTAT and IOAT reference circuitry architectures are designed. The linearity of PTAT reference is compensated by the transistor, Mc. This compensation technique has been proposed before. Our design is to add a well-defined IOAT

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Chapter 3 CMOS Voltage References reference and an efficient current compensation circuit. This Chapter has described the design concepts of two proposed circuits, one is resistor-based PTAT and IOAT reference circuitry architecture and another one is all-MOS-based PTAT and IOAT reference circuitry architecture.

Next session we will discuss the power-supply rejection ratio (PSRR) issue.

3.3 Power Supply Rejection Ratio (PSRR)

From section 3.2, we proposed two PTAT and IOAT reference circuitry architectures and some compensation technique. However, the power supply rejection ratio (PSRR) of these circuits deteriorates sharply in deep-submicro technology. So the analysis of PSRR is necessary for a reference circuit. The PSRR of PTAT reference has been discussed in previous research [18].

The small signal DC gain vptat vdd of this circuit can be derived from the low

frequency small signal model shown in Fig. 3.6. Assume go <<gm for all transistors,

then 8 6 4 1 1 3 5 7 2 2 1 1 2 3 5 7 ) 1 ( ) ( m m m m m m m m m o m o m m m m dd ptat ptat g g g g R g g g g g g g g g g g g R v v A ⋅ ⋅ ⋅ − ⋅ + ⋅ ⋅ ⋅ ⋅ ⋅ − ⋅ ⋅ ⋅ ⋅ ⋅ ≈ ≈ (3.23)

If gm4 =gm5 andgm7 = gm8, the above equation can be written as

6 1 1 3 2 2 1 1 2 3 ) 1 ( ) ( m m m m m o m o m m dd ptat ptat g g R g g g g g g g g R v v A ⋅ − ⋅ + ⋅ ⋅ ⋅ − ⋅ ⋅ ⋅ ≈ ≈ (3.24) 1 vptat

Figure 3.6 Low-frequency small-signal model of the resistor-based PTAT reference shown in Fig. 3.3.

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Chapter 3 CMOS Voltage References According to above result, we can know that gm2go1 = gm1go2 and

∞ →

+

PSRR for low frequency response.

After finishing the PSRR analysis of PTAT reference, we continue to discuss the PSRR analysis of IOAT reference in this circuit.

The small signal DC gain vioat vdd of this circuit can be derived from the low

frequency small signal model shown in Fig. 3.7. Assume go <<gm for all transistors,

then ) 1 ( ) ( ) ( 9 9 2 on mn x dd m o ioat dd ioat g g R v v g g v v v + + ⋅ − ⋅ + ⋅ − = (3.25)

And the voltage of node x can be derived as:

1 8 8 ) ( ) ( R v g g v v ptat o m x dd − ⋅ + = (3.26) ) ( 8 8 1 m o ptat dd x g g R v v v + ⋅ ⋅ − = (3.27)

Figure 3.7 Low-frequency small-signal model of the resistor-based IOAT reference shown in Fig. 3.3.

Take equation (3.36) into equation (3.34), we can get the gain ofVioat, Aioat as

)] ) ( ) ( ( [ 1 1 8 8 1 9 8 8 9 1 2 9 9 m o mn on m o m m ptat o o dd ioat g g g g R g g g g R R A g g v v + ⋅ + ⋅ + + ⋅ ⋅ + ⋅ + ≈ (3.28)

Where Aptat is shown in equation (3.23) and (3.24)

According to above result, ifgm2go1 =gm1go2, the PSRR of PTAT reference will

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Chapter 3 CMOS Voltage References 9 9 1 o o ioat g g A + ≈ (3.29) Ifgo9 >>1, the gain of IOAT reference will be unity. So we can know the power supply rejection ratio (PSRR) of IOAT is dependent on the power supply rejection ratio (PSRR) of PTAT, and the gain of IOAT reference will been unity.

3.4 Summary

In this Chapter, we proposed two kinds of PTAT and IOAT reference circuitry architectures, which one is resistor-based and another one is all-MOS-based. The design concepts are well described in this Chapter. After we describe the circuits, the issue of power supply rejection ratio (PSRR) is also discussed. According to the results, we know the PSRR of PTAT can achieve to infinite. When this happened, the gain of IOAT reference will be unity. The much well the PSRR of PTAT, the much well the PSRR of IOAT is.

Next Chapter, the pre-layout simulation results will be shown. And the layout concept is also discussed. In the end, we will show the post-layout simulation results.

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Chapter 4 Simulation and Experimental Results

CHAPTER

4

Simulation and

Experimental Results

In this Chapter, the both pre-layout simulation and post-layout simulation are presented. We simulate the both resistor-based and all-MOS-based circuitry architectures with TSMC 0.18μm CMOS technology. Moreover, all-MOS-based circuitry architecture is further simulated with TSMC 0.13μm CMOS technology. Then, the layout with TSMC 0.18μm CMOS technology is shown. Post-layout simulation is shown in the end of this Chapter.

4.1 Pre-layout Simulation

In Chapter 3, we proposed two new circuitry architectures, resistor-based and all–MOS based voltage generators and have been complete described. First, we simulate both the circuitry architectures with TSMC 0.18μm CMOS technology. The simulation results are shown in figure 4.1 and 4.2.

Figure 4.1 shows the PTAT voltage versus temperature for all-MOS-based and resistor-based PTAT references simulated in TSMC 0.18μm 1P6M standard CMOS technology. The simulation range is from -55°C to 170°C temperature range conduced for each circuit. The R-squares of resistor-based and all-MOS-based circuits are 0.99963 and 0.99968 respectively.

Figure 4.2 shows the PTAT voltage versus temperature for all-MOS-based IOAT reference simulated in TSMC 0.18μm 1P6M standard CMOS technology. The simulation range is from -55°C to 170°C for each circuit. The means of resistor-based and all-MOS-based circuits are 578.75mV and 514.94mV respectively. The variation

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Chapter 4 Simulation and Experimental Results −40 −20 0 20 40 60 80 100 120 140 160 50 60 70 80 90 100 110 120 Temperature = −55 to 170 DEG−C V(T) mV

Temperature VS. PTAT Voltage (TSMC 0.18um CMOS technology) All−MOS PTAT Simulation Result

Resistor−based PTAT Simulation Result

Figure 4.1 The simulation result of PTAT references simulated in TSMC 0.18μm CMOS technology.

of the resistor-based circuit is about ±5mV. For the all-MOS-based circuit, the variation is about ±8mV.

The performance is summarized in Table 4.1. All the transistors aspects are shown in Table 4.2 and Table 4.3. According to the simulation results, we know the performance of resistor-based circuit is not better than the performance of all-MOS-based circuit. Moreover, for the area consideration, resistor-based circuit requires more area. This means the resistor-based circuitry architecture is not suited for the market demand. For the low cost consideration, we give up this architecture, and force on all-MOS-based circuitry architecture. The further simulation of all-MOS-based circuitry architecture is done with TSMC 0.13μm CMOS technology.

Table 4.1 Summary of TSMC 0.18μm CMOS technology simulation results

TSMC 0.18μm PTAT Temperature Coefficient (mV∕°C) PTAT R-square IOAT Mean (mV) R-based 0.206 0.99963 514.94 All-MOS-based 0.276 0.99968 578.75

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Chapter 4 Simulation and Experimental Results −40 −20 0 20 40 60 80 100 120 140 160 520 530 540 550 560 570 580 590 Temperature = −55 to 170 [DEG−C] Vref(T) [mV]

Temperature VS. Reference Voltage (TSMC 0.18um CMOS technology) All−MOS IOAT Simulation Result

Resistor−based IOAT Simulation Result

Figure 4.2 The simulation result of IOAT references simulated in TSMC 0.18μm CMOS technology.

Table 4.2 Sizing of resistor-based circuit in TSMC 0.18μm CMOS technology TSMC 0.18μm CMOS technology Model Name Aspect (W/L)

M1,M2,Mn NCH 1.2/0.36 m=40 M3,M4 PCH 0.6/2.8 M5 PCH 0.64/0.6 m=10 M6,M7,M8,M9 PCH 0.64/0.6 Mc NCH 1.2/0.36 m=150 X1 Rppo1rpo 2/3050 X2 Rppo1rpo 2/12800

Table 4.3 Aspect of all-MOS-based circuit in TSMC 0.18μm CMOS technology TSMC 0.18μm CMOS technology Model Name Aspect (W/L)

M1,M2,M13 NCH 1.2/0.36 m=20

M3,M4,M5,M9,M12,M14,M17,M19 PCH 0.44/0.6

M6 PCH 0.44/0.6 m=10

M7,M8,M10,M11,M15,M16,M18,M20 NCH 0.3/1.4

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Chapter 4 Simulation and Experimental Results

Figure 4.3 shows the PTAT voltage versus temperature for all-MOS-based PTAT reference simulated in TSMC 0.13μm 1P8M standard CMOS technology. The simulation range is from -55°C to 170°C temperature range conduced for each circuit. The R-squares of all-MOS-based circuits are 0.99969 and 0.99968.

Figure 4.4 shows the PTAT voltage versus temperature for all-MOS-based IOAT reference simulated in TSMC 0.13μm 1P8M standard CMOS technology. The simulation range is from -55°C to 170°C for each circuit. The means of all-MOS-based circuit is 417.26mV. Table 4.4 summarized this simulation. All the transistors aspects are shown in Table 4.5.

Table 4.4 Summary of TSMC 0.13μm CMOS technology simulation result

−40 −20 0 20 40 60 80 100 120 140 160 80 90 100 110 120 130 Temperature = −55 to 170 DEG−C V(T) mV

Temperature VS. PTAT Voltage (TSMC 0.13um CMOS technology) SImulation Result

Linear Regression

Figure 4.3 The simulation result of PTAT reference simulated in TSMC 0.13μm CMOS technology. PTAT Temperature Coefficient (mV∕°C) PTAT R-square IOAT Mean (mV) All-MOS (0.13μm) 0.267 0.99969 417.26

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Chapter 4 Simulation and Experimental Results −40 −20 0 20 40 60 80 100 120 140 160 416 416.5 417 417.5 418 418.5 Temperature = −55 to 170 [DEG−C] Vref(T) [mV]

Temperature VS. Reference Voltage (TSMC 0.13um CMOS technology)

Figure 4.4 The simulation result of IOAT reference simulated in TSMC 0.13μm CMOS technology.

Table 4.5 Aspect of all-MOS-based circuit in TSMC 0.13μm CMOS technology TSMC 0.13μm CMOS technology Model Name Aspect (W/L)

M1,M2,M13 N 0.6/0.2 m=20 M3,M4,M5,M9,M12,M14,M17,M19 P 0.2/0.3 M6 P 0.2/0.3 m=10 M7,M8,M10,M11,M16,M18,M20 N 0.2/0.7 Mc N 0.6/0.18 m=132 M15 N 0.2/0.6

Above all, we know that all-MOS-based circuitry architecture takes advantage of both area and performance. Figure 4.5 shows both PTAT and IOAT voltage references together. The simulation results done with TSMC 0.18μm and 0.13μm CMOS technology have shown all-MOS-based circuit is well-work in this two kinds of technology. In next session, the layout in TSMC 0.18μm CMOS technology is presented. The layout concept is also described. The post-layout simulation is shown

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Chapter 4 Simulation and Experimental Results −40 −20 0 20 40 60 80 100 120 140 160 100 150 200 250 300 350 400 Temperature = −55 to 170 DEG−C V(T) mV

Temperature VS. Reference Voltage (TSMC 0.13um CMOS technology)

Figure 4.5 The simulation results of both PTAT and IOAT references simulated in TSMC 0.13μm CMOS technology.

4.2 Layout Consideration and Post-layout Simulation

Before we start the layout implementation, the fine tuning concept has to be considered. The positive and negative temperature coefficients will be changed due to the change of current ratio after LPE (PEX). So the constant K which we introduce in Chapter 3 has to be modified after LPE (PEX). Our design flow is shown in figure 4.6. Figure 4.7 shows the layout of all-MOS-based circuit which is designed with TSMC 0.18μm 1P6M CMOS technology. Because of fine tuning consideration, the length of M15 is designed to be easily changed in the layout. The supply voltage is 1.2v and area is about 42um 31× um(1260um ). Figure 4.8 and 4.9 show the post-layout 2 simulation of PTAT and IOAT references before fine tuning. Figure 4.10 and 4.11 show the post-layout simulation of PTAT and IOAT references after fine tuning. The post-layout simulation results compared with pre-layout simulation result are summarized in Table 4.6. In next session, we have a discussion on these simulation results and some considerations for applying our circuit in smart temperature sensors.

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Chapter 4 Simulation and Experimental Results

Figure 4.6 The block diagram of our design flow.

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Chapter 4 Simulation and Experimental Results −40 −20 0 20 40 60 80 100 120 140 160 80 90 100 110 120 130 Temperature = −55 to 170 DEG−C V(T) mV

Temperature VS. PTAT Voltage (TSMC 0.18um CMOS technology) Post−sim Result

Linear Regression

Figure 4.8 Post-layout simulation of PTAT reference before tuning.

−40 −20 0 20 40 60 80 100 120 140 160 423 424 425 426 427 428 429 430 431 432 433 Temperature = −55 to 170 [DEG−C] Vref(T) [mV]

Temperature VS. Reference Voltage (TSMC 0.18um CMOS technology)

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Chapter 4 Simulation and Experimental Results −40 −20 0 20 40 60 80 100 120 140 160 80 90 100 110 120 130 Temperature = −55 to 170 DEG−C V(T) mV

Temperature VS. PTAT Voltage (TSMC 0.18um CMOS technology)

Sumulation Result Linear Regression

Figure 4.10 Post-layout simulation of PTAT reference after tuning.

−40 −20 0 20 40 60 80 100 120 140 160 421 421.5 422 422.5 423 Temperature = −55 to 170 [DEG−C] Vref(T) [mV]

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Chapter 4 Simulation and Experimental Results

Table 4.6 Simulation summary of all-MOS-based circuitry architecture

4.3 Discussion

According to the post-layout simulation results, we know that the linearity of PTAT is almost the same with pre-layout simulation results. It means the compensation circuit (M17-M20, and Mc) is efficient. But the variation of IOAT is dependent on the process variance. In this work, we run the design flow to get the optimization of IOAT in the simulation level. The results also prove the improvement of IOAT by fine tuning.

In order to apply our work in smart temperature sensors, the level shift circuit has to design. When we take PTAT and IOAT as temperature signals, the first thing we have to do is to shift PTAT and IOAT in order to produce a cross point. The cross point will be defined as reference voltage at certain temperature. And if we subtract PTAT from this cross point, the difference will be taken as temperature difference signal. After the process of A/D converter, the digital value of temperature will be presented.

Above all, we can know how to improve the variation of IOAT and some design concepts for using this proposed circuit and some considerations for applying our circuit in smart temperature sensors. The conclusions and future works are discussed in next Chapter. All-MOS-based (0.18μm) Power (μW) PTAT TC (mV∕°C) PTAT R-square IOAT Variance* (mV) Pre-sim 18.4773 0.276 0.99968 87.12 Post-sim 27.8820 0.257 0.99787 142.49 Post-sim (after tuning) 28.5227 0.264 0.99788 28.46

− =[ ( () )2]12 *Variance y i mean

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Chapter 5 Conclusions and Future Works

CHAPTER

5

Conclusions and Future Works

In the previous Chapter, simulation and experimental results have been shown. Basing on those results, we make some conclusions of proposed design. Section 5.1 describes the conclusions of this thesis. The long term future works are also discussed in Section 5.2.

5.1 Conclusions

At the beginning, we review the temperature sensing methods, from mercury-in-glass thermometer to very low power and low cost smart temperature sensors. Then we discuss the advantages and disadvantages of both bipolar transistors and subthreshold MOSFETs for the low power design. Finally, we proposed new PTAT and IOAT reference circuitry architectures and show the simulation and experimental results.

In this thesis, -55 Co

to 170 Co

high linear voltage references circuitry for fully integrated temperature sensor is designed and implemented in TSMC 0.13μm and 0.18μm CMOS technology. The proposed circuit utilized temperature complementation technique on PTAT and IOAT references. Base on the simulation results, the R-squares of both circuitries are better than 0.999 in a considerable wider temperature range from -55 Co

to 170 Co

as shown in the Chapter 4. Thus, a fully integrated temperature sensor with wider temperature range is designed and easily to integrate to modern system-on-chip designs with minimal efforts. In a world, we can make three points to conclude the thesis.

1. Propose the architecture based on subthreshold MOSFETS that produce both

VPTAT and VREF. And the circuitry is working in both TSMC 0.18μm and 0.13μm CMOS technology.

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Chapter 5 Conclusions and Future Works Thermal Sensor Interface Circuit Thermal (Power) Control Mechanics Thermal-Aware Power Management

Figure 5.1 The block diagram of the thermal-aware power management system.

3. A fully integrated temperature sensor with wider temperature range (-55~170 Co )

is designed and easily to integrate to modern SOC designs with minimal efforts.

5.2 Future Works

Our long term goal is to implement the thermal-aware power management. The mid term goal is to structure a very low power and high performance smart temperature sensor. After this thesis’ work, the next step will be to research how to efficiently combine this PTAT and IOAT reference circuitry architecture with A/D converter. However, some dynamic offset-cancellation techniques should be applied in order to maintain or even improve the performance. Finally, integrate with digital interface bus to get the digital output for the thermal-aware power management. Figure 5.1 shows the block diagram of this system.

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References

REFERENCES

[1] M. N. Sabry, A. Bontemps, V. Aubert, and R. Vahrmann, “Realistic and Efficient Simulation of Electro-Thermal Effects in VLSI Circuits,” IEEE Tran. on VLSI

systems, vol.5 pp. 277-282, 1997.

[2] V. Szekely, M. Rencz, and B. Courtois, “Thermal Testing Methods to Increase System Reliability,” presented at 13th IEEE SEMI-THERM Symposium, Austin, Texas 1997.

[3] Y. S. Ju, K. Kurabayashi, and K. E. Goodson, “Thermal Characterization of IC Interconnect Passivation Using Joule Heating and Optical Thermometry,” Microscale Thermalphysical Engineering, vol. 2, pp. 101-110, 1998.

[4] Y. S. Ju, and K. E. Goodson, “Thermal Mapping of interconnects subjected to Brief Electrical Stresses,” IEEE Electron Device Lett. vol. 18, pp. 512-514, Nov. 1997.

[5] Y. S. Ju, O. W. Kading, Y. K. Leung, S. S. Wong, and K. E. Goodson, “Short-Timescale Thermal Mapping of Semiconductor Devices,” IEEE Electro

Device Lett. vol. 18, pp. 169-171, Nov. 1997.

[6] Y. Jiang and E. K. F. Lee, "Design of low-voltage bandgap reference using transimpe-dance amplifier," IEEE Trans. Circuits Syst. II, vol.47, pp. 552-555, June 2000.

[7] E. Vittoz and J.Fellrath, "CMOS analog circuits based on weak inversion operation," IEEE J. Solid-State Circuits, vol.SC-12, pp. 224-231, June 1977.

[8] F. Serra-Graells and J. L. Huertas, "Sub-1-V CMOS proportional-to-absolute temperature references," IEEE J. Solid-State Circuits, vol.38, pp. 84-88, Jan. 2003.

[9] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol.24, pp. 1433-1440, Oct. 1989.

[10] F. Forti and M. E. Wright, "Measurement of MOS current mismatch in the weak inversion region," IEEE J. Solid-State Circuits, vol.29, pp. 138-142, Feb. 1994. [11] Chih-Ming Chang, and Herming Chiueh, “A CMOS Proportional-to-Absolute

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References

[12] A. Buck, C. McDonald, S. Lewis, and T. R. Viswanathan, “A CMOS bandgap reference without resistors,” in Proc. IEEE Int. Solid-State Circuit Conf., 2000, pp. 442-443.

[13] H. J. Oguey and D. Aebischer, “CMOS current reference without resistance,”

IEEE J. Solid-State Circuits, vol. 32, pp. 1132-1135, July 1997.

[14] H. Sanchez, R. Philip, J. Alvarez, and G. Gerosa, “A CMOS temperature sensor for PowerPCTMRISC microprocessors,” in Proc. IEEE Symp. VLSI Circuits, June 1997, pp. 13-14.

[15] Poki Chen, Member, IEEE, Chun-Chi Chen, Chin-Chung Tsai, and Wen-Fu Lu, “A Time-to-Digital-Converter-Based CMOS Smart Temperature Sensor,” IEEE J.

Solid-State Circuits, vol. 40, No. 8, pp. 1642-1648, Aug. 2005.

[16] G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutri, “A Low-Voltage Low-Power Reference Based on Subthreshold MOSFETs,” IEEE J. Solid-State

Circuits, vol. 38, No. 1, Jan. 2003.

[17] C. C. Enz, F. Krummenacher, and E. A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications,” J. Analog Integrated Circuits Signal Process, vol. 8, pp. 83-114, 1995.

[18] Chih-Ming Chang, “The design and implementation of CMOS PTAT reference for monolithic temperature sensors,” National Chiao-Tung University, Taiwan, July 2004.

數據

Figure 1.1 Block diagram of a thermal aware system.
Figure 2.1 Communication between a temperature sensor and a computer.  applied are getting more and more complex
Figure 2.3 Generation of PTAT voltage with bipolar transistors.
Figure 2.4 The simulation prototypes.
+7

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When the specimen with 1mm 2 in square put on the silicon dissipation plate after the sapphire substrate was removed, it was fond that the measured junction temperature can be