Design and characterization of a 200 V, 45 A all-GaN HEMT-based
Po-Chien Chou, Stone Cheng*
Department of Mechanical Engineering, National Chiao Tung University, No. 1001, University Road, Hsinchu 30010, Taiwan
h i g h l i g h t s
This work proposes the design, development, and testing of all-GaN power module. We develop module package and determine their thermal and electrical properties. ID-VDS characteristics are obtained over a wide range of base plate temperatures. Self-heating in GaN HEMTs is studied by electrical analysis and IR thermography.
a r t i c l e i n f o
Article history: Received 19 April 2013 Accepted 3 July 2013 Available online 12 July 2013 Keywords:
Power semiconductor devices Power module
Thermal management IR thermal image
a b s t r a c t
Emerging gallium nitride (GaN)-based high electron mobility transistor (HEMT) technology has the potential to make lower loss and higher power switching characteristics than those made using tradi-tional silicon (Si) components. This work designed, developed, and tested an all-GaN-based power module. In a 200 V, 45 A module, each switching element comprises three GaN chips in parallel, each of which includes six 2.1 A AlGaN/GaN-on-Si HEMT cells. The cells are wire-bonded in parallel to scale up the power rating. Static ID-VDScharacteristics of the module are experimentally obtained over widely
varying base plate temperatures, and a low on-state resistance is obtained at an elevated temperature of 125C. The fabricated module has a blocking voltage exceeding 200 V at a reverse-leakage current density below 1 mA/mm. Two standard temperature measurements are made to provide a simple means of determining mean cell temperature in the module. Self-heating in AlGaN/GaN HEMTs is studied by electrical analysis and infrared thermography. Electrical analysis provides fast temperature overviews while infrared thermography reveals temperature behavior in selected active regions. The current dis-tribution among cells was acceptable over the measured operating temperature range. The character-ization of electrical performance and mechanical performance conﬁrm the potential use of the packaged module for high-power applications.
Crown CopyrightÓ 2013 Published by Elsevier Ltd. All rights reserved.
The AlGaN/GaN high electron mobility transistor (HEMT) is an important state-of-the-art technology for achieving a high break-down voltage, a wide bandgap, a high power density and a high
switching frequency[1,2]. The GaN is now one of the wide bandgap
materials used in advanced power electronic devices. The high
breakdown ﬁeld of GaN (3.5e5 * 106 V/cm) compared to Si
(0.3 * 106V/cm) is attractive because it enables GaN-based devices
to operate at high voltages and low leakage currents. The high
electron mobility (2000 cm2/V-s) and electron saturation velocity
(2.5 * 107cm/s) also enable high frequency operation. Because of
the close match between its thermal coefﬁcient of expansion and
that of insulating ceramics, its reasonable electron mobility, and a thermal conductivity value that does not differ much from that of Si [3,4]. However, although various studies of the power characteris-tics of GaN HEMTs have considered their performance on-wafer load-pull level, none has considered the effects of practical
as-sembly and packaging[5e9]. Since high power densities
substan-tially increase temperature in the transistor channel, accurate estimates and measurements of junction temperatures are essen-tial for designing power modules. Recently, the enhanced material properties of silicon carbide (SiC) have been exploited to improve the performance of high-power electronic device modules over
those of GaN components[10e14]. Although the quality and size of
GaN wafers have rapidly improved, some devices that use such * Corresponding author.
E-mail address:firstname.lastname@example.org(S. Cheng).
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Applied Thermal Engineering
j o u r n a l h o me p a g e : w w w . e l s e v i e r . c o m / l o c a t e / a p t h e r m e n g
1359-4311/$e see front matter Crown Copyright Ó 2013 Published by Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.applthermaleng.2013.07.004
wafers have inherent material defects, especially when operated in parallel at high power. The processes used to manufacture high quality GaN substrates, i.e., substrates with few defects, are also still in their early stages and are much less mature than those for manufacturing SiC. To evaluate the potential use of GaN technology in high power applications, a power module with multiple parallel GaN HEMT cells is needed. The thermal management requirements and the current distribution during switching affect the operation of the GaN power module and the switch utilization factor of
par-allel switches. The positive temperature coefﬁcients of GaN
switches facilitate current sharing during conduction. This work fabricated a GaN power module with a high current rating by connecting multiple GaN power HEMTs in parallel.
2. Fabrication process and structure of AlGaN/GaN HEMT device
The AlGaN/GaN heterostructure pattern is formed by metal
organic chemical vapor deposition (MOCVD) on a 625
silicon substrate. To improve process control, the growth rate, layer thickness, and surface roughness are optically monitored in real time by in situ pyrometry to support the molecular beam epitaxial
growth of GaN on the Si (111) substrate.Fig. 1presents the regularly
stacked cross-section of the fabricated AlGaN/GaN HEMT structure.
mm-thick GaN buffer layer, a 25 nm-thick Al0.25Ga0.75N barrier
layer and,ﬁnally, a 4 nm-thick GaN capping layer were deposited
on the epitaxial structure, which comprised a 120 nm-thick AlN spacer layer. The device was isolated using inductively coupled
plasma reactive ion etching (ICP-RIE) with Cl2-based gas. Source
and drain Ohmic contacts were formed by evaporating the Ti/Al/Ni/ Au (20 nm/120 nm/25 nm/5100 nm) multi-layers and then
annealing in a nitrogen atmosphere at 800C for 60 s. An ohmic
contact resistance of 3 106
Ucm2was obtained by TLM method.
The surface of the GaN capping layer used as the main dielectric coating was passivated by low-pressure chemical vapor deposition
(LPCVD) of a 50 nm-thick Si3N4layer. In the two-step process for
deﬁning the gate, a U-groove was etched to penetrate the LPCVD
Si3N4 layer. Schottky contacts were formed from Ni/Au (20 nm/
150 nm) multi-layers. The surface was again passivated with a
second 100 nm-thick Si3N4 layer, which was grown by
plasma-enhanced chemical vapor deposition (PECVD) at 300 C .
Source-terminated ﬁeld plates were deposited to improve the
electricﬁeld distribution on the drain side near the gate edge to
increase the breakdown voltage and to reduce current collapse. The ﬁeld plate was connected to the source electrode and extended
mm over and away from the gate-to-drain region. The
source-to-gate distance and channel length between the source and drain
mm and 20
mm, respectively[16,17]. Finally, a 6
plating process was used to fabricate an air-bridge connecting the
two sides of the electrodeﬁngers.
Fig. 2 presents the AlGaN/GaN HEMT structure comprising Ohmic and Schottky contacts formed by periodically arranging
multiple metalﬁngers. The upper gate structure (gate ﬁngers and
interconnects) partially overlap the source structure. The plated
air-bridge gate interconnects connect the adjacent gateﬁngers of the
transistor array through bridges that cross over the source and
drainﬁngers. The studied device layout includes 60 gate ﬁngers (6
cell; gate length, 2
mm; gate width, 500
mm), and the total width of
the gate periphery is 30 mm. The active device area is 0.25 mm2
with a 50
mm pitch separating adjacent gateﬁngers and includes
source and drain contact regions.
3. Multiple-chip gallium nitride power module packaging 3.1. GaN power module design
This work elucidates the packaging and thermal management of
numerous GaN HEMTs devices connected in parallel.Fig. 3shows a
photograph and schematic diagram of the multiple-chip GaN po-wer module. Owing to the high material and processing costs associated with GaN HEMT devices, GaN-based devices have low
yield, and few dies canﬁt on the wafer compared to silicon-based
devices. Therefore, multiple small devices are usually connected
in parallel in a power module. Such a module must use a GaN
multiple-chip array packaging and layout design to ensure
high-power and highly efﬁcient operation. The module packaging
design must meet satisfy requirements for parallel interconnection among modules, high current handling capability and low on-state
resistance.Fig. 3(b) shows that each module contains an array of 12
GaN HEMT devices arranged in four rows of three devices. Half of the six cells in each device are connected in parallel to form a switch with a high current rating. In the power module, the
sub-strate layout comprises four switch combinations, C1eC4, which
constitutes the full-bridge switching circuit. The four switch com-binations form two bridge arms: one formed from C1 and C2 and one formed from C3 and C4. This method reduces the size of the module and increases the feasibility of connecting modules in parallel.
3.2. Fabrication and assembly of process module
Module packaging and assembly is simpliﬁed by applying the
module concept used in a standard Insulated Gate Bipolar
Tran-sistor (IGBT) (rated 600 V, 75 A) package.Fig. 4displays the
sub-strates, chip-on-board assemblies and package housing selected for the GaN power module. The GaN HEMT devices are attached to an etched direct bond copper (DBC) aluminum nitride (AlN) substrate.
To provide sufﬁcient heat removal capacity, ceramics with a high
thermal conductivity (230 W/mK) and high coefﬁcients of thermal
expansion (CTE) comparable to those of silicon are used. The circuit is laid out to optimize both the chip arrangement and the electrical interconnect (wire bonding layout and location of auxiliary con-tact). The power modules are packaged using advanced wire bond interconnection technology, and multiple wire bonds are used to obtain low-induction interconnects. The gold wires have a
diam-eter of 30e50
mm to provide the required current carrying capacity
and the required size of the bond pad. Silver sintering-bonding is
used to attach two wire-bond assemblies to a stainless steelﬂat
base (heat spreader). Finally, the plastic casing is glued to the DBC substrates, and a silicone gel is coated on the module to provide
electrical insulation and physical protection.
Fig. 1. Cross-section of AlGaN/GaN HEMT with sourceﬁeld plate structure.
3.3. Performance testing and evaluation
During fabrication of a multiple-chip GaN power module incorporating 36 GaN HEMT cells, six cells became inoperable, which left 30 cells available for use in the module. Preliminary electrical testing showed that eight cells were degraded. Hence, only the test results for a multiple-chip module with 22 GaN HEMT cells are reported. The static electrical characteristics of the pro-totype module were measured as functions of base plate
temper-ature.Fig. 5plots the currentevoltage (ID VDS) characteristics of
the 12 parallel GaN HEMT devices at 25C and 125C[20e22]. The
measurements were made using a double-channel source meter by
pulsing the gate-source voltage (VGS) at 100 Hz with a duty cycle of
0.1%. This gate pulse width and duty cycle supported ID VDS
measurement with negligible trapping and thermal effects. The
IDVDScharacteristics were obtained at VGSfrom4 V to 1 V in
steps of 1 V. As expected, the drain current (ID) through the GaN
HEMT devices declined as the base plate temperature increased. Analysis of the static electrical characteristics of the assembled prototype module revealed a low on-state resistance and a high
static current capacity of 45.5 A at 25C and 31.1 A at 125C. The
positive temperature coefﬁcient facilitates the use of these cells in
parallel and reduces their overall on-resistance. The shared current must be highly uniform in all cells to prevent an excessive current from overloading the cells. To obtain a uniform distribution of current among all-GaN HEMT cells, all electrical properties, including on-resistance, threshold voltage, and leakage currents,
were matched as closely as possible[23,24]. The module remained
stable under forward bias with no signiﬁcant change in
character-istics, and the base plate maintained the temperature range of the
module at 25Ce125C.
In a switching operation, the GaN HEMT transistors alternate between the on-state, in which the gate opens the channel and
allows the currentﬂow, and the off-state, in which the gate closes
the channel and blocks the currentﬂow. Efﬁcient power switching
is associated with operation at a high off-state blocking voltage and
with leakage current below the speciﬁed limit. The breakdown
voltage, which is measured with a curve tracer, is deﬁned as the
voltage at which the leakage current reaches 1 mA/mm with the
gate biased below the threshold voltage.Fig. 6plots the off-state
leakage current as a function of drain-to-source voltage (VDS)
un-der a VGSof4 V. As VDSwas swept forward from 0 V to 200 V, the
maximum voltage at which leakage was limited to 1 mA/mm
increased steadily. The drain (ID) and gate (IG) leakage current
densities in the pulsed-mode reached as low as 278 nA/mm and 306 nA/mm at 200 V, respectively, which were three orders of Fig. 3. Development of multiple-chip GaN power module. (a) Photograph of prototype
high power density package based on all-GaN-based power devices. (b) Circuit dia-gram of power module.
Fig. 2. Photograph and schematic diagram of the HEMTs. (a) Photograph of ten-ﬁnger HEMT with air-bridge gate interconnection. (b) Overall die size is 1400mm 1300mm (six cells) 0.625 mm (thickness).
magnitude lower than the maximum on-state current. However, the GaN power devices had high gate leakage currents resulting from their surface states, which included dislocations in the buffer
layer and plasma-induced etch damage. The tested prototype
GaN power module had a high current carrying capacity and a maximum blocking voltage exceeding 200 V.
4. Thermal management in GaN HEMTs
Infrared (IR) imaging and electrical test method were used to analyze temperature increases caused by self-heating in the GaN power module. Local temperature distributions in the power module were measured by IR thermography; however, the spatial
resolution of IR analysis is only
mm to mm, depending on the
equipment used[27e29]. Electrical test method is typically used to
measure mean channel temperature in the active area of the
module[30e32]. Therefore, combining both methods can rapidly
identify hot spots and accurately determine temperature in a multiple-chip GaN power module.
Fig. 4. Module packaging and assembly procedures. (a) Silver-sintering die-attach on the gold-coated DBC substrate. (b) Wire-bond interconnection installed as needed. (c) Electrical testing. (d) Electronic module housing and assembly with integrated heat sink. (e) External pin connection. (f) Silicone gel encapsulation (potting).
0 5 10 15 20 25 30 35 40 45 50 0 1 2 3 4 5 6 7 8 9 10 ID (A ) VDS (V)
at room base plate temperature 25 C at 125 C base plate temperature
Fig. 5. Each static ID VDScurve is plotted (VGSfrom4 V to 1 V) at base plate temperatures from room-temperature (25C) to 125C.
4.1. Infrared thermal measurements of surface temperature
Thermal infrared (IR) measurements can determine junction-to-case (package) temperature differentials, which can then be used to calculate the thermal resistance of the package. Thermal IR
mi-croscopy performed using a liquid nitrogen-cooled 256 256
in-diumeantimonide (InSb) focal plane array can detect wavelengths
from 3 to 5
mm. To perform an IR measurement, the multiple
de-vices under test (DUT) on the AlN substrates are held in the test ﬁxture mounted on top of a temperature-controlled stage. To
ensure effective heat dissipation, the air gaps areﬁlled with thin
layers of thermal grease to reduce the thermal contact/interfacial resistance. Finally, a sensor thermocouple is attached to monitor substrate temperature. The IR detector and the embedded ther-mocouple are calibrated against each other.
The interior of the GaN power module was sprayed with a thin coating of boron nitride (BN) to ensure that the emissivity of the component surface was in infrared wavelengths detectable by the
IR detector. Each device switch was biased at a gate voltage
(VGS) of 0 V. Power dissipation from 1 W to 10 W per cell was
determined by multiplying the drain currents by their
Fig. 7. Thermal maps (left) and line scan proﬁles (right) based on thermal map for various power dissipations: (a) 5 W, (b) 7 W, (c) 10 W. Temperature line scan recorded along a line (trace A0 B0) perpendicular to gateﬁngers near central region.
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 25 50 75 100 125 150 175 200 IG (m A /mm) ID (m A /mm) VDS
IG VGS= -4 V
Fig. 6. Three-terminal off-state breakdown characteristics of GaN power module at VGS¼ 4 V. For VDS< 200 V, the leakage current density is less than the pre-speciﬁed benchmark of 1 mA/mm.
corresponding drain-to-source voltage (VDS) values.Fig. 7plots the
IR temperature proﬁles obtained from the maximum cell
temper-atures within the module. The GaN devices were characterized at
three power dissipations, (W)e 5 W, 7 W and 10 W, and at a base
plate temperature of 60C. Joule heat is generated along narrow
strips near the edge of the gates in the gate-to-drain extension regions, where the maximum surface temperature increases from
104.4 to 154.3C as the dissipated power increases from 5 to 10 W.
At high power dissipation, the line scan proﬁles (line traces) reveal
a steep temperature gradient along theﬁnger between the source
and the drain. Here, the effects of heat coupling between the
ﬁn-gers, which induce thermal crosstalk, are negligible.
In each static DC thermal characterization, measured IDand VDS
characteristics are recorded along with corresponding surface
temperature distributions. InfraScopeÔimage analysis software is
used to measure mean HEMT cell temperatures in each active
mm). The individually measurements are then
averaged to provide a reference temperature for analyzing the
temperature increase in the module. InFig. 8, the values are used to
plot total power dissipation. Although thermal conductivity typi-cally depends on temperature, the relationship between power
dissipation and temperatures up to 50C is presumably linear since
the dependence is weak. A slight temperature variation observed in the parallel cells resulted from a non-uniform current distribution. Thermal placement and increased heat dissipation enhanced the
effect. Linear curveﬁtting showed that the thermal resistance, i.e.,
the gradient of temperature increase, in the module was 0.3252C/
W. For reference, the normalized thermal resistance (assuming
uniform temperature over the active region) is 1.7886C mm2/W
[34e37]. Since accurate IR temperature measurements were
pre-cluded by the silicone potting compound, the module was not encapsulated during the measurements. Therefore, the peak voltage stress on the drain and the temperature were limited
dur-ing testdur-ing. After sufﬁcient IR thermal data were collected, the
boron nitride coating was removed, and the module wasﬁlled with
silicone gel for further electrical testing.
4.2. Electrical method for measuring channel temperature
The temperature-dependence of the forward gate-source Schottky junction voltage was used as the temperature-sensitive
parameter in the pulsed switching technique [38,39]. However,
this technique was difﬁcult to perform because applying a gate bias
produces a large forward gate current and a high temperature, which degrades the Schottky contact of the GaN HEMTs. Therefore, channel temperature was estimated in terms of
performance-related electrical parameters, e.g, maximum drain current IDmax
and speciﬁc drain-to-source resistance RONknown to be associated
with channel temperature.
Fig. 9(a) plots the ID VDS characteristics of the packaged
module at base plate temperatures of 30Ce180C. The plot was
obtained by sweeping VDSfrom 0 V to VDS(max¼ 4 V) with VGSset
to 0 V. Synchronized gate/drain pulsing is performed in packaged
devices to prevent self-heating and carrier trapping.
Calibra-tion performed using pulse current as a reference for channel
temperature established that, based on ID VDScharacteristics, no
power was dissipated, and no traps were produced by external
electricﬁelds. The maximum drain current IDmax(drain current at
VDS¼ 4 V and VGS¼ 0 V) declined as the base plate temperature
increased because of the reduced electron mobility at elevated
temperatures.Fig. 9(b) shows the linearity obtained at a base plate
temperature range of 30Ce180C. According to the slope for the
pulsed ID VDScurves inFig. 9(a), the RONvalues for VDS¼ 2 V are
15.84, 17.63, 20.39, 23.71, 27.82, and 33.23U mm. The extracted
pulsed IDmaxand RONare used to determine power dissipation and
to generate a lookup table for rapid estimation of actual channel temperature. 0 10 20 30 40 50 60 70 22 44 66 88 110 132 154 176 198 220 T emp erat u re ri se (º C) Power dissipation (W)
Fig. 8. Experimental IR data indicating a rise in mean cell temperatures at various power dissipations and a base plate temperature of 60C.
0 25 50 75 100 125 150 175 200 225 250 0 0.5 1 1.5 2 2.5 3 3.5 4 D rai n cu rren t ID (mA /mm) VDS(V) 30ºC 60ºC 90ºC 120ºC 150ºC 180ºC Temperature ↑
(a)ID MAX RON 15 18 21 24 27 30 33 110 130 150 170 190 210 230 250 30 60 90 120 150 180 D y n ami c res is ta n ce R ON ( mm) D rai n cu rren t ID m ax (mA /mm)
Base plate temperature (°C)
Fig. 9. (a) Pulsed ID VDSmeasurements from a quiescent bias point (VDS¼ VGS¼ 0 V) without power dissipation at various base plate temperatures. The VDSis swept from 0 V to 4 V when VGSis set to 0 V. (b) Extracted IDmaxand RONexhibit a highly linear relationship from 30C to 180C. Electrical measurements conﬁrmed that channel temperature was related to power dissipation.
Fig. 10presents the cell channel temperatures (solid line)
ob-tained from the pulsed IDmax and RON. For comparison, the cell
surface temperatures (dashed line) extracted from the thermal IR
data are also shown. At operating temperatures from 60 C to
150C, the channel temperatures estimated by pulsed IDmax
mea-surement agree with those estimated by RON measurement,
particularly at low power dissipations. The channel temperatures considerably exceed those measured by IR imaging. These experi-mental results are reasonable because the electrical method aver-ages channel temperatures throughout the active channel region.
At elevated base plate temperatures, pulsed IeV measurements
provide an indirect estimate of channel temperature in the
pack-aged module. Although the pulsed IeV measurements yield a
similar temperature rise at low power levels, the temperature be-gins to diverge from temperature measurements obtained when power dissipation exceeds 8 W per cell. This divergence is
attrib-utable to the calibration process and the 180C limitation on base
plate temperature applied in the electrical method. Since the actual channel temperature exceeds that measured by the electrical method during the calibration process, channel temperature may be underestimated. Instead of providing spatial information about the temperature distribution, the proposed electrical method
ob-tains average temperature across the sourceedrain opening, which
is a non-uniform value in the HEMT cell. However, silicone gels, including those used for insulating and packaging high-voltage modules, distort IR radiation signatures. Hence, a simple method of extrapolating to higher temperatures of an encapsulated module during dynamic operation is needed. The underestimated channel temperature is acceptable for a packaged module in which heat is generated uniformly among cells with no obvious local hot spots. Since the electrical method is not limited by the package encap-sulations, the underestimated channel temperature does not limit the use of the electrical method as a fast method of estimating channel temperature in a packaged GAN power module.
Improvements in GaN HEMT fabrication technology enable fabrication of 400 V cells that can be operated at 2.1 A with low on-state resistance and low switching loss. To support high-power
applications, the cells can be used for parallel interconnections in
all-GaN-based power modules with a multiple-chip conﬁguration.
The module designs include four power switches in a full-bridge
arrangement. Experimental results conﬁrm the high-current
ca-pacity of 22 GaN HEMT cells connected in parallel. The static
ID VDScharacteristics of the module do not signiﬁcantly differ
between base plate temperatures of 25 and 125C. The fabricated
module has a blocking voltage exceeding 200 V and a leakage current density below 1 mA/mm. Thermal infrared characteriza-tions of thermal resistance and temperature, which rise as a func-tion of power dissipafunc-tion, are used to determine the surface temperature of the module during operation. In this experiment,
the maximum average surface temperature reached 127.7C at a
base plate temperature of 60C, which corresponded to a thermal
resistance of 0.3252 C/W. The electrical technique is also an
effective non-destructive method for comparatively analyzing module temperature. It averages channel temperature within the active region of cells by using sub-microsecond pulses to measure
IDmax and RON. The consistent estimates of channel temperature
obtained by the technique were conﬁrmed by the close agreement
between temperatures determined by IDmax and RON. These
per-formance evaluations, and the results on which they are based,
conﬁrm the feasibility of a multiple-chip GaN power module for
high-power applications with parallel interconnections. Acknowledgements
This work was supported by the MOEA project 101-EC-17-A-05-S1-154, and NSC project NSC 101-2221-E-009-036, Taiwan, R.O.C.. The authors would like to thank Horace Chen of Keithley In-struments for his very helpful suggestions and technical support. References
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