560 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 20, NO. 10, OCTOBER 2010
A 60 GHz Injection-Locked Frequency
Tripler With Spur Suppression
Chien-Nan Kuo, Member, IEEE, and Tzu-Chao Yan
Abstract—A 60 GHz injection-locked frequency tripler is
designed to improve spectral purity with spur suppression of the fundamental and the even-order harmonics. Several circuit designs are utilized in the harmonic current injection circuit to maximize the third-order harmonic and minimize the undesired harmonic current outputs, including notch filters and a capacitive cross-coupled transistor pair. With the input signal of 0.5 dBm at 19.7 GHz, the harmonic rejection ratios of the fundamental, and the second-order achieve 31.3 dBc, and 45.8 dBc, respectively. Implemented in 0.13 m CMOS technology, the core circuit consumes power of 9.96 mW with 1.2 V supply voltage. The entire die occupies an area of 985 866 m2
Index Terms—Capacitive cross-coupling, frequency tripler,
in-jection-locking, notch filter.
I. INTRODUCTION
I
NJECTION locking has been found useful in RF inte-grated circuit design. One interesting application is the frequency tripler circuit for LO signal generation in 60 GHz millimeter-wave transceivers [1]–[3]. At such a high frequency, the conventional tripler with a nonlinear device or a hard-limiter generates the third-order harmonic output in a power-hungry manner. The injection-locking approach is an extension to allow a large output voltage assisted by an oscillator such that frequency tripling comes efficiently in power consumption. The oscillator tank is chosen with a low -value to enlarge the locking frequency range, namely, the operation range.A critical issue of the injection-locked tripler is spectral pu-rity. To LO signals, spurious noise is required as low as possible to avoid any undesired frequency conversion of interferers. The typical injection node is often directly at the oscillator output nodes [1], [2], [4]. Although oscillator locking is limited to the third-order harmonic frequency range, undesired spurious noise from the harmonic generator still directly feeds through and ap-pears at the output. Suppression is insufficient by the low-Q os-cillator tank. It is typical to apply additional external filtering. In this work, circuit design is aimed at spur rejection by several techniques, and verified with a 60 GHz tripler in 0.13 m RF CMOS technology.
Manuscript received January 21, 2010; revised May 06, 2010, June 17, 2010; accepted July 13, 2010. Date of publication September 07, 2010; date of cur-rent version October 06, 2010. This work was supported jointly by National Science Council, Taiwan, under the Grant NSC 97-2220-E009-010, the Medi-aTek Center at NCTU, also is supported by Chip Implementation Center (CIC) for chip fabrication and testing, and Ansoft Corp. for EDA tools.
The authors are with the Department of Electronics Engineering, National Chiao-Tung University (NCTU), Hsinchu 300, Taiwan. (e-mail: cnkuo@mail. nctu.edu.tw).
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LMWC.2010.2060260
Fig. 1. Injection-locked frequency tripler, including the output buffers for mea-surements. The differential harmonic injection circuitI is shown in Fig. 2.
Fig. 2. Differential harmonic injection circuit with spur suppression.
II. TRIPLERDESIGN
The injection-locked frequency tripler in this work is shown in Fig. 1. It consists of an oscillator and a differential harmonic current injection circuit. The oscillator is designed at the fre-quency around three times the input frefre-quency using the typical configuration of a cross-coupled pair, and . To-gether with parasitic capacitance at the transistor drain ports, the inductors and form the resonator without frequency control in this work. The third-order harmonic frequency locks the oscillator and turns it to a tripler. The locking range is deter-mined by the magnitude of third-order harmonic injection cur-rent and the -value of the LC tank [4].
The spur issue can be alleviated by the proposed differential harmonic injection circuit as shown in Fig. 2. Instead of using an external filter at the oscillator output, spurious noise is sup-pressed before injecting into the oscillator. Several circuit de-signs are utilized. They include a harmonic generator ( and ) with inductive load ( and ) for the third-order har-monic enhancement, a capacitive cross-coupled pair ( and ) for the even-order harmonic rejection, and a notch filter for the fundamental suppression. The design goal is a large har-monic rejection ratio (HRR), defined as
-- (1)
KUO AND YAN: A 60 GHZ INJECTION-LOCKED FREQUENCY TRIPLER WITH SPUR SUPPRESSION 561
Fig. 3. Contour plot of the generated third-order harmonic current for analysis of the optimal bias voltage and the drain load inductance.
Fig. 4. Micrograph of the fabricated frequency tripler.
Fig. 5. Output spectrum under the injection locked condition.
where n refers to the n -order harmonic.
and generate all harmonic currents of the funda-mental signal at the frequency . The loading impedance was suggested in [5] to be as low, low, and high at the frequency of , 2 and 3 , respectively, to enhance the third-order output current. are, therefore, placed to result in high-impedance resonance at 3 to meet this condition. Also the gate bias voltage, , affects the third-order nonlinearity. The optimal bias voltage and the load inductance, , are deter-mined by using the contour plot in Fig. 3. With of 0.6 V and of 200 pH, the third-order harmonic output current achieves 612.5 A.
The cascade configuration of and buffers the har-monic generator and relaxes the loading condition to the os-cillator tank. dc current is re-used with and . Since the
Fig. 6. Measured frequency locking range of the tripler.
Fig. 7. Measured harmonic output power levels after calibration of the cable loss over (a) different chip input power at the input frequencyf of 19.6 GHz, and (b) the frequency range of interest with the input power of 0.5 dBm.
TABLE I
DEVICEWIDTH ANDMEASUREDBIASCURRENT
even-order harmonic output currents from and are in phase as a common-mode response, the capacitive cross-cou-pling effectively rejects them all [6]. Table I lists the device sizes and the measured bias current.
The notch filter consists of , and . Connected in shunt to the signal path, it bypasses the fundamental spur with low input impedance at , and sustains the third-order har-monic injection current with high impedance at . Its input impedance is derived as
(2) which carries out a zero frequency at
562 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 20, NO. 10, OCTOBER 2010
Fig. 8. Calculated harmonic rejection ratios of the tripler. TABLE II
PERFORMANCE SUMMARY AND COMPARISON
and a pole frequency at
(4) As such, , and are selected to result in at and
at .
A two-stage differential output buffer is employed for the measurement purpose. Only one side of the buffer is shown in the dashed box in Fig. 1. For a minimum loading effect on the oscillator, a common-source stage with a small device size is adopted at the first stage. A source follower stage is used to drive 50 impendence at the second stage.
III. MEASUREMENTRESULTS
The tripler circuit is designed and fabricated in 0.13 m CMOS technology. The die micrograph is shown in Fig. 4, occupying an area of 985 866 m , including an on-chip balun placed at the input to provide a differential input signal to the harmonic generator. The measured input return loss of the entire chip is better than 10 dB from 18 to 22 GHz. The circuit is characterized single-ended at one output while the
other output is terminated into 50 load. The signal loss due to the cable setup is around 11.3 dB. The output signal spectrum is observed on a spectrum analyzer equipped with the option of an external harmonic down-converter, which conversion loss is calibrated automatically by the spectrum analyzer itself.
The measured free-running frequency of the oscillator is at 58.92 GHz, with an output power level of dBm without calibration of the cable loss. Fig. 5 shows the measured output spectrum under the injection locked condition with a chip input signal of 0.5 dBm at 19.6 GHz. The frequency locking range increases as the input power increases. As shown in Fig. 6, the locking range achieves 3.9 GHz at the input power of 0.5 dBm. The measured harmonic output power after calibration of the cable loss is shown in Fig. 7, over different input power levels and the frequency range of interest. It also demonstrates suc-cessful broadband suppression of the undesired fundamental and the second-order harmonic such that those output power levels appear to be flat across the entire band. The maximum conversion gain of dB occurs at the input frequency of 19.7 GHz. The output 3 dB bandwidth is about 2.18 GHz. Fig. 8 shows the calculated harmonic rejection ratios of two major har-monic outputs. The HRRs of the fundamental and the second-order with the input signal at 19.7 GHz are 31.3 and 45.8 dBc, respectively. The phase noise is measured with a signal source analyzer using an input signal at 19.65 GHz. The data shows an increase around 10 dB at the injection-locked output, in agree-ment with the theoretical value of 9.5 dB.
With the input power of 0.5 dBm, the core circuit and the output buffer under operation consume dc power of 9.96 and 16.1 mW, respectively, with 1.2 V supply voltage. The circuit performance of this tripler is summarized in Table II, together with those of other works for comparison. It shows that the har-monic rejection of the proposed tripler is superior to the others.
IV. CONCLUSION
Spur suppression is implemented and verified in a 60 GHz frequency tripler utilizing the injection locking approach. Not much mentioned in other literatures, the spurious noise issue is greatly alleviated in the proposed circuit without using any ex-ternal filtering. The circuit offers rejection better than 31 and 45 dB to the fundamental and the second-order harmonic spu-rious noise, respectively.
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