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超薄二氧化鉿閘極絕緣層之特性研究

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Fig. 1-3 LOP logic scaling-up of gate leakage current density limit and of  simulated gate leakage due to direct tunneling
Fig. 1-5 Important high-k regions to be optimized for 1 nm high-k transistors.  (International SEMATECH Confidential and Supplier Sensitive, 2002)
Fig. 2-2 Scaling limits of different ALCVD Hf-Based high-k Materials.
Figure 3-1 Fabrication flow chart of ultra thin HfO 2  MIS capacitor.
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