Tahui Wang,
Senior Member, IEEE, Lu-Ping Chiang, Nian-Kai Zous,
Charng-Feng Hsu, Li-Yuan Huang, and Tien-Sheng Chao
Abstract— The mechanisms and characteristics of hot car-rier stress-induced drain leakage current degradation in thin-oxide n-MOSFET’s are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero VVVgsgsgs such as drain-to-source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley–Read–Hall gen-eration current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is re-duced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 ˚A) n-MOSFET’s, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 ˚A) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation.
Index Terms— Drain leakage degradation, hot carrier, thin oxide.
I. INTRODUCTION
T
HE REDUCTION of drain leakage current at zero has been a major concern in CMOS device scaling. Gate-induced drain leakage (GIDL) current resulting from band-to-band tunneling has been recognized as one of the major drain leakage mechanisms in thin-oxide n-MOSFET’s [1]. The tunneling leakage current becomes more serious when negative word-line voltage is used in DRAM’s [2], [3]. Recently, hot carrier (HC) stress-induced device degradation has received much interest [4]–[8]. However, most of the studies were concentrated on device driving current and transconductance deterioration. The stress-induced drain leakage current degra-dation has not received as much attention. The HC effects onManuscript received September 25, 1998; revised March 1, 1999. This work was supported by the National Science Council, R.O.C., under Contract NSC87-2215-E009-060. The review of this paper was arranged by Editor M. Fukuma.
T. Wang, L.-P. Chiang, N.-K. Zous, C.-F. Hsu, and L.-Y. Huang are with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C.
T.-S. Chao is with the National Nano Devices Laboratory, Hsinchu, Taiwan, R.O.C.
Publisher Item Identifier S 0018-9383(99)06653-8.
drain leakage current are twofold [9], [10]; One is interface trap ( ) generation, and the other is fixed oxide charge ( ) creation; generation can introduce additional drain leakage mechanisms including Shockley–Read–Hall (SRH) thermal generation current, thermionic-field emission current, and se-quential tunneling current [9]. At reduced supply voltages, while band-to-band tunneling can be greatly alleviated, the -assisted leakage may become the dominant drain leakage mechanism in thin-oxide devices. The effect on drain leakage degradation is through the modification of the Si surface field. The build up of negative oxide charge in an n-MOSFET can shift the device flatband voltage and increase the Si surface field. As a result, band-to-band tunneling current and the -assisted tunneling current are enhanced.
In addition, experimental results showed that the -assisted leakage exhibits a temperature dependence [3], [11]. The thermal effect becomes increasingly important at a lower operating voltage when tunneling is relatively weak. In a certain bias range, the leakage current becomes much aggravated at an elevated temperature and may have an impact on DRAM refresh time. Furthermore, research showed that growth characteristic varies with gate oxide thickness [5]. In ultra-thin oxides, generation is almost negligible since trapped charge can easily escape via direct tunneling [7]. In this work, we intend to investigate various HC stress-induced drain leakage degradation mechanisms and to compare the degradation characteristics at different oxide thicknesses.
In measurement, the test devices are 0.35- m n-MOSFET’s with source/drain extension. The gate oxide thicknesses are 53, 40, and 30 ˚A, and the gate width is 100 m. The choice of gate length is arbitrary since the HC stress-induced leakage current flows from the drain to the substrate and is almost independent of gate length. A maximum substrate current stress at and V is applied in this work. Interface trap creation is monitored by using a charge pumping (CP) technique. Two-dimensional device simulation [12] is performed to obtain the electric field and carrier concentration distributions in the measured devices.
II. DRAIN LEAKAGE CURRENTMECHANISMS
The various drain leakage paths in an HC stressed n-MOSFET are illustrated in Fig. 1. The prestress drain leakage currents include band-to-band tunneling current ,
Fig. 1. Illustration of various drain leakage current paths in an HC stressed n-MOSFET’s. Full circles in the gate oxide represent negative oxide trapped charge and the crosses at the Si/SiO2surface are interface traps.
(a) (b)
(c) (d)
Fig. 2. Illustration of various interface trap-assisted carrier transition pro-cesses in the lateral direction.Ge andGhare electron and hole thermionic emission rates, andTeandThare electron and hole tunneling rates.ISRHis the Shockley–Read–Hall current,IT ATis charge sequential tunneling current, andIT F is thermionic-field emission current.
source subthreshold current , and junction leakage current (1) (2) where the parameters A and B are defined in [13]. denotes the Si surface field and other variables have their usual definitions. Drain junction leakage current is small here and can be ignored.
A. -Assisted Drain Leakage Mechanisms
The -assisted drain leakage mechanisms are illustrated in Fig. 2, where the carrier transition processes in the lateral direction are shown. and in the figure denote electron and hole thermionic emission rates, and and represent electron and hole tunneling rates, respectively. A complete -assisted leakage path is formed at the Si/SiO surface by hole emission from interface traps to the valence band and electron emission from the traps to the conduction band. Both electron and hole transitions can be carried out via either thermionic emission or tunneling. The carrier transition pro-cesses in Fig. 2(a) represent the SRH current ( ), where
(a) (b)
Fig. 3. Interface trap-assisted carrier transition processes in the vertical direction.
both electron and hole transitions are through thermionic emission. Fig. 2(b) is sequential tunneling current ( ). Fig. 2(c) and (d) are thermionic-field emission current ( ), i.e., one carrier transition through thermionic emission and the other through tunneling. Carrier transition processes in the vertical direction are shown in Fig. 3. Note that hole transition is through thermionic emission only in Fig. 3. Hole tunneling from the trap states to the valence band is not permissible in the vertical direction because of energy conservation in charge tunneling. Therefore, is a function of only the lateral field, while the tunneling processes and are dependent on the total field. The calculation of the charge thermionic and tunneling rates can be found in our previous publication [9]. The closed-form expressions for the -assisted leakage currents are written below
(3) (4) (5) where is the length of the HC stress region and denotes the Si bandgap. The total -assisted leakage current is the sum of these three components
(6) In addition, it can be shown that in (3) can be further reduced to an analytical expression [9]
(7) where the parameter is determined by the ratio of the surface fields in the vertical and the lateral directions. In modeling, the field-dependent parameters are electron and hole tunneling times and the temperature-dependent param-eters are the bandgap, thermal velocity, and intrinsic carrier concentration [14].
B. -Enhanced Drain Leakage Degradation
A change of the Si surface field resulting from oxide charge generation is , where is defined as the equivalent areal density at the Si/SiO surface. Assuming
(9) Two points should be mentioned: first, is linearly depen-dent on (7) but has an exponential dependence on . A small amount of can result in significant drain leakage current degradation. Second, since is affected only by (8), while is influenced by both and (9), we can characterize the and -induced degradations separately
by measuring and .
C. Drain Leakage Degradation Rates
It was reported that the growth rates of and follow a power law dependence on stress time [15], i.e.,
and (10)
Substituting (10) into (8) and (9), the degradation rates of and are obtained. In case that generation is dominant,
constant (11)
(12) On the other side, if generation is dominant
(13)
(14) III. RESULTS AND DISCUSSION
The measured prestress and poststress – characteristics in a 40- ˚A oxide n-MOSFET at K are shown in Fig. 4. The stress condition is V and V for 3000 s. generation is evidenced by the change of the subthreshold swing. creation is minimal in the stressed device because the prestress and poststress GIDL currents converge to each other at a large . The drain-induced barrier lowering effect [16] is insignificant in this device.
The dependence of prestress and poststress V drain leakage currents on supply voltage ( ) at two temperatures, K and K, are shown in Fig. 5. The interface trap annealing at K is insignificant. The stress and temperature-enhanced drain leakage current factor, defined as the ratio of the poststress drain leakage to the prestress K drain leakage, is shown in Fig. 6. The -induced drain leakage current enhancement is particularly pronounced around a supply voltage of 2.1 V. An enhancement factor of 18 at K is obtained. As temperature rises ( K),
Fig. 4. Prestress and poststressId–Vgscharacteristics in a 40- ˚A gate oxide n-MOSFET atT = 292 K. The stress condition is Vds= 4:5 and Vgs= 2:0 V for 3000 s.
Fig. 5. Measured prestress and poststress drain leakage currents atVgs= 0
V versus supply voltage (tox= 40 ˚A).
the enhancement factor is further increased up to 110. The temperature effect becomes more significant at a lower . For example, the enhancement factor at V is 5 at K and 80 at K. The poststress drain leakage currents are decomposed in Fig. 7 ( K) and Fig. 8 ( K). The solid lines are from measurement and the circles represent calculated result. In measurement, is monitored at the source, is obtained from the difference between the prestress and poststress drain leakage currents, and is assumed to be equal to its prestress result because of negligible generation in the 40- ˚A oxide device. In calculation, is 1.4 10 cm , and the length of the distribution is assumed to be 400 ˚A.
In Fig. 7, band-to-band tunneling current manifests itself as a dominant mechanism at a large supply voltage ( V). The drain leakage current degradation arising from creation is relatively unimportant in this range. By comparing Figs. 7 and 8, the at K (1.9 nA at V) is slightly above that at K (1.4 nA at V). The reason is that the bandgap reduces at a higher temperature, and thus the tunneling current
Fig. 6. The ratio of the poststress drain leakage current to the prestress drain leakage current atT = 292 K versus supply voltage.
Fig. 7. Various zeroVgsdrain leakage current components from measure-ment (solid lines) and calculation (full circles) (T = 292 K).
Fig. 8. Various zeroVgsdrain leakage current components from measure-ment (solid lines) and calculation (full circles) (T = 353 K).
increases. In Figs. 7 and 8, the -assisted leakage current shows a weaker field dependence than due to a smaller tunneling barrier from the traps to conduction band (electron tunneling) or to the valence band (hole tunneling).
Fig. 9. Calculation of various interface trap-assisted drain leakage currents
atT = 292 K.
Fig. 10. Calculation of various interface trap assisted drain leakage currents
atT = 353 K.
In other words, the in (7) is smaller than the parameter in (1). Consequently, as supply voltage scales down, drops more quickly and becomes dominant for V. When is further reduced ( V), the tunneling effect is unimportant and the drain leakage current enhancement results mainly from the SRH generation current. Thus, the effect is most significant at a medium and the enhancement factor in Fig. 6 peaks around 2.1 V.
Furthermore, we analyze the components of the -assisted leakage current in Fig. 9 ( K) and Fig. 10 ( K). In Fig. 9, is dictated by for
V, by for V V, and by for
V. In Fig. 10, the thermally related components and are more prominent. For example, the -dominant region extends from V at K to
V at K.
The oxide thickness dependence of drain leakage current degradation is investigated in Fig. 11. The drain leakage current degradation rates in two different oxide thickness (30 and 53 ˚A) devices are compared. Note that the oxide thickness 30 ˚A is already in the direct tunneling regime. The
Fig. 11. Comparison of the drain leakage current degradation in the 30- ˚A oxide and 53- ˚A oxide n-MOSFET’s measured atVgs= 0 and Vds= 2:5 V.
The stress bias isVgs = 2:0 and Vds= 4:5 V.
Fig. 12. Normalized drain leakage currents versus stress time in the 30- ˚A oxide and 53- ˚A oxide n-MOSFET’s measured atVgs = 0 and Vds = 2:5
V. The solid lines represent fitting results and the circles are measured data points.
dominant drain leakage current is from Fig. 9. Although the drain leakage current in the 53- ˚A oxide device is smaller initially, it shows a faster degradation rate when stress time is sufficiently long. A crossover of these two drain leakage currents is observed. To explore the reason for the drastic drain leakage degradation in the 53- ˚A oxide device, we replot the two leakage currents on a log–log scale in Fig. 12. For the purpose of comparison, the two currents are normalized to have the same starting value. The corresponding CP currents in the two devices are shown in Fig. 13. In Fig. 12, the in the 30- ˚A oxide device follows a power law degradation rate in the entire stress period. The power factor is about 0.4, which correlates with the stress time dependence of the CP current reasonably well and reflects the growth rate of . In contrast, the degradation in the 53- ˚A oxide device exhibits a distinctly different feature. A two-stage degradation process is noticed [10]. In the first stage ( s), is dominant and the degradation follows a power law dependence. In the second stage, becomes dominant and shows an accelerated degradation rate. The calculated results from (12) and (14)
Fig. 13. Charge pumping current versus stress time in the 30- ˚A oxide and 53- ˚A oxide n-MOSFET’s. The CP measurement frequency is 100 kHz.
Fig. 14. Normalized band-to-band tunneling currents in the 30- ˚A oxide and 53- ˚A oxide n-MOSFET’s measured atVgs= 03 and Vds= 1:5 V. are shown by the solid lines in Fig. 12. The extracted power factor is about 0.2, and the estimated density at s is about 1.6 10 q/cm . Note that the degradation rate is even faster than the growth rate in the second stage since has an exponential effect on . The exponential degradation of the drain leakage current due to creation may potentially impose a severe limit on device lifetime.
Since is only affected by , measurement of the drain leakage current at V and V, where is dominant, can be used to monitor oxide charge creation. The normalized ’s in the two devices are shown in Fig. 14. The ’s are nearly constant for s, which implies minimal creation. A slight decline in the ’s in this period can be explained by a small amount of net positive oxide charge (or interface charge) creation. For s, the in the 30- ˚A oxide device remains still constant. This result is consistent with the statement by Momose et al. [7] that creation is unlikely in ultra-thin oxides in the direct tunneling regime. The in the 53- ˚A oxide device, however, increases significantly in the second stage. The increase of the can be well fitted by using (13) (solid line) with .
IV. CONCLUSION
Various drain leakage current degradation mechanisms have been modeled and characterized. At scaled supply voltages, the -assisted leakage current becomes a dominant drain leakage mechanism in the current devices. An oxide thickness dependence of drain leakage degradation has been observed. In ultra-thin oxide (30 ˚A) devices, the HC stress-induced drain leakage degradation is mostly attributed to interface trap gen-eration, while in thicker oxide (53 ˚A) devices, the degradation is driven by both interface trap and oxide charge creation. By using a thinner gate oxide, oxide charge generation is negligible and the stress-induced drain leakage degradation can be much improved.
ACKNOWLEDGMENT
The authors would like to acknowledge National Nano De-vices Laboratory for fabricating the test deDe-vices. Special thanks are extended to Dr. Chimoon for many helpful discussions.
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Tahui Wang (M’86–SM’94) was born in Taoyuan,
Taiwan, R.O.C., on May 3, 1958. He received the B.S. degree from National Taiwan University, Taipei, in 1980, and the Ph.D. degree in electrical engineering from the University of Illinois, Urbana-Champaign, in 1985.
From 1985 to 1987, he was with Hewlett-Packard Laboratories, Palo Alto, CA, where he was engaged in the development of GaAs HEMT devices and cir-cuits. Since 1987, he has been with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, where he is currently a Professor. His research interests include hot carrier phenomena characterization and reliability physics in VLSI devices, RF CMOS devices, and high-speed devices.
Dr. Wang was granted the Best Teacher Award by the Ministry of Education, R.O.C., in 1991. He has served as technical committee member of many international conferences, among them IEDM and IRPS.
Lu-Ping Chiang received the B.S. degree from
Tatung Institute of Technology, Taipei, Taiwan, R.O.C., in 1994, and the M.S. degree in electronics engineering from the National Chiao-Tung Uni-versity (NCTU), Hsinchu, Taiwan, in 1996. He is currently pursuing the Ph.D. degree at NCTU.
His research interests include characterization and modeling of flash EEPROM reliability.
Nian-Kai Zous received the B.S. degree in
elec-tronics engineering from National Chiao-Tung Uni-versity (NCTU), Hsinchu, Taiwan, R.O.C., in 1996. He is currently pursuing the Ph.D. degree at NCTU. His research interests include thin oxide reliabil-ity and hot carrier effects in deep submicrometer MOSFET’s.
Charng-Feng Hsu received the B.S. degree in
1986 from the National Ocean University, Keelung, Taiwan, R.O.C., and the M.S. degree in electronics engineering from the National Chiao-Tung Uni-versity (NCTU), Hsinchu, Taiwan, in 1990. He is currently pursuing the Ph.D. degree at NCTU.
From 1990 to 1998, he was with the Department of Electrical Engineering at the Ming-Hsin Institute of Technology, Hsinchu, as an Instructor. His re-search interests include the reliability issues and hot carrier effects in deep submicrometer MOSFET’s and memory device design and modeling.
Li-Yuan Huang received the B.S. degree in
elec-tronics engineering in 1997 from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., where he is currently pursuing the M.S. degree.
His research interest is in hot carrier effects in deep submicrometer MOSFET reliability.
Tien-Sheng Chao was born in Penghu, Taiwan, in 1963. He received the
Ph.D. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. in 1992.
He jointed the National Nano Device Laboratories (NDL), Hsinchu, as an Associate Researcher in July 1992 and became a Researcher in 1996. He was engaged in developing the thin dielectrics preparations and cleaning processes. He is presently responsible for the deep submicrometer device integration at NDL.
