The Dependence of the Performance of Strained NMOSFETs on Channel Width

The Dependence of the Performance of Strained

NMOSFETs on Channel Width

Lingyen Yeh, Member, IEEE, Ming Han Liao, Student Member, IEEE, Chun Heng Chen, Jun Wu,

Joseph Ya-min Lee, Chee Wee Liu, Senior Member, IEEE, T. L. Lee, and M. S. Liang

Abstract—The dependence of the performance of strained

NMOSFETs on channel width was investigated. When the

chan-nel width was varied, the stress in the chanchan-nel varied

accord-ingly. This changed the electron effective mass and, consequently,

the ON-state current

I

. By shrinking the channel width of a

strained NMOSFET from 1 to 0.1

µm and by keeping the channel

length at 55 nm, the ON-state drain current per unit channel width

was enhanced by 22%. The gate leakage current was also affected

by the stress in the channel, which can be explained by the increase

in hole barrier height at the Si

/SiO

interface. Furthermore, when

the film stress was increased by 1 GPa, the gate leakage current

density

J

of a strained NMOSFET with a channel width of

0.1

µm and a length of 55 nm under a negative bias −3 V was

reduced by 63%.

Index Terms—Contact etch stop layer (CESL), high-stress

silicon nitride, MOSFET, strained silicon.

I. I

T

HE USE OF a contact etch stop layer (CESL) is one of

the key methods to boost the performance of

nanometer-scale MOSFETs [1]–[3]. The stress in the channel of a

CESL-strained MOSFET can be enhanced by increasing the CESL

film stress and the CESL thickness and by optimizing the device

structure [1], [2]. The stress in the channel is also observed

to depend on the layout of a MOS transistor [3]. However,

few studies have been carried out to increase the stress in the

channel by properly choosing the channel width. The optimal

channel width to reach an

I

gain for a CESL-strained

NMOS-FET with a channel length of 55 nm has already been reported

[4]. The stress in the channel is also found to affect the gate

leakage current density

J

. However, the dependence of

J

on

the channel width has not been fully investigated. This brief

examined the dependence of

I

and

J

on the channel width,

Manuscript received January 22, 2009; revised July 22, 2009. Current version published October 21, 2009. The review of this brief was arranged by Editor J. Woo.

L. Yeh is with the Institute of Electronics Engineering, National Tsing Hua University, Hsinchu City 300, Taiwan, and also with Taiwan Semicon-ductor Manufacturing Company, Hsinchu City 300, Taiwan (e-mail: lyyeh. jcsu@msa.hinet.net).

M. H. Liao, T. L. Lee, and M. S. Liang are with Taiwan Semiconductor Manufacturing Company, Hsinchu City 300, Taiwan.

C. H. Chen and J. Y. Lee are with the Institute of Electronics Engineering, National Tsing Hua University, Hsinchu City 300, Taiwan.

J. Wu is with Taiwan Semiconductor Manufacturing Company, Hsinchu City 300, Taiwan, and also with the Graduate Institute of Materials Science and Engineering, National Chiao Tung University, Hsinchu City 300, Taiwan.

C. W. Liu is with the Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan, and also with the National Nano Device Laboratories, Hsinchu City 300, Taiwan.

Digital Object Identifier 10.1109/TED.2009.2030542

Fig. 1. Calculated inverse of the electron effective mass plotted as a function ofSxxin the channel. VariousSyy/Sxxratios−0.28, 0.5, 1 (biaxial stress), and 1.5 are depicted.

and its scope has been extended to the channel width for

CESL-strained NMOSFETs with channel lengths ranging from 1

µm

to 55 nm.

II. E

In this brief, NMOSFETs were processed using shallow

trench isolation (STI), nitrided-SiO

gate dielectric, n+

poly-crystalline silicon gate, and tensile silicon nitride CESL [5].

The filling material of the STI was silicon oxide that was

deposited by a high-density-plasma chemical-vapor-deposition

(CVD) process. The STI process followed the conventional

STI process reported in [6]. The effective oxide thickness was

about 1.9 nm, which was measured on a large gate square and

operated at 1.1 V. The CESL was deposited by a CVD process.

The 3-D stress distribution with different device geometric

structures was simulated by a 3-D finite element mechanical

stress simulation program, ANSYS. In the simulation, the

elastic analysis was restricted to the effect of the nitride layer

on the channel [7]. The change in the effective mass under the

stress was calculated by the

k · p model [8], [9].

III. R

D

Fig. 1 shows the calculated inverse electron effective mass

m

e

as a function of the simulated

S

. Various

S

/S

ratios

of

−0.28, 0.5, 1 (biaxial stress), and 1.5 are depicted. S

and

S

represent the stresses in the channel, which are in parallel

and transverse to the direction of the current flow. The inverse

m

e

is observed to increase with an increase in

S

when the

Fig. 2. (a) CalculatedSyy/Sxxplotted as a function ofSxxwith various combinations of channel length and channel width. (b) Stress components plotted as a function of channel width for NMOSFETs withL = 55 nm.

value of

S

is smaller than about 1.5 GPa. Furthermore, the

film stress after annealing must be greater than 3 GPa to give

an

S

of 1.5 GPa in the simulation. It is unlikely that silicon

nitride would ever reach such a high tensile film stress [10].

Thus,

S

that is below approximately 1.5 GPa has been the

focus of this study. Moreover,

m

is observed to further reduce

with an increasing ratio of

S

/S

from

−0.28 to 1.5.

Fig. 2(a) shows the ways to reach a high

S

/S

(small

m

)

by optimizing the dimensions of the NMOSFETs. The

calcu-lated

S

/S

was plotted as a function of

S

with various

combinations of channel length

L and channel width W . For

example, consider the curve with

L = 55 nm in Fig. 2(a). It

can be observed that, when

W decreases from 10 to 0.6 µm,

S

/S

increases; however,

S

decreases with the reduction

in

W . When W decreases further from 0.6 µm to 75 nm,

S

/S

keeps increasing with the reduction in

W , but S

changes from a decreasing to an increasing value with the

reduction in

W . Fig. 2(b) (in our previous work, , Fig. 1(b)[4])

provides an explanation for this phenomenon. When

W is

greater than 0.6

µm, S

increases, whereas

S

decreases,

and, therefore,

S

/S

increases with a reduction in

W . Both

S

and

S

increase with a reduction in

W when W is lesser

than 0.6

µm. The rate of increase in S

with decreasing

W is

observed to be about eight times of that for

S

. As a result,

S

is found to dominate the width dependence of

S

/S

, and the

S

/S

ratio is observed to increase with a reduction in

W . In

Fig. 3. ExperimentalIon per unit width compared to the theoretical cal-culation is plotted as a function of channel width. (—) Theoretical I_on, Lphysical= 55 nm (quasi-ballistic model). (· · ·) Theoretical Ion,L_physical= 80 nm (quasi-ballistic model). (-. -) Theoretical I_on, L_physical= 0.5 µm (drift-diffusion model). (- - -) Theoretical Ion, L_physical= 1 µm (drift-diffusion model). (◦) Measured I_on,L_physical= 55 nm. () Measured I_on, Lphysical= 80 nm. () Measured Ion,L_physical= 0.5 µm. () Measured Ion, Lphysical= 1 µm. The value for the devices with W = 10 µm is

normalized as one. The inset in Fig. 3 shows Vt− Vt (W = 10 µm) as a function of channel width.(◦) L_physical= 55 nm. () L_physical= 80 nm. () Lphysical= 0.5 µm. () Lphysical= 1 µm.

addition,

S

is found to take up a minimum value when

W is

about 0.6

µm, which gives rise to the turnaround in the curve

with

L = 55 nm [Fig. 2(a)]. A similar analysis can be applied

to other

L values.

As shown in Fig. 2(a), to reduce

m

by a large

S

/S

ratio, the smallest

W should be used. Furthermore, S

and

S

became more tensile, and

S

became more compressive

with a decrease in

W , and this trend was preferred to increase

the electron mobility [2], [4]. Thus, the preferred

S

,

S

, and

S

stresses and

S

/S

ratio could be reached by adopting

the smallest

W value.

To prove the mechanism mentioned earlier, the measured

I

per unit width of the strained NMOSFETs with various

W and L values is presented in Fig. 3. By reducing the value

of

W from 1 to 0.1 µm, the I

per unit width was observed

to increase to about 1%, 2%, 7%, and 22% for

L of 1 µm,

0.5

µm, 80 nm, and 55 nm, respectively. Furthermore, the

magnitude of the increase in the

I

per unit width increased

with decreasing channel length mainly because of the smaller

separation distance between the center of the channel and the

sources of the applied stress with decreasing

L. Thus, the film

stress became more effective to affect the stress in the channel

and reduce the electron effective mass. Furthermore, the film

stress was also more effective in increasing

I

. The

stress-induced enhancement of the electron mobility was applied to

the theoretical calculation of NMOSFETs with an

L of 1 and

0.5

µm, based on the drift-diffusion model [11]. However,

ballistic transport was observed in nano-MOSFETs [12]. To

resolve this problem, a quasi-ballistic transport model was used

for nano-NMOSFETs with an

L of 80 and 55 nm (Fig. 3). The

details of the calculation using quasi-ballistic transport were

reported in [8] and [12]–[14].

To further validate the stress mechanism discussed earlier,

J

under the stress described in Fig. 2(a) was also studied.

Fig. 4. Ig of the highly and lightly strained NMOS devices is plotted as a function of channel width. The CESL stress for the highly strained devices is 1 GPa higher than that for the lightly strained ones.V_substrate= 0 V in this measurement.

accumulation. Both the highly and lightly strained NMOSFETs

were measured, and the CESL stress for the highly strained

devices was 1 GPa higher than the lightly strained ones. The

J

of the highly strained NMOSFET with a

W/L of 0.1 µm/55 nm

was reduced by 63% compared that of the lightly strained one

under a negative bias of

−3 V. Furthermore, the J

of the lightly

strained devices was reduced by about 17%, 33%, and 39% by

decreasing

W from 1 to 0.1 µm under V

biases of

−1, −2,

and

−3 V, respectively, and that of the highly strained devices

by about 40%, 48%, and 56%, respectively. Thus,

J

could be

reduced by decreasing

W from 1 to 0.1 µm, and this effect was

more obvious for the highly strained devices. Generally, the

J

of NMOSFETs with a smaller

W was higher than those with a

higher

W because J

near the STI edge was higher [15]–[17].

Hence, the

J

reduction in Fig. 4 may not have been caused by

the STI process. Furthermore, the energy bands of the strained

silicon and carrier distribution were altered by stress [2]. The

influence of stress on the electron barrier height was relatively

insignificant because the work functions of conductors and

heavily doped polycrystalline silicon changed relatively little

by stress [18]. Thus, the effect was mainly on holes. The

calculation of the splitting of the sixfold degenerate valence

band was reported in [19]. It involved linear splitting and

spin-orbit splitting, expressed in terms of deformation potentials.

The spin-orbit splitting for silicon was very small (

∼0.04 eV),

and, hence, this term was neglected in the calculation. The

required parameters to calculate the deformation potential can

be obtained from [19]–[21]. The calculated result is shown in

Fig. 5. A higher

S

/S

value was observed to cause a greater

shift of the valence band edge. Thus, the barrier height for

light holes increased, and the probability of the hole injecting

into the gate was reduced, which explains the reduction in

J

in Fig. 4. This

J

reduction was found to be more effective

with decreasing channel length. This can be explained by the

fact that the separation distance between the center of the

channel and the sources of the applied stress became closer with

decreasing channel length. As a result, for an NMOSFET with

smaller channel length, the CESL film stress may become more

effective to affect the stress in the channel and to increase the

barrier height for light holes. Thus, the CESL film stress may

be more effective in reducing

J

.

Fig. 5. Calculated valence band splitting of light holes (V1), heavy holes (V2), and split-off holes (V3) are plotted as a function of stressSxx. Various Syy/Sxxratios from−0.28 to 1.5 are depicted.

IV. C

Thus, in this study, the dependence of the performance

of silicon-nitride-strained NMOSFETs on channel width was

investigated. When the value of

W was varied, the stress in

the channel varied accordingly. This changed

m

and,

conse-quently,

I

. By reducing the value of

W , S

and

S

became

more tensile,

S

became more compressive, and the

S

/S

ratio became higher. All these changes aided in the reduction

in

m

and increased the value of

I

. By decreasing the value

of

W from 1 to 0.1 µm, the I

per unit width was observed to

increase by about 1%, 2%, 7%, and 22% for an

L of 1 µm,

0.5

µm, 80 nm, and 55 nm, respectively. The stress in the

channel also reduced the value of

J

. This was explained by

an increase in the barrier height for light holes. When the film

stress was increased by 1 GPa, the

J

of an NMOSFET with a

W/L of 0.1 µm/55 nm was reduced by 63% under a negative

bias of

−3 V.

R

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Lingyen Yeh (M’04) received the M.S. degree in

materials science and engineering from National Tsing Hua University, Hsinchu City, Taiwan, in 1994. Since 1994, he has been worked in the semi-conductor industry in Taiwan. From 1994 to 1995, he was with the R&D, Holtek Semiconductor In-corporation. From 1995 to 2000, he was with the R&D, Winbond Electronics Corporation, and its sub-sidiary company Worldwide Semiconductor Manu-facturing Company. Since 2000, he has been with the R&D, Taiwan Semiconductor Manufacturing Com-pany, Hsinchu City. He is currently with the Institute of Electronics Engi-neering, National Tsing Hua University, Hsinchu City. He has done research work in CMOS devices, including shallow trench isolation, strained silicon, ultrashallow junction, thin dielectric film, and CMOS process integration. He has authored and coauthored more than ten papers and received more than ten U.S. patents.

Ming Han Liao (S’07) received the B.S. degree in

mechanical engineering and the Ph.D. degree in elec-tric engineering from National Taiwan University, Taipei, Taiwan, in 2003 and 2007, respectively.

Since 2008, he has been with the R&D, Taiwan Semiconductor Manufacturing Company, Hsinchu City, Taiwan, where he is involved in strained Si technology and ultrashallow junction develop-ment. He has authored or coauthored more than 30 publications/conference proceeding papers/ presentations.

Dr. Liao was the recipient of the Zhuo Zhang-Zong Scholarship Award in 2005 for his outstanding research work.

Chun Heng Chen was born in Taipei, Taiwan, in

1982. He received the B.S. degree in electrical en-gineering from National Chung Hsing University, Taichung, Taiwan, in 2005 and the M.S. degree in electronics engineering from National Tsing Hua University, Hsinchu City, Taiwan, in 2007, working on the electrical characterization and reliability of high-k dielectrics, where he is currently working toward the Ph.D. degree in silicon solar cells.

Jun Wu received the B.S. and M.S. degrees in

mate-rials sciences and engineering in National Tsing Hua University, Hsinchu City, Taiwan, in 1993 and 1997, respectively.

He is currently with the Graduate Institute of Materials Science and Engineering, National Chiao Tung University, Hsinchu City. He is currently with the R&D, Taiwan Semiconductor Manufacturing Company, Hsinchu City, where his work involves thin-film processing and strained silicon technol-ogy. His research interests include semiconductor processing.

Joseph Ya-min Lee received the B.S. degree from

the Department of Physics, National Taiwan Uni-versity, Taipei, Taiwan, in 1965 and the Ph.D. de-gree from the Department of Physics, University of Maryland, College Park, in 1972. His Ph.D. thesis work was done in the area of experimental solid-state physics.

From 1972 to 1975, he was an Associate Professor with the Department of Physics and the Department of Materials Science, National Tsing Hua Univer-sity, Hsinchu City, Taiwan. From 1976 to 1987, he worked in the U.S. semiconductor industry. From 1977 to 1981, he was with Carlsbad Research Center, Hughes Aircraft Company, Carlsbad, CA, and, from 1981 to1987, with Hughes Research Laboratories, Malibu, CA. From 1987 to 1989, he was a Full Professor with the Department of Electrical Engineering and Applied Physics, Case Western Reserve University, Cleveland, OH. Since 1989, he has been a Full Professor with the Department of Electrical Engineer-ing, National Tsing Hua University. He has done research work in experimental solid-state physics, semiconductor photodetectors, CMOS and CMOS/SOS devices, GaAs/AlGaAs real space transfer devices, high dielectric constant, and ferroelectric thin films for VLSI memory devices. He has published more than 115 scientific journal papers and authored seven books.

and M.S. degrees in electrical engineering from Na-tional Taiwan University (NTU), Taipei, Taiwan, in 1985 and 1987, respectively, and the Ph.D. degree in electrical engineering from Princeton University, Princeton, NJ, in 1994.

He is currently a Professor with the Department of Electrical Engineering, NTU, where he is also with the Graduate Institute of Electronics Engineering. He is also with the National Nano Device Laboratories, Hsinchu City, Taiwan. His current research interests include strained-Si/Ge FETs, SiGe photonics, Ge/Si on anything, high-k, metal gate, and bulk/thin-film solar cells. He invented the first MOS tunneling LEDs