Design and implementation of an all-digital QPSK direct-sequence spread-spectrum transceiver IC

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DESIGN AND IMPLEMENTATION OF

AN ALL-DIGITAL QPSK DIRECT-

SEQUENCE SPREAD-SPECTRUM TRANSCEIVER IC

Jen-Shi Wu, Ming-Luen Liu, Hsi-Pin Ma, and Tzi-Dar Chiueh

Room 5 1 1, Department

of

Electrical Engineering

National Taiwan University

Taipei, Taiwan 10617,

R.O.C.

E-Mail:

Jenshi@analog.ee.ntu.edu.tw

Abstract

In this paper, an all-digital differentially encoded quater- nary phase shift keying (DEQPSK) direct sequence spread- spectrum (DSSS) transceiver is proposed. It consists of &yo

parts: a baseband/IF spread-spectrum transmitter and a coher- ent intermediate frequency (IF) receiver. The center frequency of this IF receiver is llMHz and the sampling rate is 44 Msampleslsecond. Modulatioddemodulation, carrier recovery, PN code acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design have been done before layout implementation. Fur- thermore, we added testing circuits in this chip and thus each fimctional block is easily tested. The chip was fabricated through TSMC 0 . 8 ~ n-well CMOS SPDM technology. The maximum operational clock rate is measured at over 90MHz (5V, over 4Mbps), and the minimum supply voltage for 2Mbps (44MHz) rated speed is 2.6V.

I. Introduction

Wireless communication becomes an obvious trend in per- sonal communication system in recent years. It also encour- ages extensive research in communication techniques and VLSI technology in order to implement the underlying radio components, such as increasing the utilization of channel bandwidth and the high demand in capacity for many applica- tions, improving the technology to obtain a small size, low power dissipation, high speed processor, and so on. Unlike wired transmission, there are many factors that affect the quality of wireless communication, such as multipath fading and co-channel interference. All of them will degrade the communication quality and reliability.

Spread-spectrum is a technique that can solve these non- ideal problems, besides it can increase the bandwidth utiliza- tion and the system capacity. The known advantages of spread- spectrum are as follows: (a) anti-jamming, (b) interference rejection, (c) multipath protection, (d) low probability of intercept, and (e) multiple access. Spread-spectrum systems can be classified by their modulation methods. The most common modulation techniques employed are: direct sequence, frequency hopping, time hopping, and so on.

Today, a trend related to the spread-spectrum techniques is

based on the commercial applications in wireless local area

network (WLAN) and personal communication network (PCN). All of these products have one key component, that is, a spread-spectrum transceiver. Its speed and reliability will directly affect the overall performance. Consequently, in- creasing demands on transmission rate, communication quality, and security make a high speed and high performance spread- spectrum transceiver necessary.

In this paper, a transceiver for direct sequence spread- spectrum (DSSS) and differentially encoded quaternary phase shift keying (DEQPSK) modulation scheme is presented. This chip includes an IF transmitter (DSSS

+

DEQPSK), a direct digital fkequency synthesizer, a Costas loop demodulator, and a high speed digital matched filter. It has the following prop- erties:

0 Complete 0.8pm CMOS digital direct sequence spread- spectrum transceiver.

0 Ideal for wireless local area networks (WLANs) at 2Mbps, operation up to 4Mbps possible.

Operates at 1 1 Mchips/sec. (44 MHz clock rate) in

transmit and receive modes at a supply voltage of 2.6V. 0 Programmable loop filter in order to meet different re- quirements or environments.

0 High performance digital matched filter results in a very low acquisition overhead.

0 Full duplex operation.

0 Input of the receiver can be either real or complex.

11. System Architecture

The proposed architecture consists of a baseband/IF trans- mitter and a coherent IF receiver. The transmitter includes five parts: a serial-to-parallel converter, a differential encoder, two spreaders, a sinelcosine waveform generator, and a QPSK modulator, as shown in Fig. 1. In our architecture, the spread- ing code is a barker code with a length of 1 1 chips, thus the processing gain is about 10.4 dB.

The receiver, as shown in Fig. 2, consists of a complex multiplier, two integrate-and-dump filters, a differential decoder, a parallel-to-serial converter, a numerically con- trolled oscillator (NCO), a Costas estimation loop for carrier recovery, and a matched filter for PN code acquisition. For the flexibility of our system, we use a complex multiplier as the down-converter that can process either real or complex signals.

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The overall function of DSSS DEQPSK demodulation is to down-convert the input signal from IF to baseband using the complex multiplier, compute the summation of all the samples within one symbol time using integrate-and-dump filters, decode the signal dumped out using differential decoder, and finally convert the outputs of the I and Q channels into a single bit stream. However, error probability will increase if the receiver does not have correct carrier recovery because there will be interference between the I and Q channels when the phase error of the sinelcosine waves generated ftom the NCO becomes large. In our design, we use a Costas estimation loop to perform the carrier recovery. There exists a frst order loop filter in the carrier recovery loop, and it has two programmable parameters to tune the bandwidth or the damping ratio of the loop. It can be shown that the phase error will converge to O",

90°, 180', or 270' in QPSK demodulation when we use Costas

estimation loop to synchronize the carrier contained in the input signal. A differential coder is then necessary for solving the phase ambiguity problem. Furthermore, in a spread spectrum system, we use the low correlation property of the sidelobe to reject noise and delayed versions of the signal. If the code within the receiver does not synchronize with the input signal, it will cause the input signal be spread out and no correct output generated. So an acquisition loop for code synchronization is mandatory. In the PN code acquisition loop, a digital matched filter was adopted to locate the position where the maximum correlation occurs and a pipeline archi- tecture allows it to complete all operations in one symbol time. From the position computed by the matched filter, we may align the PN code and the input signal on the fly, thus reducing the bit error rate.

111. Simulation Result

Before circuit design, we used the word-length optimiza- tion method as mentioned in [8] to reduce the complexity of additional hardware required for coherent demodulation. Thus the word-lengths of several important signals in this trans- ceiver were reduced without degrading the system perform- ance and a smaller chip area was obtained. In our design, the

A/D quantization level adopted is 6 bits; the sine/cosine

waves' resolution is 6 bits; the Costas estimation loop input word-length is 12 bits; and the view port size of the digital matched filter is 4 bits.

Overall gate-level simulation results of our receiver are shown in Fig. 3 and Fig. 4. At the beginning of the simulation, our receiver is initialized with a phase error and a nonsynchro- nized PN code, hence the outputs of integrate-and-dump filters become small since the input signal is not synchronized. In 5ps, the matched filter locates the instant with the maximum correlation as shown inside the dash-lined circle in Fig. 3.

Furthermore, one can find that the carrier is not synchronized in the first lops, so there is some small-scale fluctuation at the

IV. Layout Design and Testing Result

This transceiver was fabricated through the TSMC 0.8pm n-well CMOS technology. The die size is 4800x4800 pm2 and its microphotograph is shown in Fig. 5. To prevent the clock skew problem, we laid out the clock buffers at the center of the chip and routed the clock signal along the opposite direction of data signals. In view of testing, we added a test bus across the whole chip vertically, making it easy to observe and control several significant nodes in the chip.

We divided our testing strategy into two parts: (a) func- tional test and (b) performance test. For functional testing, we implemented a test board connected to a PC and used a program we developed to verify the functionality of the chip. In addition, we used this test board to do some other measure- ments, such as BER and frequency-error tolerance. To simu- late the channel effects, we wrote a pseudo transmitter and a pseudo fading channel to generate the contaminated input signal at the receiver. The algorithm we chose is Monte Carlo method with lo6 input bits. Fig. 6 and Fig. 7 show the meas- ured results of BER under AWGN and frequency error, respectively.

In addition to functional testing, we used an IMS tester to verify AC and DC performance of our chip. We measured the supply current and computed power dissipation. Fig. 8 shows maximum speed of the chip at different supply voltages. Fig. 9 illustrates power consumption of the chip running at maximum speed for different supply voltages. From these two figures, we can see that the maximum operating speed is 93 MHz, 65 MHz, 44 MHz at 5V, 3.3V, 2.6V supply voltage, respectively. At these three speeds, the power consumption of the chip is 850 mW, 234 mW, and 92 mW, respectively. Our chip outper- forms all previous spread-spectrum transceiver chips in terms of speed and power dissipation (see Table 1).

V. Conclusion

In this paper, an architecture for DSSS DEQPSK base- band/IF transceiver is presented. This architecture is suitable for all-digital implementation. We have integrated the DSSS DEQPSK modulatorldemodulator, the Costas carrier recovery loop, the PN sequence acquisition loop using a full digital matched filter in a single chip. This approach greatly reduces communication time between modules and increases system perfonnance. The complexity of the hardware required at IF demodulator was minimized through word-length optimization and the functionality was verified through functional and gate- level simulations. This transceiver was fabricated through TSMC 0.8pm n-well CMOS SPDM technology. The fabri- cated chip was tested and proven to be functionally correct. Furthermore, the chip can work at a speed of 4Mbps at 5V supply voltage. For low power applications, this chip can be slowed down to 2Mbps (compatible to IEEE 802.1 l), when it

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Selected Area Commun., NO.l, pp.44-58, Jan. 1992. r - - - _ _ _ _ _ _ _ _ _ _ _ _ _

I

DSSS DEQPSK Transmitter I I I I I I I I I I I I I I I I I I I I I I

. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - - _ - _ .

I

Fig.1 : Block diagram of the proposed DSSS DEQPSK transmitter.

Vol. 11, N0.7, pp.1096-1107, Sep. 1993.

C. Chien, et al., “A single-chip 12.7 Mchipsh digital IF BPSK direct sequence spread-spectrum transceiver in 1.2 pm CMOS,” IEEE .lSolid State Circuits, VOL.29, N0.12, pp.1614-1623, Dec. 1994.

[ 101 ASIC Custom Products Group. Digital, Fast Acquisition, Spread Spectrum Burst Processor STEL-2000A

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Pre- liminary Product Information. Stanford Telecommunica- tion, Inc., Santa Clara, 1994.

w

[I 11 S. Y. S h y , “Design and analysis of an all-digital spread spectrum receiver architecture,” Master Thesis, Depart- ment of Electrical Engineering, National Taiwan Univer-

(X) Input quantlzahon level (B) SindCosine wave resolution (C) Input quantuatfon level of matchedfilter

(D) Word length dumped to phase detector sity, Jun. 1994.

Fig. 2: Block diagram of the proposed DSSS DEQPSK receiver.

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Fig. 4: Convergence curve of the phase error in the Costas estimation loop.

Fig. 5: DSSS DEQPSK transceiver die photo.

Bit error rate measurement 10- I 2 j 10" a lo-;O 11 12 13 14 15 16 17 18 19 20 EWNO (dB)

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Frequency ermr VS BER TABLE I

Comparison with other DSSS transceivers

e n 10-5

t

i

10";

'

5

Ib 1'5 20 25 do 35 4'0 5: 50

'

Frequency error (kM)

Fig. 7: Measured bit error rate for different frequency errors.

m i m u m Clock speed vs. SUDDIV Voltage

100 90 N 80 s 70 60

-

B

g

50 fn 40

2

30

9

20 IO " 5 4.8 4.6 4.4 4 2 4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1

Supply Voltage (Volt)

Fig. 8: Maxi" clock rate vs. supply voltage.

Supply Voltage (Volt)

CYChip STEL-2000 PA-100 MSM SSRX Proposed IC Chip Rate 1 Mcps 10 Mcps 32 Mcps 1.228 Mcps 12.7 M C ~ S 2211 1 Mcps Porcessing l 2 d B a t 18dBat 4 8 d B a t Z l d B a t 2 1 d B a t 10.4dBat Gain 16 kbps 160 kbps 0.5 kbps 9.6 kbps at 100 kbps 412 M b p s External

c~~~~~~~~~ NONE NONE NCO NONE NONE NONE

Power Efficiency 9.2 (5V, 88MHz)

(mWiMsis) 37.5 44 NIA 23.8 "" 2.1 (2.6V, 44MHz) Complexity 60000trans. 180000 NIA 450000 51000 56000 Technology 0.7m 1 um 1 um 0.8 um 1.2 0.8 ~m

gatearray CMOS gatearray CMOS CMOS CMOS

Fig. 9: Power consumption at various different supply volt-

數據

Fig.  2:  Block  diagram  of  the  proposed  DSSS  DEQPSK  receiver.
Fig. 2: Block diagram of the proposed DSSS DEQPSK receiver. p.3
Fig.  4:  Convergence curve  of  the  phase  error  in  the  Costas  estimation loop.
Fig. 4: Convergence curve of the phase error in the Costas estimation loop. p.4
Fig. 6: Measured bit error rate.
Fig. 6: Measured bit error rate. p.4
Fig. 5: DSSS DEQPSK transceiver die photo.
Fig. 5: DSSS DEQPSK transceiver die photo. p.4
Fig. 7: Measured bit error rate for different frequency errors.
Fig. 7: Measured bit error rate for different frequency errors. p.5
Fig.  9:  Power  consumption at  various  different  supply  volt-  ages.
Fig. 9: Power consumption at various different supply volt- ages. p.5
Fig. 8: Maxi"  clock rate vs. supply voltage.
Fig. 8: Maxi" clock rate vs. supply voltage. p.5

參考文獻