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Wideband Matched CMOS LNA Design Using R-L-C Loading Network

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Wideband Matched CMOS LNA Design Using R-L-C

Loading Network

Hui-I Wu&Qi-Yuan Horng&Robert Hu& Christina F. Jou

Received: 20 July 2009 / Accepted: 1 June 2010 / Published online: 22 June 2010

# Springer Science+Business Media, LLC 2010

Abstract This paper proposes a new methodology for designing and analyzing wideband matched CMOS LNA with R-L-C loading network, where validity of this new approach is supported by the agreement between the simulated input impedance of the LNA and its calculated counterpart. To demonstrate its feasibility, two wideband matched LNA’s are designed using TSMC 0.18-μm RF-CMOS process. One is for 3–8 GHz application and the second one targets at 8–25 GHz frequency range. The measured results of both circuits will then be presented.

Keywords Wideband . Input matching . Low noise amplifier . LNA

1 Introduction

Wide-band low-noise amplifiers (LNA’s) have been a critical component for both scientific community and the communication industry, such as radio astronomy receivers for the former and ultra-wideband (UWB) technologies for the latter [1–3]. Among the different circuit design methodologies proposed for wideband amplifiers, the distributed one is probably the most straightforward in realizing broad bandwidth [4,5]. However, it tends to consume a lot of power while providing only modest gain. An amplifier using common-gate transistor as input stage can indeed have wideband matched impedance; nonetheless, the resulting circuit will have poor power gain and large noise figure [6]. Adding a delicate L-C circuit in front of the amplifier can improve its input matching over a wide bandwidth, but at the cost of additional noise generated by these passive components and, especially in the case of silicon, this deterioration is pronounced [7–9]. Recently, it becomes popular DOI 10.1007/s10762-010-9664-6

H.-I. Wu (*)

:

Q.-Y. Horng

:

C. F. Jou

Department of Communication Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan 300, Republic of China

e-mail: huiiwuhuiiwu@gmail.com R. Hu

Department of Electronics Engineering, National Chiao Tung University, 1001 University Road, Hsinchu, Taiwan 300, Republic of China

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applying current re-use method in designing wideband CMOS amplifiers; however, the stacking of one n-type and one p-type transistors requires a large bias voltage [10,11].

In the case of high mobility transistor (HEMT), it has already been demonstrated that through the intrinsic gate-drain capacitor Cgd, the transistor’s output R-C loading can alter

its input impedance to the intended value over a wide bandwidth [12]. In spite of that, implementation of this large loading equivalent resistance is not that easy in the CMOS circuit. Thus, the input matching mechanism for wideband matched COMS LNA needs to be re-examined and modified if necessary, and that prompts the research described in this paper.

In the following section, after a brief review of the 0.18-μm RF-CMOS transistor’s small-signal modeling, we propose what should constitute the first-stage transistor’s loading: Ld, Rd, and Cd, as shown in Fig.1, where Ldis an explicit element, and both Rdand

Cdcan be from the equivalent input circuit of the following-stage. Physically, the external

source inductor Ls is critical in determining the low-frequency input matching, and the

loading Ldstarts playing a role as frequency increases. In both cases, Cdis used for setting

Re[Zin], and proper choice of Rdhelps lowering S11at high frequency. If the high frequency

range means infinite, then Ldcan indeed be omitted; otherwise, the importance of this Ld

cannot be overlooked for finite-bandwidth wideband LNA, as this Ldcould improve the

input matching at the intended high frequency range. Without inserting any complicated passive (and lossy) circuit in front of the first-stage transistor, superior noise performance is expected for this type of amplifier.

A 3–8 GHz LNA is therefore fabricated using TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-μm RF-CMOS process. To explore the high frequency performance of this commercial process, a second LNA targeting the 8–25 GHz frequency range is then designed. Measured results of both amplifiers will be presented too.

2 Analysis of wideband LNA design

To facilitate the circuit analysis, S-parameters of a TSMC 0.18-μm RF-CMOS transistor need to be numerically fitted to find its equivalent small-signal model, as shown in Fig.2, where the substrate effect due to Csuband Rsubhas been included. For this 216-μm 27-finger n-type

transistor biased at Vgs=0.65 Volt and Id=7 mA, our model is valid up to 20 GHz at least, and

Fig. 1 The simulated input reflection coefficient Sinof the

proposed transistor circuit with Ld=0 and 0.6nH, respectively,

while Cd=0.13pF, Rd=25Ω,

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the parameter values are tabulated in Table 1. Though S-parameter discrepancies can be observed with the omission of Rg, Cds, Rsub, and Csub, they are relatively minor; thus, to

retain the physical meaning while simplifying the mathematical derivation, these four parameters are removed from that used in the following circuit analysis.

Mathematically, the input impedance Zin, as indicated in Fig.3, can be expressed as

Zin¼ Yaþ

1 Zb

 1

ð1Þ where Yαis the admittance looking into the Cgdbranch, and Zβis the impedance looking

into the Cgsbranch. Both Yαand Zβcan be derived as

Ya¼ jwC1 gd þ 1 jwCd þ Rdþ jwLd  1 þ 1 jwGmRdsCgd þ 1 Gm þ jwLs    þ 1 Cd GmCgdþ Cgd=jwLsCd  þ 1 1 jwGmRdCgdþ Ls RdCgd   þ 1 Ls jwCgdLd   1 w2L dCgdGm  !13 5 1 ð2Þ and Zb¼jwC1 gsþ GmLs Cgs þ jwLs ð3Þ

The corresponding equivalent circuit can be arranged as that of Fig.4, where Yαis the

dominant branch and Zβoffers some modification [12]. Again, it is the Cdthat determines

Table 1 Parameters in the small-signal model of the 216-micron 27-finger tsmc n-type transistor. Vgs=0.65 Volt, Id=7 mA

parameter value parameter value

Rg 7Ω Csub 0.3pF

Rds 452Ω Cds 0.063pF

Rsub 180Ω Cgd 0.08pF

Gm 64mS Cgs 0.2pF

Fig. 2 a Small-signal model of a TSMC 0.18-μm RF-CMOS tran-sistor biased at saturation region. b Simulated S-parameters from both the foundry provided design kit (solid lines) and our small-signal model (dashed lines).

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the matched Re[Zin] (= Cd/GmCgd ), as discussed in detail in [12]. With appropriate

component values, the shape of the input reflection coefficient Sin resembles a hook, as

shown in Fig. 5. The solid curve is the simulated result with Cd=0.13pF, Rd=25Ω, Ld=

0.6nH, and Ls=0.3nH; the overlapping dashed curve is the calculated counterpart using (1).

On the Sintrajectory, there are two marked frequency points where the corresponding input

impedance is purely real and close to 50Ω, and thus are good indices for this circuit’s (slightly larger) available frequency range. By setting Im[Yα] to zero, both fLand fHcan be

determined as fL¼ 1 2p ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiLsðCgdþ CdÞGmRds p ð4Þ and fH ¼ 1 2p ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiðLsþ LdÞCd p ð5Þ

The calculated fLand fHare 4.09 GHz and 13.24 GHz in this case, and are very close to

the simulated 5 GHz and 12.8 GHz, respectively. Apparently, with Cdused in determining

Re[Zin], fLcan now be set by Ls while fHcould be manipulated by Ld. Fig. 6shows the

simulated input reflection coefficient with different Ls, where curves 1–3 have Ls=0.3, 0.4,

and 0.5nH, and all have their Cd=0.13pF, Rd=25Ω, and Ld=0.6nH. Fig. 7illustrates the

impact of Ldon Sin, where curves 1–3 are with Ld=0.3, 0.6, and 0.9nH, and all have their

Cd=0.13pF, Rd=25Ω, and Ls=0.3nH. Figure8 shows the simulated Sinwith different Rd,

Fig. 3 The proposed transistor circuit used in the wideband analysis. in S gs C gd d mRC G gd m d C G C gd C d C β Z Yα m G 1 d R Ld m gd dC G L 2 1 ω − s L gs s m C L G gd ds mR C G s L gd d s C C L gd d s C R L s d gd L L C Fig. 4 Equivalent input

schema-tic of the proposed transistor circuit. Yαis the admittance

looking into Cgdbranch, Zβis the

impedance looking into Cgs

branch, and Sinis the overall

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where curves 1–3 have Rd=25, 45, and 65Ω, and all have their Cd=0.13pF, Ls=0.3nH, and

Ld=0.6nH. Intuitive understanding of this matching mechanism can now be best described

as follow:

(a) f < fL: As series RdLdCdtends to be open-circuit at very low frequency and the effect

of Lsis very small in this frequency range, the transistor’s loading is now dominated

by channel resistance Rds (= 452Ω). The resulting Miller capacitance GmRdsCgd

(= 2.31pF) puts the location of Sin in the capacitive region of the Smith chart. As

frequency increases, the real part of input impedance will start to be affected by the loading Cd, as Re[Zin] = Cd/GmCgd. The Sintrajectory can be determined by Cdand

moves along the constant resistance circle in the capacitive region [12].

(b) fL≤ f < fH: As frequency continues to increase, the inductive voltage induced by Lsat

the input is becoming more obvious, thus the inductive components of Zin(originating

from Ls) will resonate out the aforementioned Miller capacitance GmRdsCgd. On the

Smith chart, Sin will now pass-by the zero point and enter the inductive region;

therefore, it is apparently that fLcan be set by Ls. Since the loading resistor Rd(= 25Ω)

can also generate a small Miller capacitance GmRdCgd(= 0.125pF), a further bending

of the still-inductive Sinon the Smith chart can be observed in this frequency range.

Fig. 5 Calculated and simulated input reflection coefficient of the proposed transistor circuit. a The solid curve on the Smith chart is the simulated result while the dashed curve is its calculated counterpart. Here fL

and fHare the resonant low- and high-frequency points. b The same results expressed in dB vs. frequency.

Fig. 6 Simulated input reflection coefficient of the wideband transistor circuit with different values of Ls. a

On the Smith chart, curves 1–3 correspond to Ls=0.3, 0.4, and 0.5, respectively, while Cd=0.13pF, Rd=25Ω,

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(c) f≥ fH: When the inductor Ld begins to resonate out Cd, the loading circuit can be

approximated as Rdat the resonance frequency; therefore, Zinis predominated by the

corresponding Miller capacitance GmRdCgd, which means Sin on the Smith chart can

be easily dragged into the capacitive region. A complete loop around the zero point is now constructed and we know that fHcan be changed by Ld. If the high frequency

range means infinite, this Ldcan indeed be omitted; otherwise, the importance of this

Ld cannot be ignored in the case of finite-bandwidth wideband LNA. Thus far, the

roles played by Cd, Ls,Ld, and Rd in achieving wideband input matching are well

explained and can be easily understood.

3 Wideband LNA design

With the wideband matching mechanism fully analyzed, two CMOS LNA’s, one covers the more common 3–8 GHz as an initial verification and the other the more challenging 8–25 GHz for exploring this type of circuits’ potential and limitation, are designed and fabricated using TSMC 0.18-μm RF-CMOS process. Both the S-parameters and noise Fig. 7 Simulated input reflection coefficient of the wideband transistor circuit with different values of Ld. a

On the Smith chart, curves 1–3 correspond to Ld=0.3, 0.6, and 0.9nH, respectively, while Cd=0.13pF, Rd=

25Ω, and Ls=0.3nH. b The same results expressed in dB vs. frequency.

Fig. 8 Simulated input reflection coefficient of the wideband transistor circuit with different values of Rd. a

On the Smith chart, curves 1–3 correspond to Rd=25; 45, and 65Ω, respectively, while Cd=0.13pF, Ls=

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figures of these two circuits are measured on-wafer at room temperature. Description of the circuits and their measured results will be presented below.

Figures9and10are the photograph and schematic of the 3–8 GHz LNA. It is mainly the 1nH source inductor Ls, 1.5nH inter-stage Ld, and 0.2pF loading capacitor Cd, that

contribute to the wideband input matching. The coupling between Ls and Ld allows the

reduction of the chip size. To reduce its power consumption, a slightly smaller transistor is used for the first stage. To ensure that the equivalent Cgdis still sufficient to sustain the

wideband matching mechanism, an external capacitor Cexis added. The large inductor Lbias

on the drain branch is for DC bias purpose and has small impact on S11in 3–8 GHz. Since

this Lbias tends to introduce a negative Re[Zin] at very low frequency, Rbias is used to

stabilize this amplifier.

Figure11shows the measured and simulated S-parameters of this 3–8 GHz LNA where

the both the S11and S22are below -10dB, S21around 15dB, and S22far below -20dB. For

each measured scattering parameter, there are two simulated counterparts, technically SS and TT corners, to account for the inevitable process variation. The bias is set at Vd1=

1V and Id1=9.5 mA for the first-stage transistor, Vd2= 1V and Id2=7.5 mA for the second

stage, and Vd3= 1V and Id3=7.4 mA for the last stage. Figure12shows the same S11and

S22on the Smith chart, and both resemble the familiar wideband hook shape. Figure 13

Fig. 9 Photograph of the 3–8 GHz LNA. The chip size is 1400×1000 μm2. T1, T2, and T3are the three

transistors.

Fig. 10 Schematic of the 3–8 GHz LNA.

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Fig. 11 Measured and simulated S-parameters of the 3–8 GHz wideband LNA. a S21and S11where the solid

curves are the measured results and the dashed curves are their simulated counterparts in two circumstances. b S12and S22.

Fig. 12 Measured and simulated S11and S22of the 3–8 GHz wideband LNA on the Smith chart. a The solid

curve is the measured S11 and the two dashed curves are the simulated counterparts. b Measured and

simulated S22.

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shows the measured noise figure and the linearity (IIP3) of this circuit. The total power consumption of this amplifier is 24.4mW.

Figures14and15 are the photograph and schematic of the 8–25 GHz five-stage LNA

where the design methodology is similar to that of the 3–8 GHz one. To simplify the bias Fig. 14 Photograph of the

8–25 GHz CMOS LNA. The chip size is 945×1245μm2. T

1, T2,

T3,T4,and T5are the five

transistors.

Fig. 15 Schematic of the 8–25 GHz CMOS LNA. There is only one drain bias and one gate bias needed for this 5-stage circuit.

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Fig. 16 Measured and simulated S-parameters of the 8–25 GHz wideband LNA. a Measured (solid) and simulated (dashed) S21and S11. b Measured and simulated S12and S22.

Fig. 18 Measured S21, S11and noise figure of the 8–25 GHz LNA. a Measured S21and S11where the solid

curves are with Vd= 2V, Idis 37, 50, and 62 mA; the dashed curves are with Vd= 1V, Idis 31, 42, and

53 mA, b Measured noise figure with Vd= 2V (solid) and Vd= 1V (dashed) with different bias current.

Fig. 17 Measured and simulated S11and S22of the 8–25 GHz wideband LNA on the Smith chart. a The

solid curve is the measured S11 and the dashed curves are the simulated counterparts. b Measured and

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scheme, only one drain bias and one gate bias are used. Isolation along the common drain bus between each stage is provided by the long transmission lines that surround the periphery of this chip. A small chip size of 945×1245μm2can thus be obtained. With Vd=

1.8V and Id=62 mA, both the measured and simulated S11and S22are below -10 dB, S21

around 15 dB, and S22 far below -20dB, as shown in Figs. 16 and 17. Apparently, an

increase of the input inductor by the use of bond-wire can easily move the S11loop upward

on the Smith chart and surround the zero point, therefore, lowers the input reflection coefficient further. The total power consumption is 112mW. To explore this circuit’s performance under different bias conditions, Fig. 18shows the measured input reflection coefficient, gain, and noise figure at different bias conditions where the solid curves are at Vd= 2V, Idis 37, 50, and 62 mA; the dashed curves are with Vd= 1V and Idis 31, 42, and

53 mA, respectively.

4 Conclusion

In this paper, the input matching technique for common source wideband LNA design has been thoroughly analyzed. The agreement between the simulated input impedance of the LNA and its calculated counterpart confirms the accuracy of our analysis. To demonstrate its wideband potential, both the 3–8 GHz and 8–25 GHz low noise amplifiers using TSMC 0.18-μm RF-CMOS process are designed, fabricated and measured.

Acknowledgment The authors are very grateful for the support of the National Chip Implementation Center (CIC), Hsinchu, Taiwan, R.O.C., for chip fabrication and high frequency measurement.

References

1. WPAN High Rate Alternative PHY Task Group 3a (TG3a), IEEE 802.15, 2007 [Online]. Available:

http://www.ieee802.org/15/pub/TG3a.html

2. N. R. Erickson, R. M. Grosslein, R. B. Erickson, and S. Weinreb,“A cryogenic focal plane array for 85– 115 GHz using MMIC preamplifiers,” IEEE Trans. Microwave. Theory Tech. 47(12), 2212–2219 (1999), Dec.

3. N. Wadefalk, et. al., “Cryogenic wide-band ultra-low noise IF amplifiers operating at ultra-low DC power,” IEEE Trans. Microwave Theory Tech. 51(6), 1705–1711 (2003), Jun.

4. X. Guan and C. Nguyen,“Low-power-consumption and high-gain CMOS distributed amplifiers using cascade of inductively coupled common-source gain cells for UWB systems,” IEEE Trans. Microwave Theory Tech. 54(8), 3278–3283 (2006), Aug.

5. P. Heydari,“Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA,” IEEE J. Solid-State Circuits. 42(9), 1892–1904 (2007), Sept.

6. L. Yang, K. S. Yeo, A. Cabuk, J. Ma, M. A. Do, and Z. Lu,“A novel CMOS low-noise amplifier design for 3.1-to 10.6-GHz ultra-wide-band wireless receivers,” IEEE Trans. Circuits Syst. I. 53(8), 1683–1692 (2006), Aug.

7. A. Ismail and A. Abidi,“A 3–10-GHz low-noise amplifier with wideband LC-ladder matching network,” IEEE J. Solid-State Circuits, 39(12), 2269–2277 (2004), Dec.

8. A. Bevilacqua, C. Sandner, A. Gerosa, and A. Neviani,“A fully integrated differential CMOS LNA for 3–5-GHz ultrawideband wireless receivers,” IEEE Microwave Wireless Compon. Lett. 16(3), 134–136 (2006), Mar.

9. Y.-J. E. Chen and Y.-I. Huang,“Development of Integrated Broad-Band CMOS Low-Noise Amplifiers,” IEEE Trans. Circuits Syst. I. 54(10), 2120–2127 (2007), Oct.

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10. C.-T. Fu, and C.-N. Kuo,“3∼11-GHz CMOS UWB LNA using dual feedback for broadband matching,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., San Francisco, California, pp. 67–70, 2006. 11. C.-T. Fu, C.-L. Ko, C.-N Kuo, and Y.-Z. Juang, “A 2.4–5.4-GHz Wide Tuning-Range CMOS

Reconfigurable Low-Noise Amplifier,” IEEE Trans. Microwave Theory Tech. 56(12), 2754–2763 (2008), Dec.

12. R. Hu,“Wide-band matched LNA design using transistor’s intrinsic gate-drain capacitor,” IEEE Trans. Microwave Theory Tech., 54(3), 1277–1286 (2006), Mar.

數據

Fig. 1 The simulated input reflection coefficient S in of the proposed transistor circuit with L d =0 and 0.6nH, respectively, while C d =0.13pF, R d =25 Ω, and L s =0.3nH.
Table 1 Parameters in the small-signal model of the 216-micron 27-finger tsmc n-type transistor
Fig. 3 The proposed transistor circuit used in the wideband analysis. S in C gs gddmRCG gdmdCGC C gd C dZβYαGm1 R d L d mgddCG2L1ω − L s gs smCLG gddsmRCG L s gddsCLC gddsCRLsdgdLCLFig
Fig. 6 Simulated input reflection coefficient of the wideband transistor circuit with different values of L s
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