358 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 3, MARCH 2007
A 90-dB
10-Gb/s Optical Receiver Analog
Front-End in a 0.18-
m CMOS Technology
Wei-Zen Chen, Member, IEEE, and Da-Shin Lin
Abstract—A 10-Gb/s 90-dB optical receiver analog front-end (AFE), including a transimpedance amplifier (TIA), an automatic gain control circuit, and a postamplifier (PA), is fabricated using a 0.18- m CMOS technology. In contrast with a conventional lim-iting amplifier architecture, the PA is consisted of a voltage ampli-fier followed by a slicer. By means of the TIA and the PA codesign, the receiver front-end provides a 3-dB bandwidth of 7.86 GHz and a gain bandwidth product (GBW) of 248.5 THz-. The tiny photocurrent received by the AFE is amplified to a differential voltage swing of 900 mVppwhen driving 50- output loads. The measured input sensitivity of the optical receiver is 13 dBm at a bit-error rate of10 12with a231 1 pseudorandom test pattern. The optical receiver AFE dissipates a total power of 199 mW from a 1.8-V supply, among which 35 mW is consumed by the output buffer. The chip size is1300 m 1796 m.
Index Terms—Optical receiver, postamplifier (PA), transformer, transimpedance amplifier (TIA).
I. INTRODUCTION
T
HIS PAPER describes an optical receiver analog front end (AFE) that incorporates a transimpedance amplifier, an au-tomatic gain control circuit, and a post amplifier (PA) in a single chip. Conventionally, the PA is basically a limiting amplifier which consists of identical gain cells and with equal gain-band-width performance in each gain stage [2], [6], [7]. However, in such a multistage cascaded amplifier, the last few stages may be driven into large-signal operation mode, and the overall signal bandwidth is limited by the first few stages. It turns out that the gain and bandwidth assignment for each gain stage is not opti-mally designed.Different from the prior art, in this design, the PA is com-posed of a voltage amplifier followed by a slicer, whose gain and bandwidth are assigned separately. Thus, their gain band-width product (GBW) requirement per stage can be further relaxed so as to save power dissipation. The proposed receiver also provides several advantages over conventional multiple chips solutions [1]–[3]. First, tiny photocurrent generated from the photodetector can be on-chip enlarged to a logic level. It increases noise immunity and off-chip interference can be
Manuscript received March 16, 2006; revised June 5, 2006. This work was supported in part by projects under Contract NSC-93-2220-E009-004 and Con-tract 93-EC-17-A-07-S1-001, by Mediatek Inc., and by the Industrial Tech-nology Research Institute (ITRI)/SoC TechTech-nology Center (STC).
W.-Z. Chen is with the Department of Electronics Engineering, Na-tional Chiao-Tung University, Hsin-Chu, Taiwan 300, R.O.C. (e-mail: wzchen@mail.nctu.edu.tw).
D.-S. Lin was with National Chiao-Tung University, Hsin-Chu, Taiwan 300, R.O.C. He is now with MediaTek Inc, Hsin-Chu, Taiwan 300, R.O.C.
Digital Object Identifier 10.1109/TVLSI.2007.893625
avoided. Second, no interstage matching networks are required at the transimpedance amplifier (TIA) output stage and the input stage of the PA. Broadband matching networks in general induce gain loss and are power hungry. By these means the re-ceiver manifests a GBW as high as 248.5 THz- and consumes much less power while fewer peaking inductors are required in comparison to the prior art.
This paper is organized as follows. Section II describes the architecture of the optical receiver. The TIA and the PA are codesigned, and the design issues of the receiver AFE are dis-cussed in Section III. To achieve both wide-band and high gain design goals, inductive peaking techniques are adopted using 3-D symmetric transformers [4]. In this paper, distributed ca-pacitance models [13] of the 3-D transformer are proposed, and its superiorities over the conventional architectures are investi-gated in detail. Their performance comparisons are discussed in Section IV. Section V describes the experimental results. Fi-nally, our conclusions are presented in Section VI.
II. OPTICALRECEIVERARCHITECTURE
The receiver architecture is shown in Fig. 1, which integrates a transimpedance amplifier, an automatic gain control (AGC) circuit, and a PA in a single chip. To alleviate bandwidth degra-dation caused by the parasitic capacitance of the photodetector and IC package, a regulated cascode (RGC) input stage is adopted [5]. The TIA architecture is in pseudo differential configuration with shunt-feedback for better sensitivity and higher common mode noise immunity. Furthermore, an AGC loop is built in to avoid data jitter induced by signal overload. The AGC is composed of an amplitude detector, a comparator, and an integrator [15]. As the TIA’s output swing exceeds a threshold voltage, the AGC will be activated to keep output amplitude constant by turning on the tunable feedback resistors M3 and M4. Otherwise, the AGC will be disabled, and M3 and M4 are switched off for high-gain and low-noise operation. The single ended TIA output is converted to a fully differential signal by the B1 amplifier in conjunction with the R1 and C1 low-pass filter. The conversion gain of the TIA is chosen to make its output swing overpass the sensitivity level of the PA, and its bandwidth is chosen to compromise between ISI and noise performance [7].
Different from our previous work in [7], the PA is consisted of a voltage amplification stage (for small-signal amplification) followed by a slicing stage (for large signal operation). In con-trast to a conventional limiting amplifier that is composed of five or six identical gain cells [2], [6], [7], the voltage amplifier is de-signed to provide a sufficient gain to fully switch the slicer. In
Fig. 1. Optical receiver architecture.
this case, a three-stage cascaded amplifier is required for a min-imum power dissipation. Thus the required GBW per gain stage is much relaxed compared to that of conventional architectures, and no peaking inductors are required in the voltage amplifier design. The slicer functions as a predriver for the output buffer. As a large-signal operation stage, it also provides 24-dB conver-sion gain before driving the last buffer stage, and the bandwidth degradation caused by the slicer is almost negligible [8].
III. TIAANDPA CODESIGN
For an optical receiver, the input sensitivity is limited by the input referred noise current , which can be expressed
(1) where is the conversion gain of the TIA, and represent the input referred noise current of the TIA and the input referred noise voltage of the PA, BW and BW de-note their noise bandwidth, respectively. The lower bound of the is chosen to avoid the PA degrading the input sensitivity level, and the input referred noise current of the TIA is essen-tial to the overall receiver performance. As a rule of thumb, the 3-dB bandwidth of the TIA is chosen to be about 0.7 bit rate to compromise between ISI and noise performance, while the 3-dB bandwidth of the PA is chosen for about 1.2 bit rate to minimize ISI.
In this design, to achieve an input sensitivity level of 13 dBm with a photodetector whose responsivity is 1 A/W, the transimpedance amplifier is designed to provide a conver-sion gain of 50 dB and a 3 dB bandwidth of about 8 GHz. The TIA output is then enlarged and limited to a voltage swing of 900 mVpp (differential) to drive external 50– loads by the PA. The corresponding conversion gain in the post amplifica-tion stage is about 40 dB. Since the output stage delivers high
output current and introduces significant capacitance to the amplifier core, inverse scaling [16] is not applied in this design [2].
Conventional PA is comprised of identical cascaded gain cells [2], [6], [7]. Assuming each gain cell is identical and approxi-mated by a two-pole amplifier, its conversion gain can be de-scribed by A(s), where
(2) Here, denotes the small-signal dc gain, is the corre-sponding damping factor, and is the nature frequency. Let the targeted 3 dB bandwidth of an N-stage cascaded amplifier be , and the conversion gain be . For a flat response, the required gain bandwidth product (GBW) per stage can be ex-pressed as [2], [6]
GBW (3)
For a targeted bandwidth of 12 GHz and a conversion gain of 40 dB, according to (3), a five-stage limiting amplifier demands a GBW of 49 GHz per stage, and, thus, inductive peaking for bandwidth enhancement is required in a conventional design. In contrast to a conventional limiting amplifier that is comprised of identical gain cells, in this design, the PA is constructed of a voltage preamplifier (small-signal operating stage) followed by a slicer (large-signal operating stage). For the same input sensi-tivity level, the preamplifier only needs to provide 16-dB voltage gain to fully switch the slicer. Thus, a three-stage voltage am-plifier is chosen for a minimum power dissipation by the analyt-ical model proposed in [6]. It corresponds to a required GBW of 35 GHz per stage according to (3), which is much relaxed compared to that of a conventional stand-alone limiting ampli-fier with identical gain cells. A lower GBW per stage means no special peaking inductors are required in the gain cell design,
360 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 3, MARCH 2007
and the chip area can be further saved. The slicer stage, which is consisted of three identical buffers, further provides 24-dB con-version gain before driving the last output buffer. Since it is a large-signal operating stage, the bandwidth degradation caused by the slicer is negligible [8].
The core circuit of the voltage amplifier is shown in Fig. 2(a), which is based on Cherry-Hooper circuit architecture with ac-tive feedback [2], [17]. Compared to the prior art in [2], since the GBW requirement of the gain cell is much relaxed, thus no peaking inductor is required to save area. Also, different from our previous work in [7] using resistive feedback, unilaterally active feedback avoids tradeoffs between the feedback factor (close loop gain) and the open loop gain (close loop bandwidth) of the voltage amplifier.
Let C1 and C2, respectively, represent the parasitic capaci-tance at the drain node of M1 and M3, and denote the transconductance of the differential pair and , and be the transconductance of the active feedback stage , the conversion gain of the voltage amplifier can be derived as [2]
(4) where
(5) (6) (7) For a maximally flat Butterworth response, the 3-dB band-width of the voltage amplifier is about . In addition, it has been shown in [2] that the active feedback can increase the GBW of the voltage amplifier beyond the technology . The core cell of the slicer is shown in Fig. 2(b). Herein, a symmetric trans-former is utilized to accelerate voltage switch and balance the rising and the falling time of the output waveform at a high voltage level.
IV. DISTRIBUTEDCAPACITANCEMODEL OFTRANSFORMERS
To realize broadband amplifiers under low supply voltage, inductive peaking techniques are applied in the TIA, slicer, and buffer stage design [9]. Conventional planar inductors and transformers are in general bulky and occupy significant chip areas [10], [11]. Although a miniaturized 3-D inductor structure has been proposed [12], it is asymmetric and two inductors are needed in a fully differential amplifier. To reduce inductor counts and save chip area, a 3-D inverting type transformer is utilized in this design [4]. Furthermore, as a peaking inductor in a broad band amplifier design, the self-resonant frequency of the inductor is more demanding than its quality factor since the peaking inductor would become a capacitive load as the operating frequency exceeds . The resonant frequency can be viewed as the frequency at which the peak magnetic and electric energy are equal, and can
Fig. 2. (a) Gain cell of preamplifier. (b) Gain cell of slicer.
be determined by , where and , respectively, represent the equivalent inductance and capacitance of the inductor [11], [12]. In the following, the of both a planar inductor and our proposed 3-D symmetric transformer are analyzed utilizing a distributed capacitance model, and their comparisons are investigated in detail.
For a given peak voltage of across the inductor and a stored electric energy of in the structure, the equivalent capaci-tance can be calculated by [11]
(8) To derive the electric energy stored in the parasitic capacitors of the inductor, the following assumptions are made to simplify the derivations [11]–[13].
1) Voltage distribution is proportional to the length of the metal track.
Fig. 3. Cross-sectional view and voltage profile of a planar inductor.
2) The voltage potential is equal in half turn of the metal wire in the transformer and is determined by averaging the volt-ages of the previous half turn and the next one.
Fig. 3 illustrates the cross-sectional view of an turn planar inductor and its electrical potential distribution. Assume the lengths of each half turn are denoted as , the metal width is , metal thickness is , and the total length of the metal wire is .
Define , the voltage profile of the in-ductor can be described as
(9) Based on these assumptions, the voltage of the th half turn can be approximated as
(10) Let denote the unit capacitance of metal to sub-strate, the electrical energy stored in the capacitor between the metal layer and the substrate can be expressed as , where
(11) In addition, let denote the unit side-wall capacitance between metal and , the electric energy stored in the side-wall parasitic capacitors between the metal layers can be expressed as , where
(12) Combining (11) and (12), the total electric energy
stored in the structure can be derived as [13]
(13)
Fig. 4. Cross-sectional view and voltage profile of a 3-D transformer.
Thus, the effective parasitic capacitance of a planar inductor can be expressed as , which is shown here
(14) On the other hand, the cross-sectional view of an n-turn, single turn per layer, 3-D symmetric transformer and its elec-trical potential distribution is illustrated in Fig. 4. In case of a differential excitation, the center point of the transformer can be connected to a common mode voltage and ac grounded. The voltage profile of the transformer can be described as
(15) Also, it can be seen that the metal to substrate capacitors exist in the bottom two metal layers only. Based on the same assump-tions previously mentioned, the electrical energy stored in the capacitor between the metal layer and the substrate can be ex-pressed as , where
(16) On the other hand, since there is only one turn on a metal layer, the side-wall capacitors do not exist. Let denote the unit metal to metal overlapped capacitance between metal k and , the electrical energy stored in the metal to metal parasitic capacitors can be represented as
362 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 3, MARCH 2007
By taking both (16) and (17) into account, the total electric energy stored in the structure can be derived as [13]
(18) The effective parasitic capacitance of the 3-D transformer can be expressed as , which is also shown here
(19) Based on the derived equations in (14) and (19), for an in-ductor pair with an inductance of 2.85 nH in each branch, five turns, metal width m, metal spacing m, and an inner diameter of 110 m, the effective parasitic capacitance of the 3-D transformer is reduced by 45% compared to that of a planar inductor pair . The significant improvement is due to the following reasons.
1) The metal to substrate capacitance is minimized and only exists in the bottom two metal layers.
2) The side-wall capacitors are negligible in this architecture, which would become significant in a deep-submicrometer process [13].
3) The metal to metal parasitic capacitances are reduced by increasing the distance between metal plates and mini-mizing the electrical potential across the top and bottom plates [4].
By EM simulation, the 3-D transformer manifests a higher self resonant frequency (12 GHz versus 9 GHz) compared to its planar counterpart owing to a smaller . Furthermore, the substrate loss of the 3-D transformer is improved by a differ-ential stimulus, and a wider operating bandwidth is achieved in contrast to a single-ended driven counterpart [14]. Most impor-tant of all, the chip area of the 3-D transformer is 47% smaller than that of its planar counterparts, which is essential in the mul-tistage broadband amplifier design.
V. EXPERIMENTALRESULTS
For performance measurement, the receiver IC and a photode-tector are mounted on a printed circuit board. The eye diagrams and the bit error rate performance are characterized using Agi-lent N4901B. The pattern generator sends a PRBS test pattern to modulate a commercial 10-Gb/s laser module. With an Oepic-P5030A photodetector, whose responsivity is 1 A/W and parasitic capacitance is about 0.15 pF, the measured sensi-tivity of the optical receiver AFE at 10 Gb/s is about 13 dBm for a bit error rate of less than . The bit error rate perfor-mance is summarized in Fig. 5. The tolerated power level is up to 0 dBm by the built-in automatic gain control scheme. The
Fig. 5. Measured bit error rate performance of the optical receiver.
Fig. 6. Measured 5 Gb/s eye diagram with2 0 1 PRBS input. (X-axis: 33.3 ps/div,Y -axis: 100 mV/div, Jitter(pp) = 24:42 ps).
input-referred noise current of the optical receiver is derived from its sensitivity performance. As
Sensitivity dBm (20) where is the responsivity of the photodetector, and is the extinction ratio. The corresponding is about 6.68 A .
Fig. 6 and Fig. 7 illustrate the measured eye diagrams at 5 and 7 Gb/s, respectively, at sensitivity level. The data jitter is about 3.94 ps (24.4 ps ) and 3.96 ps (30.9 ps ). Fig. 8(a) illustrates the measured 10 Gb/s eye diagram at the input power of sensitivity level ( 13 dBm), and Fig. 8(b) illus-trates the measured 10 Gb/s eye diagram when the input power is overloaded. The measured jitters are about 4.95 ps (30.96 ps ) and 5.67 ps (36.27 ps ). Fig. 9(a) illustrates the sim-ulated conversion gain of the receiver AFE and the TIA, and the frequency response of the PA, including the voltage amplifier and the slicer, is shown in Fig. 9(b).
In summary, the receiver front-end provides a conversion gain of 90 dB , among which 50 dB is provided by the TIA. It is capable of delivering 900 mV differential voltage swings to 50 output loads directly. The dB is about 7.86 GHz,
Fig. 7. Measured 7 Gb/s eye diagram with2 0 1 PRBS input. (X-axis: 24 ps/div,Y -axis: 97.3 mV/div, Jitter(pp) = 30:93 ps).
Fig. 8. Measured 10 Gb/s eye diagram with2 0 1 PRBS input. (a) Input power= 013 dBm. (b) Input power = 0 dBm (X-axis: 16 ps/div, Y -axis: 100 mV/div).
which is limited by the transimpedance amplifier. The PA ex-hibits a conversion gain of 40 dB. The voltage amplifier pro-vides a 16-dB conversion gain to fully switch the slicer. As a tapered buffer, the slicing stage further provides 24-dB voltage gain. The tolerated power level is up to 0 dBm by the built in automatic gain control scheme. Operating under a 1.8-V supply,
Fig. 9. (a) Simulated frequency response of the optical receiver analog front-end. (b) Simulated frequency response of the post voltage amplifier.
Fig. 10. Chip photograph.
the power dissipation is 199 mW, among which 35 mW is con-sumed by the output buffer. Fig. 10 illustrates the chip photo. Fabricated in a 0.18- m CMOS technology, the chip size is
364 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 3, MARCH 2007
TABLE I PERFORMANCE BENCHMARK
VI. CONCLUSION
This paper describes the design of a 10-Gb/s optical receiver analog front-end in a generic 0.18- m CMOS technology. The optical AFE provides a conversion gain of 90 dB and a 3 dB bandwidth of about 7.86 GHz, which is limited by the transimpedance amplifier. A regulated cascode input stage is utilized to decouple the loading effect at the input node, and wide bandwidth is achieved by means of shunt feedback and inductive peaking. The PA is composed of a preamplification stage followed by a slicing stage. In contrast to a conventional limiting amplifier which consists of identical gain cells, the GBW requirements in the proposed topology are much relaxed, thus, both peaking inductors and power consumption can be saved. Moreover, an AGC is built in to alleviate overload induced data jitter. Instead of using bulky planar inductors or two asymmertric 3-D inductors, a novel fully symmetric 3-D transformer for inductive peaking is utilized in this design to save chip area. A distributed capacitance model of the 3-D transformer is also proposed. The superiority of the proposed transformer over conventional planar counterpart is demonstrated.
The performance benchmark of this paper, our previous work in [7], and the prior art of TIA and limiting amplifiers [1]–[3], [7], [16], [18] is summarized in Table I. By a single chip integration, gain-bandwidth requirement for the individual building blocks can be rearranged and further optimized. The proposed prototype is power efficient, manifests a GBW as high as 248.5 THz- , while fewer peaking inductors are required.
ACKNOWLEDGMENT
The authors would like to thank the Chip Implementation Center for chip fabrication.
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Wei-Zen Chen (M’99) received the B.S., M.S., and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsin-Chu, Taiwan, R.O.C., in 1992, 1994, and 1999, respectively.
After graduation, he was with the Industrial Tech-nology Research Institute (ITRI), Hsin-Chu, Taiwan, working on RF integrated circuit design. Since 2002, he has been with the Department of Electronics En-gineering, National Chiao-Tung University, where he is currently an Associate Professor. From 1999 to 2002, he was with the Department of Electrical Engineering, National Central University, Chung-Li, Taiwan. His research interests include integrated circuits and systems for high speed networks and wireless communications.
Dr. Chen is a member of Phi-Tau-Phi.
Da-Shin Lin was born in Changhua, Taiwan, R.O.C., in 1976. He received the B.S. degree in mechanical engineering from National Central University, Chung-Li, Taiwan, in 2001, and the M.S. degree from the Institute of Electronics, National Chiao-Tung University, Hsin-Chu, Taiwan, in 2004.
Currently, he is an Engineer with the R&D Division, MediaTek, Inc., Hsin-Chu, Taiwan. His research interests include CMOS optical receiver design.
