應用於輸出級驅動電路之靜電放電防護設計

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(1)國立臺灣師範大學電機工程學系碩士論文. 指導教授：林群祐博士. 應用於輸出級驅動電路之靜電放電防護設計 On-Chip ESD Protection Design for Output Driver Applications. 研究生：邱彥璉撰中華民國一百零五年七月.

(2) 應用於輸出級驅動電路之靜電放電防護設計. 學生 : 邱彥璉. 指導教授 : 林群祐博士. 國立臺灣師範大學電機工程學系碩士班. Abstract (Chinese). 隨著製程演進，晶片微縮，靜電放電(ESD)容易造成晶片內部的電子元件遭受到不可逆之破壞，而所有的微電子產品必須符合此可靠度的規範。因此，靜電放電防護的可靠度議題必須被探討。在積體電路的應用上，本論文設計了幾種新型的靜電放電防護元件，此元件在 0.18um 1.8V/3.3V CMOS 製程下實現。透過實驗分析的結果，防護元件可以承受較大的訊號擺幅和能夠耐受 2kV 的人體放電模式之靜電放電測試。為了驗證靜電放電防護元件在實際電路上的效能，本論文使用堆疊元件的輸出級驅動器並搭配嵌入式矽控整流器（Embedded SCR）。一種新型的靜電放電防護設計被提出來，為了改善其靜電放電的防護能力。此電路在 0.18um 1.8V/3.3V CMOS 製程下實現。本論文所提出的防護設計經實際驗證，在不影響電路正常操作的情況下，有效改善其靜電放電的防護能力，證明所提出的設計可以改善靜電放電防護的能力。. 關鍵字：靜電放電，輸出驅動器，矽控整流器. I.

(3) On-Chip ESD Protection Design for Output Driver Applications Student：Yan-Lian Chiu. Advisors：Dr. Chun-Yu Lin. Department of Electrical Engineering National Taiwan Normal University. Abstract (English). With the continuous evolution of semiconductor integrated circuits (ICs) process, electrostatic discharge (ESD) events are likely to cause internal electronic components of the wafer suffered irreversible damage. All microelectronic products must meet the reliability specifications. Therefore, ESD must be taken into consideration. In the application of integrated circuit, several novel ESD protection devices are designed in this work. By designing the structure, this work has been fabricated in 0.18μm 1.8V/3.3V CMOS process. In the experimental results, this design can achieve large swing tolerance and endure 2kV human-body-model (HBM) test. In order to verify the protection ability of ESD protection device on the circuits, a novel design of stacked-device output driver with embedded silicon-controlled rectifier (SCR) is proposed to improve the ESD robustness. This work has been fabricated in 0.18-um 1.8V/3.3V CMOS process. Besides, the transient behaviors of the proposed design during normal operation are not degraded. Therefore, the proposed design can be used to improve the ESD robustness of stacked-device output driver. Keywords: electrostatic discharge (ESD), output driver, silicon-controlled rectifier (SCR).. II.

(4) Acknowledgment. 首先，要感謝我的指導教授林群祐老師三年來耐心的教導，使我能順利完成碩士學位，在老師不厭其煩地給予更正和指導下，讓學生在靜電放電防護設計的領域上奠定了成功的基礎，特別是老師在做研究上的認真和嚴謹的態度，以及在論文寫作上的技巧都讓學生非常的欽佩。也很感謝老師給予了「晶焱科技」實習的機會，讓學生能夠直接接觸到靜電放電防護相關的工作，並且有幸認識了此產業的諸位先進，對我來說實在是受益良多阿!. 在研究過程中，我要感謝「國家晶片系統設計中心」讓我有機會下線對我的電路進行驗證，此外還要感謝「國立交通大學電子工程學系」，提供量測機台協助晶片的量測與分析；同時也要感謝「晶焱科技」的陳東暘協理以及「國立交通大學電子工程學系」的陳柏宏教授，在碩士口試時，提出了相當多寶貴的建議和想法，使學生的論文能更加精進。. 另外還要感謝奈米積體電路與系統實驗室的同伴們，李冠儀、傅偉豪、林孟霆、黃國倫、邱鈺凱、岳軒宇、陳俊宇等同學及學弟妹們，能與大家一起共識的這段時間，將會是我人生中最美好的回憶之一，在這裡要特別感謝李冠儀和邱鈺凱同學，您們改變了整間實驗室的氣氛，凝聚了大家對實驗室的向心力，也很感謝傅偉豪同學，帶我進入 ACGN 的世界，體會到另一個次元的感動，雖然這個坑有點深但我不怕因為我愛她，真的由衷的感謝你們，讓我碩班生涯的盡頭是五彩繽紛的；感謝平行計算實驗室的劉暐辰同學，邀請我一起去看中華職棒，能在碩班生涯遇到興趣相符的朋友，我真的很幸運；感謝同是 102 級的宋旻翰和鍾宜曄同學提供了碩士口試準備的經驗及相關資訊；感謝系辦的鄭琇文小姐，在報帳上給予我相當多的協助；感謝師大學生輔導中心的陳淑雲老師，在我碩一時謝謝您跟我聊了很多，讓我在心情上或多或少有了一些釋放，有了陳老師的協助使我在面對碩班生涯更踏實了些；幫助我的人太多了，在此無法一一致謝，真的很謝謝 III.

(5) 您們，因為能遇見您們我的碩班生涯才會如此精彩。最後，我要特別至上我最深的感謝給我的父親邱進東先生、母親李琇琴女士、弟弟邱彥勳先生，沒有你們的支持、照顧與鼓勵，就沒有我今日的成就。這幾年家裡發生相當多重大的變故，都是家人在幫忙處理，很多事情我無法幫忙分攤說來實在慚愧，家人讓我沒有後顧之憂的完成碩士學位，在此衷心的地感謝您們；同時也要向二十二歲的自己說一聲謝謝你，當初有繼續堅持下去沒有輕言放棄，才能有現在的成果。另外，要祝福所有在這些年與我相處過的朋友們，有緣與您們相識是我的榮幸，願大家心想事成，身體健康。論文雖然力求完善，但錯誤之處在所難免，請各位讀者不吝惜給予寶貴的意見，使本論文能更加完整。. 邱彥璉謹誌於師大中華民國一零五年七月. IV.

(6) Contents Abstract (Chinese)……………………………………………………………………………………………………….I Abstract (English)………………………………………………………………………………………………………II Acknowledgment………………………………………………………………………………………………………………III Content s……………………………………………………………………………………………………………… V Table Captions…………………………………………………………………………………………………………VII Figure Captions…………………………………………………………………………………………………………VIII Chapter 1 Introduction……………………………………………………………………….1 1.1 Background of ESD……………………………………………………….1 1.2 Models of ESD………………….…………………………………….........1 1.3 Typical Design of On-Chip ESD Protection Circuits…………………3 1.3.1 ESD Protection Design with Diodes……………………………….4 1.3.2 ESD Protection Design with GGNMOS……………...……………5 1.3.3 ESD Protection Design with SCR………………………………….6 1.4 Applications for Output Driver……………………………………………8 1.4.1 Architecture of Electrical Stimulator………......….……… ………8 1.4.2 ESD Protection Challenges………………………………………..10 1.5 Thesis Organizat ion……………………………………………... ........12 Chapter 2 Novel Dual-Directional SCR in Output Stage with Monopolar Configuration…………………………………………………13 2.1 Introduction…………………………………………………………………….13 2.2 ESD Robustness of Stand-Alone Output Stage with monopolar configuration………………………………………………….15 2.3 ESD Protection Design for Output Stage………………………………………18 2.3.1 DDSCR-Based Devices for CMOS On-Chip ESD Protection…….18 2.3.2 Novel Dual-Directional SCR………………………………………..20 2.4 Experimental Results of novel DDSCR…………………………………22 2.4.1 Measured TLP I-V Characteristics…………………………………..22 2.4.2 Measured DC I-V Characteristics…………………………………....26 2.4.3 Measured ESD Robustness…………………………………………...30 2.4.4 Measured Parasitic Capacitance……………………………………...30 2.4.5 Document Comparison of DDSCR…………………………………....33 V.

(7) 2.5 Summary…………………………….………………………....………………33 Chapter 3 Novel Embedded SCR Device in Output Stage with Bipolar Configuration…...…….……………………………………..34 3.1 Introduction………………………….……………………………....... ....34 3.2 Design of Novel High Voltage Output Driver……………………………37 3.3 Proposed ESD Protection Design for Stacked-Device Output Driver…44 3.4 Experimental Results………………………………………………………47 3.4.1 Transient Waveforms……………………………………………………48 3.4.2 ESD Robustness and TLP I-V Characteristics………………………52 3.4.3 Reliability of Novel High Voltage Output Driver………………….63 3.4.4 Document Comparison of High Voltage Output Drivers…………..63 3.5 Summary……………………………………………………………………….64 Chapter 4 Conclusions and Future Works…………………………………………………65 4.1 Conclusions…………………………….……………………………………..65 4.2 Future Works…..………………….…….……………………………………66 References……………………………………………………………………………………67 Vita………………………………………………………………………………...................73 Publication List………………………………………………………………………………74. VI.

(8) Table Captions Table 2.1.. The I-V characteristics of the DDSCR measured results by DC curve tracer…….29. Table 2.2.. Design parameters of test devices…….……….....................................................31. Table 2.3.. Measurement results of test devices………………………………………….......32. Table 2.4.. Comparison among the DDSCR-based devices for on-chip ESD protection…….33. Table 3.1.. Design parameters of the test circuits…………………….....................................47. Table 3.2.. HBM ESD robustness of test circuits…………………………………………….53. Table 3.3.. TLP measurement results, as zapping from GND-VOUT and VOUT to 3xVDD………………………………………………….62. Table 3.4.. TLP measurement results, as zapping from VOUT-to-GND and 3xVDD-to-VOUT………………………………………………62. Table 3.5.. Comparison of high voltage output drivers…………………………....................64. VII.

(9) Figure Captions Fig. 1.1.. Equivalent circuits of HBM ESD test…………………................................2. Fig. 1.2.. Equivalent circuits of MM ESD test………………………………………..2. Fig. 1.3.. Typical design of on-chip ESD protection circuits………….……………...3. Fig. 1.4.. ESD protection design with diodes…………………...................................4. Fig. 1.5.. ESD protection design with GGNMOS……………………………………5. Fig. 1.6.. ESD protection design with SCR…………………………………………..6. Fig. 1.7.. ESD protection design window of ESD protection device………………....7. Fig. 1.8.. Output driver with monopolar configuration…………….…………….......9. Fig. 1.9.. Output driver with bipolar configuration…………………………………..9. Fig. 1.10.. Integrated circuits with large signal swing……..........................................11. Fig. 2.1.. Cross-sectional view of conventional ESD protection devices: (a) diode, (b) GGNMOS, (c) SCR, and (d) DDSCR....................................14. Fig. 2.2.. Cross-sectional view of output stage of electrical stimulator: (a) stacked PMOS and (b) stacked NMOS…………………......................16. Fig. 2.3.. Measured TLP I-V curves of (a) stacked PMOS and (b) stacked NMOS……………………………………...………...............17. Fig. 2.4.. (a) The cross-sectional view of the dual-direction SCR structure, (b) Equivalent circuit schematic of a SCR device………………...............19. Fig. 2.5.. Layout top view of DDSCR1 with (a) 4 segments and (b) 8 segments…………………………………………………………….20. Fig. 2.6.. Cross-sectional view of DDSCR1 along (a) A-A' and (b) B-B'…………21. Fig. 2.7.. Cross-sectional view of DDSCR2 along (a) A-A' and (b) B-B'…………21. Fig. 2.8.. Cross-sectional view of DDSCR3 along (a) A-A' and (b) B-B'…………22. Fig. 2.9.. Measured TLP I-V curves of DDSCR1 with (a) 4 segments and (b) 8 segments…………………………………………………………….23. Fig. 2.10.. Measured TLP I-V curves of DDSCR2 with (a) 4 segments and (b) 8 segments…………………………………………………………….24. VIII.

(10) Fig. 2.11.. Measured TLP I-V curves of DDSCR3 with (a) 4 segments and (b) 8 segments…………………………………………………………….25. Fig. 2.12.. I-V characteristics of DDSCR1 with 4 segments measured by dc curve tracer……………………………………………....26. Fig. 2.13.. I-V characteristics of DDSCR1 with 8 segments measured by dc curve tracer……………………………………………....27. Fig. 2.14.. I-V characteristics of DDSCR2 with 4 segments measured by dc curve tracer……………………………………………....27. Fig. 2.15.. I-V characteristics of DDSCR2 with 8 segments measured by dc curve tracer……………………………………………....28. Fig. 2.16.. I-V characteristics of DDSCR3 with 4 segments measured by dc curve tracer……………………………………………....28. Fig. 2.17.. I-V characteristics of DDSCR3 with 8 segments measured by dc curve tracer……………………………………………....29. Fig. 2.18.. Measured parasitic capacitances………………….………………………30. Fig. 3.1.. Block diagram of 3xVDD-tolerant stacked-device output driver..................36. Fig. 3.2.. ESD current paths in 3xVDD-tolerant stacked-device output driver with high-voltage-tolerant ESD clamp circuit……………………..36. Fig. 3.3.. Structure of high voltage output driver fabricated in 0.18-um 3.3-V CMOS process…………………………………………………….38. Fig. 3.4.. (a) A triply-stacked output driver (b) high-level drive (c) low-level drive………………………………………………...............39. Fig. 3.5.. Simulated transient waveforms of high voltage output driver with VIN-VOUT…………………………………………………………….40. Fig. 3.6.. Simulated transient waveforms of high voltage output driver with Vi2-Vi2b……………………………………………………...............41. Fig. 3.7.. Simulated transient waveforms of high voltage output driver with Vi1a-Vi2a-Vi3a………………………………………………...............41. Fig. 3.8.. Simulated |Vgd|, |Vgs|, and |Vds|, of transistors in output stage: (a) MN2, (b) MN1, (c) MN0, (d) MP0, (e) MP1, and (f) MP2………..................43. IX.

(11) Fig. 3.9.. Cross-sectional view of stacked NMOS devices in output stage of conventional 3xVDD-tolerant stacked-device output driver……………45. Fig. 3.10.. Cross-sectional view of stacked NMOS devices with additional P+ region in output stage of proposed 3xVDDtolerant stacked-device output driver with embedded SCR………………46. Fig. 3.11.. Measured transient waveforms of general 3xVDD-tolerant stackeddevice output driver in Output Driver_10………………………………...48. Fig. 3.12.. Measured transient waveforms of general 3xV DD-tolerant stackeddevice output driver in Output Driver_30………………………………...49. Fig. 3.13.. Measured transient waveforms of general 3xV DD-tolerant stackeddevice output driver in Output Driver_50………………………………...49. Fig. 3.14.. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_10_10.…………………………………………………….50. Fig. 3.15.. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_30_10.…………………………………………………….50. Fig. 3.16.. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_50_10.…………………………………………………….51. Fig. 3.17.. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_30_30.…………………………………………………….51. Fig. 3.18.. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_50_50.…………………………………………………….52. Fig. 3.19.. Measured TLP I-V curves of Output Driver_10 and Driver + SCR_10_10, as zapping from VOUT to 3xVDD.…………………..54. Fig. 3.20.. Measured TLP I-V curves of Output Driver_10 and Driver + SCR_10_10, as zapping from GND to VOUT…………………......55. X.

(12) Fig. 3.21.. Measured TLP I-V curves of Output Driver_30 and Driver + SCR_30_10, as zapping from VOUT to 3xVDD.…………………..55. Fig. 3.22.. Measured TLP I-V curves of Output Driver_30 and Driver + SCR_30_10, as zapping from GND to VOUT.………………….....56. Fig. 3.23.. Measured TLP I-V curves of Output Driver_50 and Driver + SCR_50_10, as zapping from VOUT to 3xVDD.…………………..56. Fig. 3.24.. Measured TLP I-V curves of Output Driver_50 and Driver + SCR_50_10, as zapping from GND to VOUT.………………….....57. Fig. 3.25.. Measured TLP I-V curves of Output Driver_30 and Driver + SCR_30_30, as zapping from VOUT to 3xVDD.…………………..57. Fig. 3.26.. Measured TLP I-V curves of Output Driver_30 and Driver + SCR_30_30, as zapping from GND to VOUT.………………….....58. Fig. 3.27.. Measured TLP I-V curves of Output Driver_50 and Driver + SCR_50_50, as zapping from VOUT to 3xVDD.…………………..58. Fig. 3.28.. Measured TLP I-V curves of Output Driver_50 and Driver + SCR_50_50, as zapping from GND to VOUT.…………………….54. Fig. 3.29.. Measured TLP I-V curves, as zapping from GND to VOUT of driver with embedded SCR…………………………………………….60. Fig. 3.30. Measured TLP I-V curves, as zapping from VOUT to GND……………….60 Fig. 3.31.. Measured TLP I-V curves, as zapping from 3xVDD to VOUT………………61. Fig. 3.32.. Long-term test of high voltage output driver…………………………..….63. Fig. 4.1.. 3xVDD-tolerant stacked-device output driver with high-voltagetolerant ESD clamp circuit……………………………………………….66. XI.

(13) Chapter 1 Introduction. 1.1 Background of ESD The phenomenon of electrostatic discharge (ESD) occurs when an electrostatic voltage slowly develops between an object and its surrounding environment, commonly referred to as ground, then spontaneously discharges as an electrical current impulse [1].. 1.2 Models of ESD A typical specification for a commercial IC on ESD robustness is 2kV for the humanbody-model (HBM) and 200V for the machine-model (MM) [2]-[4]. The equivalent circuits of HBM and MM ESD tests are shown in Fig. 1.1 and Fig. 1.2, respectively. In the equivalent circuits of HBM ESD test, a 100 pF capacitor represents the charged human body and the 1.5kΩ resistor is used to model the discharging resistance of human body. In the MM ESD test, the circuit component is a 200 pF capacitor with no resistive component. HBM is the most prevalent ESD event model and widely used as a basic ESD protection standard for the semiconductor products at industry.. 1.

(14) 1.5kΩ. R. VESD. 100pF. Device Under Test. Fig. 1.1. Equivalent circuits of HBM ESD test.. R. VESD. 200pF. Fig. 1.2. Equivalent circuits of MM ESD test.. 2. Device Under Test.

(15) 1.3 Typical Design of On-Chip ESD Protection Circuits. ESD failure is the major electronics reliability problems at system level and component. Industrial standards require satisfactory on-chip ESD protection for all ICs and systems, which becomes a constantly increasing IC design challenge for complex ICs using advanced IC technologies [5]. With the design of considering the possible ESD damage sites, the ESD discharging current paths need to be created and constructed. The Typical Design of On-Chip ESD Protection Circuits is shown in Fig. 1.3.. Input PAD. ESD Protection Circuit. ESD Protection Circuit. Internal Circuits. Output PAD. Power-Rail ESD Clamp Circuit. VDD. VSS Fig. 1.3. Typical design of on-chip ESD protection circuits.. The ESD-testing modes at input-output (I/O) pads with respect to VDD or VSS pins, pin-to-pin and the VDD-to-VSS ESD stresses have been specified to judge the wholechip ESD robustness. Under the ESD-stress condition, the VDD-to-VSS ESD clamp circuit can provide a low impendence path to discharge the ESD current between the VDD and VSS power lines.. 3.

(16) 1.3.1 ESD Protection Design with Diodes Diode is widely used as ESD protection. Both its reverse and forward operational mode can be used to conduct ESD current. For reverse biased diode, it has smaller current conduction ability and need to deplete large area to reach the prospective protection specification. For forward biased diode, it is always assisted with power-rail ESD clamp circuits together to realize a rail based protection. Fig. 1.4 show the ESD stress modes on I/O pads. When positive electrostatic discharge form I/O PAD to VSS (positive-to-VSS, PS), electrostatic current will flowing through the D P and then discharge by the power-rail ESD clamp circuit. When negative electrostatic discharge form I/O PAD to VSS (negative-to-VSS, NS), electrostatic current will discharge by the forward bias DN. When positive electrostatic discharge form I/O PAD to VDD (positiveto-VDD, PD), electrostatic current will discharge by forward bias D P. When negative electrostatic discharge form I/O PAD to VDD (negative-to-VDD, ND), electrostatic current will flowing through the power-rail ESD clamp circuit and discharge by the forward bias DN.. Fig. 1.4. ESD protection design with diodes. 4.

(17) 1.3.2 ESD Protection Design with GGNMOS A gate-grounded NMOS (GGNMOS) is widely used in ESD protection. GGNMOS, structure is made from the standard NMOS structure by grounding the gate terminal [6]. Fig. 1.5 also marked the electrostatic discharge path when this circuits is affected by ESD stress. In all different ESD protection devices, GGNMOS is often used in the industry. There are still several issues existed for the GGNMOS structures. Large layout area is required due to its destitute protection reliability needs to be improved to implement a high ESD protection.. Fig. 1.5. ESD protection design with GGNMOS.. 5.

(18) 1.3.3 ESD Protection Design with SCR Silicon-controlled rectifier (SCR) device consists of a vertical PNP and a lateral NPN bipolar transistors to form a 4-layer PNPN (P+/N-well/P-well/N+) structure, which is instinctive in the CMOS processes. Due to have the low holding voltage (V h, about ~1.5V in general CMOS processes) of SCR device [7], the power dissipation (power ≅ IESD×Vh) located on the SCR device during ESD stress is meaningful less than that located on other ESD protection devices, such as the BJT, diode, and field-oxide device. The SCR device can sustain a much higher ESD level within a smaller layout area in CMOS ICs. Fig. 1.6 also marked the electrostatic discharge path when this circuit is affected by ESD stress.. I/O PAD. Internal Circuits SCR. P+ N-Well P-Well. N+. PS. NS. VSS. Fig. 1.6. ESD protection design with SCR.. 6. ND. PD. Power-Rail ESD Clamp Circuit. VDD.

(19) There are some ESD design issue. The first one is ESD design optimization and prediction, which necessitate comprehensive mixed-mode ESD simulation to address the complex coupling effects among process, device, circuit and layout. Second, ESD protection device will introduce parasitic effects, such as resistance (RESD), capacitance (CESD), and leakage current (Ileak), etc., which will unfavorably affect IC chip performance [8]. To promise the effectiveness of an ESD protection design, it has been approved that the I-V characteristics of ESD protection devices should locate within the ESD protection window. As shown in Fig. 1.7, the ESD protection window is defined that trigger voltage (Vt1) should be smaller than breakdown voltage of internal circuits (VBD, Internal) to ensure successful protection, and holding voltage (V hold) should be higher than the operational voltage (VDD) to avoid the a possible latch-up issue [9].. VDD. Holding Voltage (Vh) 10%~20%. 10%. Internal circuit Breakdown Voltage. Current (A). ESD Protection Window. Trigger Voltage (Vt1). Vh<VDD, Latch-up issue. Voltage (V). Fig. 1.7. ESD protection window of ESD protection device.. 7. Vt1>VBD, Internal Fail to Protect.

(20) 1.4 Applications for Output Driver. 1.4.1 Architecture of Electrical Stimulator As medical science and electronics engineering evolving, bioelectronics combined the microelectronics technology with medicine knowledge results in a new generation of therapy and healthcare. Nowadays, the stimulator that transmits artificial electrical signals into nervous system to repair some physical functions of a human has been investigated and verified [10]. Therapeutic electrical stimulation (TES) and functional electrical stimulation (FES) systems have been developed for restoring function in different applications such as cardiac pacing, vision restoration, muscle exercising and suppression of epileptic seizure [11]-[13]. Comparing with the traditional treatments by using surgery or medicine, the electrical stimulation is more harmless, flexible, and recoverable [14], [15]. The output driver methodology about electrode configuration is classified into two types: two leads per site (bipolar stimulation) and one lead per site (monopolar stimulation). To realize the output driver, the usually used configurations of monopolar and bipolar stimulators are shown in Figs. 1.8 and 1.9 [16], [17]. In Fig. 1.8, the monopolar stimulator utilizes the dual supply voltages (VHH and VLL) with anodic and cathodic output drivers to deliver anodic and cathodic stimulus currents. In Fig. 1.9, the bipolar stimulator utilizes the single supply voltage (VHH) with single output driver from VHH.. 8.

(21) VHH Anodic Output Driver. I/O Cathodic Output Driver. ZL. VLL Fig. 1.8. Output driver with monopolar configuration.. VHH. VHH. Output Driver. Output Driver. I/O. I/O ZL. Fig. 1.9. Output driver with bipolar configuration.. 9.

(22) The anodic and cathodic stimulus currents of the bipolar stimulator are generated by reversing the current paths using switches. The monopolar stimulation is preferred over a bipolar counterpart if the current is intended to spread over a wider area, and the monopolar stimulation is usually more efficient than the bipolar stimulation [18]. For multi-channel application, the number of interconnect leads between the stimulator and tissue by monopolar type is a half of the number by bipolar type, reducing chip area of contact pads . On the other hand, in the simultaneous stimulation using electrode arrays, the bipolar stimulation is preferred to monopolar stimulation, as the former can reduce crosstalk among neighboring sites [19].. 1.4.2 ESD Protection Challenges Biomedical electronics is becoming indispensible to health care solutions. Obviously, reliability may be the most important affect for biomedical electronics because of its life threatening nature, especially for portable and implantable devices. For some biomedical electronics applications, the signal swing at input/output (I/O) pads may be higher than the supply voltage (VDD) or lower than 0V (GND) [20]. To prevent from the reliability issues such as electrical overstress, the stacked MOS configuration is used to design the biomedical integrated circuits in these applications. Of course, the ESD protection devices at I/O pads also need to tolerate the signal swing which is higher than VDD or lower than 0V, as illustrated in Fig. 1.10.. 10.

(23) Fig. 1.10. Integrated circuits with large signal swing.. Because of its essence, biomedical electronics obviously requires robust ESD protection. Various distinct ESD design challenges must be affected for biomedical ICs. [21] - [23]. ESD has been considered as a major reliability in semiconductor industry for. As CMOS technology scales down, design of ESD protection circuits becomes more challenging. This is due to smaller channel lengths and thinner gate oxides in advanced technologies that make them more sensitive to ESD damages. As a result, design window for the ESD protection circuit becomes narrower. In the design of an ESD protection circuit, in addition to ESD robustness, the interaction between the main circuit and the protection circuit should be well understood.. 11.

(24) The ESD specifications of commercial IC products are generally required to be higher than 2 kV in HBM ESD stress. In order to design a robust ESD protection circuit, a deeper insight of the device behavior under high current and high voltage stress conditions is required.. 1.5 Thesis Organization. In Chapter 1, introduces the basic background knowledge of ESD protection design and the thesis organization. In Chapter 2, novel dual-directional silicon-controlled rectifier (DDSCR) ESD protection devices will be introduced in detail. In this study, all testing devices are fabricated in 0.18um CMOS process. In Chapter 3, novel high-voltage output driver is successfully verified in 0.18um CMOS process in the chapter, some simulation of the high-voltage output driver will be introduced. Next, the novel high-voltage output driver will also be equipped with the novel ESD protection devices to measure the ESD robustness of the circuits. The last chapter, chapter 4, recapitulates the major consideration of this thesis and concludes with suggestions for future investigation.. 12.

(25) Chapter 2 Novel Dual-Directional SCR in Output Stage with Monopolar Configuration 2.1 Introduction CMOS technologies are attractive to implement the integrated circuits for biomedical electronics applications [24]-[26]. However, the transistors currently used in CMOS technologies are vulnerable to electrostatic discharge (ESD) events, which is the major reliability concern. In order to sustain the required ESD robustness, the on-chip ESD protection devices must be added in the IC products. A typical specification for a commercial IC on human-body-model (HBM) ESD robustness is 2 kV. If consider the reliability of biomedical integrated circuits used on the human, the required ESD robustness may be even higher. The conventional ESD protection devices have the drawback of leakage current. Fig. 2.1 shows the conventional ESD protection devices used in the CMOS technologies, including diode, gate-grounded NMOS (GGNMOS), silicon-controlled rectifier (SCR), and dual-directional SCR (DDSCR) [27]-[30]. A parasitic pn junction exists in the conventional ESD protection devices with the common grounded P-substrate, as shown in Fig. 2.1. In this chapter, a novel ESD protection design for output stage is investigated in a 0.18-um 1.8V/3.3V CMOS process.. 13.

(26) VI/O < -VD I/O. GND. N+. P+. STI. STI. VI/O < -VD I/O. GND. N+. N+ P+. STI. STI. P-Well. P-Well. P-Substrate. P-Substrate. (a) VI/O < -VD I/O. STI. N+ P+. N-Well. STI. (b) VI/O < -VD I/O. GND. N+ P+. STI. STI. STI. N+ P+. STI. N-W e l l. P-Well. GND. N+ P+. P-W e l l N-W e l l. P-S u b s t r a t e. P-Substrate. (c). (d). Fig. 2.1. Cross-sectional view of conventional ESD protection devices: (a) diode, (b) GGNMOS, (c) SCR, and (d) DDSCR.. 14. STI.

(27) 2.2 ESD Robustness of Stand-Alone Output Stage with monopolar configuration. The stacked PMOS and NMOS of the output stage of electrical stimulator are shown in Figs. 2.2(a) and 2.2(b), respectively. To investigate the I-V characteristics of the stand-alone output stage of electrical stimulator under ESD-like conditions, the transmission line pulsing (TLP) system with a 10-ns rise time and a 100-ns pulse width is used. The TLP-measured I-V curves of the test devices are shown in Fig. 2.3. According to the test results, the stacked PMOS and NMOS under ESD-like conditions can sustain up to 27V and 25V, respectively, without damage (increasing leakage current). In other word, the additional ESD protection device must clamp the overshoot voltage lower than 25V to prevent the electrical stimulator from ESD damages.. 15.

(28) GND. I/O (Guard-Ring) Gate-Bias Control. P+ STI. P+. Gate-Bias Control. P+ N+. STI. P+. Gate-Bias Control. P+ N+. STI. N-Well. VHH. P+. P+ N+. STI. N-Well. P+ STI. STI. N-Well. P-Substrate. (a) I/O. GND. (Guard-Ring). VLL. P+ STI. Gate-Bias Control. P+ N+ STI. NWell. Gate-Bias Control. N+. P+ N+. N+. STI. P-Well. NWell. Gate-Bias Control. P+ N+ STI. P-Well. NWell. N+. P+ STI. P-Well. STI. NWell. Deep N-Well P-Substrate. (b) Fig. 2.2. Cross-sectional view of output stage of electrical stimulator: (a) stacked PMOS and (b) stacked NMOS.. 16.

(29) Leakage Current (A) 10-10 0.5. 10-9. 10-8. 10-7. 10-6. 10-5. 10-4. 15. 20. 25. 30. TLP Current (A). 0.4. 0.3 TLP I-V Leakage 0.2. 0.1. 0.0 0. 5. 10. TLP Voltage (V). (a) Leakage Current (A) 10-12 0.05. 10-11. 10-10. 10-9. 10-8. 10-7. TLP Current (A). 0.04. 0.03. 0.02. TLP I-V Leakage. 0.01. 0.00 0. 5. 10. 15. 20. 25. 30. TLP Voltage (V). (b) Fig. 2.3. Measured TLP I-V curves of (a) stacked PMOS and (b) stacked NMOS. 17.

(30) 2.3 ESD Protection Design for Output Stage. 2.3.1 DDSCR-Based Devices for CMOS On-Chip ESD Protection A typical SCR device provides only one direction ESD protection path. The dualdirection SCR (DDSCR) device can protect each I/O pad against ESD stress in the PSmode (positive-to-VSS), NS-mode (negative-to-VDD), PD-mode (positive-to-VDD), and ND-mode (negative-to-VSS) [31]. The device structure of a DDSCR device illustrated in Fig. 2.4(a) is a symmetrical five-layer NPNPN structure comprising two vertical NPN and one lateral PNP. Adding another layer of N+ isolation can avoid leakage current issue of conventional ESD devices. When a positive ESD pulse is applied to the anode of DDSCR and its cathode is relatively grounded. The positive ESD current can be discharged through the current path1 is shown in Fig. 2.4(b). Similarly, when a negative ESD pulse is applied to anode of DDSCR with its cathode grounded, the negative ESD current can be discharged through the current path2 is shown in Fig. 2.4(b). The DDSCR provides low holding voltage and low impedance path to discharge the ESD current under every stress mode.. 18.

(31) Anode. STI. NWell. P+. STI. Cathode. N+. N+. STI. N-Well. P-Well Q3. STI. Q2. Q1. P+. P-Well. STI. NWell. N+ isolation. (a). Anode Path 1. Q3. Q1. Q2. Path 2. Cathode (b) Fig. 2.4 (a) The cross-sectional view of the dual-direction SCR structure, (b) Equivalent circuit schematic of a SCR device.. 19.

(32) 2.3.2 Novel Dual-Directional SCR In this work, a novel dual-directional SCR (DDSCR) device for ESD protection in biphasic output driver was proposed. This design can achieve low leakage, large swing tolerance, and high ESD robustness. Two kinds of layout of the DDSCR device are shown in Fig. 2.5. In the Figs. 2.5(a) and 5(b), the SCR paths are divided into 4 and 8 segments, respectively. The SCR paths consist of P+/P-well/N-well/P-well/N+. The SCR paths along A-A' and B-B' provide the discharging path from I/O to GND and from GND to I/O, respectively, as shown in Fig. 2.6. The distance between I/O and GND of SCR is wished to be minimized, so the layout style with minimized “d” is used. The test devices have been fabricated in a 0.18um 1.8-V CMOS process. All the dimensions of test devices are listed in Table 2.2.. P+ A. A'. B. N+. B'. P+ NWell. w. P+. N+. N+. P+. P+. N+. N+. P+. N+. P+. A B w. P+. NWell. A' B'. N+. N+. N+. P+. N+. P+. P+. N+. s. N+. P+. d. d. (a). (b). Fig. 2.5. Layout top view of DDSCR1 with (a) 4 segments and (b) 8 segments.. 20. s.

(33) In order to reduce the switching voltage of DDSCR1 device to provide more effective ESD protection for the internal circuits, the DDSCR2 and DDSCR3 was invented. The devices structure of the DDSCR2 and DDSCR3 are illustrated in Fig. 2.7 and Fig. 2.8. The DDSCR2 and DDSCR3 devices are made by adding an N+ diffusion is inserted into the N-well to lower the avalanche breakdown voltage of N-well/P-well junction. The inserted N+ diffusions are connected out as the n-trigger nodes of the DDSCR2 and DDSCR3 devices.. I/O. A STI. NWell. P+. N+. STI. NWell. P-Well. X1. I/O. GND. P-Well. A' B STI. STI. NWell. NWell. GND. N+. P+. STI. NWell. P-Well. P-Well. Deep N-Well. Deep N-Well. P-Substrate. P-Substrate. X2. X3. X2. X1. X1. X2. (a). X3. X2. B' STI. NWell. X1. (b). Fig. 2.6. Cross-sectional view of DDSCR1 along (a) A-A' and (b) B-B'.. I/O. A STI. NWell. P+. GND. STI. STI. N-Well. P-Well. X1. N+. GND. N+ S N+ T I. P-Well. A' B STI. STI. NWell. NWell. N+ S N+ T I. P-Well. I/O. STI. N+. STI. N-Well. P-Well. Deep N-Well. Deep N-Well. P-Substrate. P-Substrate. X2. X3. X2 X1 X4 X5. X5 X4 X1 X2. (a). X3. X2. (b). Fig. 2.7. Cross-sectional view of DDSCR2 along (a) A-A' and (b) B-B'.. 21. P+. X1. B' STI. NWell.

(34) I/O. A STI. NWell. P+. GND. STI. STI. N-Well. P-Well. X1. N+. GND. N+ S N+ T I. A' B STI. STI. NWell. NWell. P-. P-Well. N+ S N+ T I. P-. P-Well. I/O. STI. N+. STI. N-Well. P-Well. Deep N-Well. Deep N-Well. P-Substrate. P-Substrate. X2. X3. X2 X1 X4 X5. X5 X4 X1 X2. (a). X3. P+. X2. B' STI. NWell. X1. (b). Fig. 2.8. Cross-sectional view of DDSCR3 along (a) A-A' and (b) B-B'.. 2.4 Experimental Results of novel DDSCR. 2.4.1 Measured TLP I-V Characteristics To investigate the turn-on behavior and the I-V characteristics in high-current regions of the ESD protection devices, the transmission-line-pulsing (TLP) system with 10-ns rise time and 100-ns pulse width is used. The TLP-measured I-V characteristics are shown in Figs. 2.9~2.11. The trigger voltages (Vt1) of the test devices are about 9~12V, which means the ESD protection devices can sustain the signal swing up to ±9V. The secondary breakdown current (It2) of ESD protection device, which indicated the current-handling ability, can also be obtained from the TLP-measured I-V curves. All these measurement results are also listed in Table 2.3.. 22.

(35) 2.5. TLP Current (A). 2.0. 1.5. DDSCR1 with 4 Segments 1.0 w=20um w=40um w=60um. 0.5. 0.0 0. 2. 4. 6. 8. 10. 12. 14. TLP Voltage (V) (a). 2.5. TLP Current (A). 2.0. 1.5. DDSCR1 with 8 Segments. 1.0. w=20um w=40um w=60um. 0.5. 0.0 0. 2. 4. 6. 8. 10. 12. 14. TLP Voltage (V) (b) Fig. 2.9. Measured TLP I-V curves of DDSCR1 with (a) 4 segments and (b) 8 segments. 23.

(36) 2.5. TLP Current (A). 2.0. 1.5. DDSCR2 with 4 Segments 1.0 w=20um w=40um w=60um. 0.5. 0.0 0. 2. 4. 6. 8. 10. 12. 14. TLP Voltage (V). (a). 2.5. TLP Current (A). 2.0. 1.5. DDSCR2 with 8 Segments 1.0 w=20um w=40um w=60um. 0.5. 0.0 0. 2. 4. 6. 8. 10. 12. 14. TLP Voltage (V). (b) Fig. 2.10. Measured TLP I-V curves of DDSCR2 with (a) 4 segments and (b) 8 segments. 24.

(37) 2.5. TLP Current (A). 2.0. 1.5. DDSCR3 with 4 Segments 1.0 w=20um w=40um w=60um. 0.5. 0.0 0. 2. 4. 6. 8. 10. 12. 14. TLP Voltage (V) (a). 2.5. TLP Current (A). 2.0. 1.5. DDSCR3 with 8 Segments 1.0 w=20um w=40um w=60um. 0.5. 0.0 0. 2. 4. 6. 8. 10. 12. 14. TLP Voltage (V) (b) Fig. 2.11. Measured TLP I-V curves of DDSCR3 with (a) 4 segments and (b) 8 segments. 25.

(38) 2.4.2 Measured DC I-V Characteristics In order to further ascertain the possibility of the parasitic bipolar to reach and maintain holding state, relationship between power supply voltage and holding voltage need to be explored. In this work, the snapback holding voltage of novel DDSCR devices, have been investigated by curve tracer, the measurement was carried out with Tektronix 370A curve tracer as shown in Fig. 2.12~ 2.17. All these measurement results are listed in Table 2.1.. Fig. 2.12. I-V characteristics of DDSCR1 with 4 segments measured by dc curve tracer.. 26.

(39) Fig. 2.13. I-V characteristics of DDSCR1 with 8 segments measured by dc curve tracer.. Fig. 2.14. I-V characteristics of DDSCR2 with 4 segments measured by dc curve tracer.. 27.

(40) Fig. 2.15. I-V characteristics of DDSCR2 with 8 segments measured by dc curve tracer.. Fig. 2.16. I-V characteristics of DDSCR3 with 4 segments measured by dc curve tracer.. 28.

(41) Fig. 2.17. I-V characteristics of DDSCR3 with 8 segments measured by dc curve tracer.. Table 2.1 The I-V characteristics of the DDSCR measured results by DC curve tracer. Test Device. DDSCR1 with 4 Segments. DDSCR2 with 4 Segments. DDSCR3 with 4 Segments. w (um). Vt1 (V). 20. 1.49. 40. 1.20. 60. Test Device. w (um). Vt1 (V). 20. 1.14. 40. 1.18. 1.06. 60. 1.02. 20. 1.22. 20. 1.51. 40. 1.14. 40. 1.20. 60. 0.99. 60. 0.98. 20. 1.20. 20. 1.16. 40. 1.00. 40. 1.16. 60. 0.96. 60. 1.06. DDSCR1 with 8 Segments. DDSCR2 with 8 Segments. DDSCR3 with 8 Segments. 29.

(42) 2.4.3 Measured ESD Robustness The ESD robustness of test devices are evaluated by the HBM tester. The failure criterion is defined as the I-V characteristics shifting over 30 % from its original curve after ESD stressed at every ESD test level. All these measurement results are listed in Table 2.3.. 2.4.4 Measured Parasitic Capacitance With the on-wafer measurement, the two-port S-parameters of the test devices were measured by using the vector network analyzer. The parasitic effects of the pads have been removed by using the de-embedding technique [32]. The parasitic capacitance of each test device can be extracted from the S-parameters. Fig. 2.12 shows the extracted parasitic capacitance of the test devices.. Fig. 2.18. Measured parasitic capacitances.. 30.

(43) Table 2.2 Design parameters of test devices. Test Device DDSCR1 with 4 Segments. DDSCR1 with 8 Segments. DDSCR2 with 4 Segments. DDSCR2 with 8 Segments. DDSCR3 with 4 Segments. DDSCR3 with 8 Segments. w d s (um) (um) (um). X1 X2 X3 X4 X5 (um) (um) (um) (um) (um). 20. 2.26. 5. 1.29. 0.43. 1.4. N/A. N/A. 40. 2.26. 10. 1.29. 0.43. 1.4. N/A. N/A. 60. 2.26. 15. 1.29. 0.43. 1.4. N/A. N/A. 20. 2.26. 2.5. 1.29. 0.43. 1.4. N/A. N/A. 40. 2.26. 5. 1.29. 0.43. 1.4. N/A. N/A. 60. 2.26. 7.5. 1.29. 0.43. 1.4. N/A. N/A. 20. 2.26. 5. 1.29. 0.92. 0.42. 0.8. 1.5. 40. 2.26. 10. 1.29. 0.92. 0.42. 0.8. 1.5. 60. 2.26. 15. 1.29. 0.92. 0.42. 0.8. 1.5. 20. 2.26. 2.5. 1.29. 0.92. 0.42. 0.8. 1.5. 40. 2.26. 5. 1.29. 0.92. 0.42. 0.8. 1.5. 60. 2.26. 7.5. 1.29. 0.92. 0.42. 0.8. 1.5. 20. 2.26. 5. 1.29. 0.92. 0.42. 0.8. 1.5. 40. 2.26. 10. 1.29. 0.92. 0.42. 0.8. 1.5. 60. 2.26. 15. 1.29. 0.92. 0.42. 0.8. 1.5. 20. 2.26. 2.5. 1.29. 0.92. 0.42. 0.8. 1.5. 40. 2.26. 5. 1.29. 0.92. 0.42. 0.8. 1.5. 60. 2.26. 7.5. 1.29. 0.92. 0.42. 0.8. 1.5. 31.

(44) Table 2.3 Measurement results of test devices. Test Device. HBM Level (kV). Vt1 (V). Vh (V). It2 (A). C (fF). RON (ohm). DDSCR1. 2.0. 11.5. 2.0. 0.8. 67.1. 6.55. with 4. 4.0. 11.5. 2.0. 1.6. 110.5. 3.39. Segments. 5.0. 11.6. 1.9. 2.3. 154.9. 2.85. DDSCR1. 2.0. 11.8. 2.3. 0.8. 70.6. 6.82. with 8. 3.5. 11.6. 2.3. 1.6. 116.4. 3.43. Segments. 5.0. 11.8. 2.2. 2.4. 163.1. 2.92. DDSCR2. 2.0. 10.4. 2.0. 0.8. 74.9. 6.48. with 4. 3.5. 10.5. 1.9. 1.5. 121.0. 3.32. Segments. 5.0. 10.4. 1.9. 2.3. 167.8. 2.89. DDSCR2. 2.0. 10.4. 2.0. 0.8. 78.9. 6.73. with 8. 3.5. 10.4. 2.0. 1.5. 127.4. 3.47. Segments. 4.5. 10.4. 2.0. 2.2. 176.7. 2.91. DDSCR3. 2.0. 9.2. 2.0. 0.7. 62.5. 6.57. with 4. 3.5. 9.2. 1.9. 1.5. 116.7. 3.35. Segments. 5.0. 9.2. 2.0. 2.2. 169.5. 2.81. DDSCR3. 2.0. 9.2. 2.0. 0.8. 80.1. 6.63. with 8. 3.5. 9.2. 2.0. 1.5. 128.0. 3.43. Segments. 4.5. 9.2. 2.0. 2.2. 177.3. 2.88. 32.

(45) 2.4.5 Document Comparison of DDSCR The comparison among various DDSCR-based devices for CMOS on-chip ESD protection has been summarized in Table 2.4. The trigger voltage (Vt1) and the holding voltage (Vh) of DDSCR-based devices must be finely designed to fully and effectively protect the output stage.. Table 2.4 Comparison among the DDSCR-based devices for on-chip ESD protection. Test Device. Technology. References [44]. 0.18um CMOS. 30. N/A. References [47] DDSCR1 with 4 Segments. 0.18um CMOS. DDSCR2 with 4 Segments. 0.18um CMOS. DDSCR3 with 4. 0.18um. Segments. CMOS. W (um). HBM Level. Vt1 (V). Vh (V). It2 (A). C (fF). RON (ohm). 3.0. 16.9. 4.5. 2.9. N/A. 3.33. N/A. N/A. 10.2. 4.6. 2.2. N/A. N/A. 20. 2.0. 11.5. 2.0. 0.8. 67.1. 6.55. 40. 4.0. 11.5. 2.0. 1.6. 110.5. 3.39. 60. 5.0. 11.6. 1.9. 2.3. 154.9. 2.85. 20. 2.0. 10.4. 2.0. 0.8. 74.9. 6.48. 40. 3.5. 10.5. 1.9. 1.5. 121.0. 3.42. 60. 5.0. 10.4. 1.9. 2.3. 167.8. 2.89. 20. 2.0. 9.2. 2.0. 0.7. 62.5. 6.57. 40. 3.5. 9.2. 1.9. 1.5. 116.7. 3.35. 60. 5.0. 9.2. 2.0. 2.2. 169.5. 2.81. (kV). 2.5 Summary. The dual-directional SCR (DDSCR) device has been developed for on-chip ESD protection in output driver. Verified in 0.18-um CMOS process, this design can achieve low leakage, large swing tolerance, and high ESD robustness. 33.

(46) Chapter 3 Novel Embedded SCR Device in Output Stage with Bipolar Configuration. 3.1 Introduction. In nanoscale CMOS technologies, the feature size has been scaled down to improve circuit performances with the decreased power supply voltage for low-power applications. However, the higher output voltage levels are still needed for the external I/O to communicate with other circuits in the microelectronic systems or subsystems, such as 3.3V or 5V for some signaling standards. Even higher output voltage levels are needed for some applications, such as >10V for display driver and biomedical stimulator. Therefore, the high-voltage output driver must be designed with the consideration of high-voltage tolerance [33], [34]. To avoid the overstress issue without using additional high-voltage device, stacking low-voltage devices is usually used for the high-voltage output driver [35]-[37]. Once the voltage drop divided equally across the stacked devices, this configuration allows for higher voltage, and no single device is overstressed. A conventional 3xVDD-tolerant stacked-device output driver is shown in Fig. 3.1, which consists of a control circuit and a pair of triply-stacked MOS in the output stage [38], [39].. 34.

(47) Electrostatic discharge (ESD), which is the significant reliability issue, may cause the damage in IC products. The transistors currently used in CMOS technologies are vulnerable to ESD events. To provide the required ESD robustness, on-chip ESD protection design must be added in the integrated circuits, including the output driver [40]. For example, a typical specification for a commercial IC on HBM ESD robustness is 2kV. With the help of high-voltage-tolerant ESD clamp circuit [41]-[43] and the parasitic body-to-drain diodes, the on-chip ESD protection for stacked-device output driver is shown in Fig. 3.2. The ESD currents can be discharged from VOUT to 3xVDD (path ①), from GND to VOUT (path ②), from VOUT to GND (path ①+③), and from 3×VDD to VOUT (path ④ + ② ). This ESD protection design can provide the corresponding ESD current paths during all kinds of ESD events at VOUT pad. However, in the output stage, the sizes of PMOS devices are usually larger than those of NMOS devices to have symmetrical driving ability, which makes the asymmetrical ESD current paths. With the smaller NMOS devices, the ESD robustness of path ② is usually lower than that of path ①. Of course, the designer can use some dummy NMOS devices or additional ESD diodes to improve the ESD robustness. In this work, a more efficient design by using embedded silicon-controlled rectifier (SCR) to improve ESD robustness is proposed. With the assistance of embedded SCR, the ESD robustness of NMOS part of stacked-device output driver can be improved without using any additional ESD protection device and layout area.. 35.

(48) 3xVDD. MP2. MP1. MP0. Control Circuit. VIN. VOUT. MN0. MN1. MN2 GND. Fig. 3.1. Block diagram of 3xVDD-tolerant stacked-device output driver. 3xVDD. MP2. ① MP1. Control Circuit. MP0. VOUT. MN0. High-Voltage-Tolerant ESD Clamp Circuit. VIN. ③ . ② ④. MN1. MN2 GND. Fig. 3.2. ESD current paths in 3xVDD-tolerant stacked-device output driver with highvoltage-tolerant ESD clamp circuit. 36.

(49) 3.2 Design of Novel High Voltage Output Driver. Fig. 3.3 shows the design of high voltage output driver, which consists of bias circuit, control circuit, and output stage. The 3.3V transistors in a standard 0.18μm CMOS process are used. Once the voltage differences across each transistor are lower than 3.63V (3.3V + 10%) [48], the foundry promises their reliability. The output driver is controlled by the input signal (VIN) with voltage swing between 0V and 3.3V. The aims of this design are that the output signal (VOUT) can swing between 0 and ~10V (3xVDD), and the voltage differences across each transistor are lower than 3.63V to prevent from reliability issues, whether the output driver is turned on or off. In order to sustain the high voltage (~10V) without gate-oxide overstress, the stacked MOS configuration between 3xVDD and ground is used. The bias circuit, which consists of three PMOSdiodes (MR1~MR3), is used to provide the biases of 2xVDD (VDD2) and 1xVDD (VDD1) from the 3xVDD. To reduce the bias current to the range of < mA, three PMOS with small width/length ratio are used. The control circuit includes two level shifters, and three buffers. The level shifters 1 and 2 transfer the signals with low-voltage level (1xVDD) to the high-voltage levels (2xVDD and 3xVDD). The level shifter 1 with differential structure can transfer the VIN and Vi1a (voltage swing: 0V ~ 1xVDD) to Vi2 and Vi2b (voltage swing: 1xVDD ~ 2xVDD). Similarly, the level shifter 2 can further transfer the Vi2 and Vi2b to Vi3 (voltage swing: 2xVDD ~ 3xVDD). The buffers control the output stage to turn on or off.. 37.

(50) 3xVDD. MP5 Level Shifter 2. MR3. MP2. Vi3a. MN5. Vi3. MP1. VDD2. Level Shifter 1. MR2. MP0. MP4 Vi2b. Vi2a. Vi2. MN4. VOUT MN0. VDD1. MP3 MR1. MN1. Vi1a. VIN MN6. MN3. MN2. GND Level Shifter 1. Level Shifter 2. VDD2. 3xVDD. M07. M08. Vi2b. M15. M16. Vi2. M05. Vi3. M06. M13. M14. VDD1. VDD2. M03 VIN. M04 M01. M02. M11 Vi1a. GND. Vi2. M12 M09. M10. Vi2b. VDD1. Fig. 3.3. Structure of high voltage output driver fabricated in 0.18-um 3.3-V CMOS process.. 38.

(51) As VIN is 0V, the gate potentials of MP0, MP1, and MP2 are designed to be 1xVDD, 2xVDD, and 3xVDD, respectively, so the stacked PMOS are kept off. In the meantime, the gate potentials of MN0, MN1, and MN2 are all 1xVDD, so the stacked NMOS conduct the VOUT to 0V. As VIN is 3.3V, the gate potentials of MN0, MN1, and MN2 are 2xVDD, 1xVDD, and 0V, respectively, so the stacked NMOS are kept off. In the meantime, the gate potentials of MP0, MP1, and MP2 are all 2xVDD, so the stacked PMOS conduct the VOUT to 3xVDD. Shown in Fig. 3.4 is the schematic of a triply-stacked output driver that enables voltage drive up to 3x the transistor rating. Both scenarios are better depicted by the schematics in Fig. 3.4(b) and 3.4(c). Simple device stacking as explained poses certain reliability risks during switching transitions. 3xVDD. MP2. 3xVDD. 3xVDD. VDD2. 3xVDD. MP2. MP2 VDD2-Vt. 3xVDD. MP1. VDD2. VDD2. MP1. MP1 VDD1-Vt. 3xVDD. MP0 VDD1 0. VDD2. VDD1. MP0. Control Circuit. MP0 0. 3xVDD. MN0. VDD2. MN0. MN1. VDD1. MN1. MN2. 0. MN2. VDD1. MN0. VDD1. MN1. VDD1. MN2. 0. VDD2-Vt. VDD1-Vt. (a). (b). 0. (c). Fig. 3.4. (a) A triply-stacked output driver (b) high-level drive (c) low-level drive.. 39.

(52) The stacked-device output driver has been simulated in HSPICE with the 0.18μm CMOS process. Fig. 3.5 ~ 3.7 shows the simulated transient waveforms of stackeddevice output driver. As long as the VIN is 0V or 3.3V, the Vi1a is inverted instantaneously. The Vi2, Vi2a, and Vi2b swing between 3.3V and 6.6V, the Vi3a swing between 6.6V and 9.9V, and the VOUT finally swings between 0V and 9.9V.. 10. 8. Voltage (V). VIN VOUT 6. 4. 2. 0 0. 100. 200. 300. 400. 500. Time (us) Fig. 3.5. Simulated transient waveforms of high voltage output driver with VIN-VOUT.. 40.

(53) 7. Vi2 Vi2b. Voltage (V). 6. 5. 4. 3 0. 100. 200. 300. 400. 500. Time (us) Fig. 3.6. Simulated transient waveforms of high voltage output driver with Vi2-Vi2b.. 10 Vi1a Vi2a Vi3a. Voltage (V). 8. 6. 4. 2. 0 0. 100. 200. 300. 400. 500. Time (us). Fig. 3.7. Simulated transient waveforms of high voltage output driver with Vi1a-Vi2a-Vi3a. 41.

(54) To verify the voltage differences across each transistor are lower than 3.63V during all VIN potentials, a ramp voltage from 0V to 3.3V is injected into VIN, and then the voltage of each node is captured. Fig. 3.8 shows the simulated |Vgd|, |Vgs|, and |Vds|, of each transistor, as the VIN is between 0V and 3.3V. For the MN2, each terminal is constrained to swing between 0V and 1xVDD, as shown in Fig. 3.8(a). For the MN1, its gate potential is kept at 1xVDD, its source potential is constrained to swing between 0V and 1xVDD, and its drain potential will swing between 0V and 2xVDD. Even though, the voltage differences across each terminals of MN1 are still lower than 3.63V, as shown in Fig. 3.8(b). For the MN0, its gate potential will swing between 1xVDD and 2xVDD, its source potential will swing between 0V and 2xVDD, and its drain potential will swing between 0V and 3xVDD. The simulation results show that the voltage differences across each terminals of MN0 are still lower than 3.63V, as shown in Fig. 3.8(c). The operations of MP0~MP2 are complementary to those of MN0~MN2, so the similar results can be found, as shown in Figs. 3.8(d) ~ 3.8(f).. 42.

(55) (a). (b). (c). (d). (e). (f). Fig. 3.8. Simulated |Vgd|, |Vgs|, and |Vds|, of transistors in output stage: (a) MN2, (b) MN1, (c) MN0, (d) MP0, (e) MP1, and (f) MP2. 43.

(56) With the proper design of control circuit, the PMOS and NMOS transistors in output stage are well controlled to turn on or off. The simulation results show that the voltage differences across each transistor are 3.63V at most, which meets the design target. Although the stacked-device output driver with embedded SCR can’t be simulated, its transient behaviors should be equal to the output driver without embedded SCR, since the additional P+ region in the proposed design will not affect the operation of drain, gate, source, and body terminals of three NMOS devices during normal operation.. 3.3 Proposed ESD Protection Design for Stacked-Device Output Driver. The cross-sectional view of NMOS part in output stage of conventional 3xVDDtolerant stacked-device output driver is shown in Fig. 3.9. The N-well and deep N-well regions are used to isolate the P-well region of each stacked NMOS from the common P-substrate. The body-to-drain (P-well/N+) diodes form the ESD current path from GND to Vo. Besides, a parasitic SCR (P-well/Deep N-well/P-well/N+) can also help to discharge the ESD current from GND to VOUT, but its path is too long to effectively discharge the ESD current.. 44.

(57) GND. VOUT. MN2 P+ N+. MN1 N+. STI. NWell. P+ N+. MN0 N+. STI. P-Well Parasitic SCR. NWell. P+ N+. N+. STI. P-Well Deep N-Well. NWell. STI. Parasitic SCR. P-Well. NWell. Parasitic SCR. P-Substrate. Fig. 3.9. Cross-sectional view of stacked NMOS devices in output stage of conventional 3xVDD-tolerant stacked-device output driver.. To have symmetrical ESD protection ability in PMOS and NMOS parts, a stackeddevice output driver with embedded SCR is proposed, as shown in Fig. 3.10. In the proposed design, additional P+ region is added into the N-well region, and then an embedded SCR device is formed from GND to VOUT. Since the existing N-well region is usually large enough to contain the additional P+ region, this design will not increase the layout area. Besides, the SCR device can be safely used without latchup danger in the proposed design, since the anode (GND) potential is always lower than the cathode (VOUT) potential during normal operation, and the SCR device can’t keep turning on. The SCR device has been reported to be useful for ESD protection. The equivalent circuit of the embedded SCR consists of the cross-coupled PNP (P+/N-well/P-well) and NPN (N-well/P-well/N+) BJTs. In the proposed design, the body-to-drain (P-well/N+) diodes play the role of trigger circuit of embedded SCR to enhance the turn-on speed. As ESD stresses from anode (GND) to cathode (VOUT) of the SCR are applied, the diode path will turn on to discharge the initial ESD currents, and then the SCR path will take over to discharge the primary ESD currents. The positive-feedback regenerative 45.

(58) mechanism of PNP and NPN BJTs results in the SCR device becoming highly conductive to make the SCR very robust against ESD stresses. GND. VOUT. MN2 P+ N+. MN1 N+. STI. NWell. P+ N+. MN0 N+. STI. P-Well Parasitic SCR. NWell. P+ N+. Embedded SCR. N+. STI. P-Well. Deep N-Well. NWell. P+ STI. STI. Parasitic SCR. P-Well. NWell. Parasitic SCR. P-Substrate. Fig. 3.10. Cross-sectional view of stacked NMOS devices with additional P+ region in output stage of proposed 3×VDD-tolerant stacked-device output driver with embedded SCR.. This research designed 2 kinds of high-voltage output driver, contains without ESD protective element of the driver, and the driver in the output stage with embedded SCR. The driver match output stage of different sizes to explore the characteristics of electrostatic discharge protection design. Comparison of three different sizes, are used in the output stage of the driver, in output stage finger to change the number of transistors. In order to investigate the reliability of related problems, this study also designed test circuit as shown in Table 3.1.. 46.

(59) Table 3.1. Design parameters of the test circuits. (W/L)n. (W/L)p. MN0~MN2. MP0~MP2. Output. 10/0.35. 10/0.35. Driver_10. um/um. um/um. Output. 30/0.35. 30/0.35. Driver_30. um/um. um/um. Output. 50/0.35. 50/0.35. Driver_50. um/um. um/um. Driver +. 10/0.35. 10/0.35. SCR_10_10. um/um. um/um. Driver +. 30/0.35. 30/0.35. Driver. SCR_30_10. um/um. um/um. with Embedded SCR. Driver +. 50/0.35. 50/0.35. SCR_50_10. um/um. um/um. Driver +. 30/0.35. 30/0.35. SCR_30_30. um/um. um/um. Driver +. 50/0.35. 50/0.35. SCR_50_50. um/um. um/um. Test Circuits. Pure Output Driver. Finger width. Total Width. MN0~. MP0~. MN0~. MP0~. MN2. MP2. MN2. MP2. 10 um. 10 um. 10 um. 10 um. 10 um. 10 um. 30 um. 30 um. 10 um. 10 um. 50 um. 50 um. 10 um. 10 um. 10 um. 10 um. 10 um. 10 um. 30 um. 30 um. 10 um. 10 um. 50 um. 50 um. 30 um. 30 um. 30 um. 30 um. 50 um. 50 um. 50 um. 50 um. 3.4 Experimental Results. To verify the stacked-device output driver in silicon chip, both circuits without and with embedded SCR (pure output driver and driver with embedded SCR) have been fabricated in 0.18μm CMOS process. Each circuit occupies a chip area is less than 250×175μm2, including 3xVDD, GND, VIN, and VOUT pads without high-voltagetolerant ESD clamp circuit.. 47.

(60) 3.4.1 Transient Waveforms A 9.9V supply voltage is used for 3xVDD, a 3.3V and 10kHz square wave is applied to VIN, a 100kΩ resistance is loaded to VOUT, and then the VOUT swing is measured, as shown in Fig. 3.11 ~ 3.18. Fig. 3.11 ~ 3.13 shows the measured waveforms of general stacked-device output driver (pure output driver), and Fig. 3.14~ 3.18 shows those of proposed stacked-device output driver with SCR (driver with embedded SCR). As long as the VIN is 0V or 3.3V, the VOUT of both circuits can swing between 0V and ~9.7V.. Fig. 3.11. Measured transient waveforms of general 3xVDD-tolerant stacked-device output driver in Output Driver_10. .. 48.

(61) Fig. 3.12. Measured transient waveforms of general 3xVDD-tolerant stacked-device output driver in Output Driver_30.. Fig. 3.13. Measured transient waveforms of general 3xVDD-tolerant stacked-device output driver in Output Driver_50. 49.

(62) Fig. 3.14. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_10_10.. Driver + SCR_30_10 10. VIN VOUT. Voltage (V). 8. 6. 4. 2. 0 0. 50x10-6. 100x10-6. 150x10-6. 200x10-6. Time (s). Fig. 3.15. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_30_10. 50.

(63) Driver + SCR_50_10 10. VIN VOUT. Voltage (V). 8. 6. 4. 2. 0 0. 50x10-6. 100x10-6. 150x10-6. 200x10-6. Time (s). Fig. 3.16. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_50_10.. Fig. 3.17. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_30_30. 51.

(64) Fig. 3.18. Measured transient waveforms of proposed 3xVDD-tolerant stacked-device output driver with embedded SCR in Driver + SCR_50_50.. 3.4.2 ESD Robustness and TLP I-V Characteristics The HBM ESD robustness of each circuit is evaluated by the HBM tester. The failure criterion is defined as the I-V characteristics shifting over 30 % from its original curve after ESD stressed at every ESD test level. According to the measurement results, the VOUT-to-3xVDD ESD robustness of both circuits are more than 1.25kV. The GND-toVOUT ESD robustness of general stacked-device output driver (Output Driver_10 and Output Driver_30) are 0.75kV, while that of proposed stacked-device output driver with embedded SCR (Driver + SCR_10_10 and Driver + SCR_30_10) are improved to 1.75kV and 2.25kV, respectively, the GND-to-VOUT ESD robustness of general stackeddevice output driver (Output Driver_50) is 1.25kV, while that of proposed stackeddevice output driver with embedded SCR is improved to 2.50kV. All these HBM measurement results are listed in Table 3.2. 52.

(65) Table 3.2 HBM ESD robustness of test circuits HBM Level Test Circuits GND-to-VOUT. VOUT–to-3xVDD. Output Driver_10. 750V. 1250V. Output Driver_30. 750V. 1250V. Output Driver_50. 1250V. 1500V. Driver + SCR_10_10. 1750V. 1250V. Driver with. Driver + SCR_30_10. 2250V. 1250V. Embedded. Driver + SCR_50_10. 2500V. 1750V. SCR. Driver + SCR_30_30. 4000V. 3500V. Driver + SCR_50_50. 4500V. 4000V. Pure Output Driver. To investigate the turn-on behavior and the I-V characteristics of the circuits in the domain of HBM ESD event, the transmission-line-pulsing (TLP) system with a 10ns rise time and a 100ns pulse width is used. The current-handling ability, i.e. the secondary breakdown current (It2), of test circuit can be obtained from the TLPmeasured I-V curves. The TLP-measured I-V curves of test circuits are shown in Fig. 3.19 ~ 3.28. As measuring from VOUT to 3xVDD, the test circuits of Output Driver_10 and Driver + SCR_10_10 have almost the same TLP I-V characteristics, and the TLP-measured It2 are ~0.85A, the test circuits of Output Driver_30 and Driver + SCR_30_10 have almost the same TLP I-V characteristics, and the TLP-measured It2 are ~1.03A, the test circuits of Output Driver_50 and Driver + SCR_50_10 have almost the same TLP I-V characteristics, and the TLP-measured It2 are ~1.20A, the test circuits 53.

(66) of Driver + SCR_30_30 and Driver + SCR_50_50 can achieve the TLP-measured (It2) of 2.16A and 3.29A, respectively. As measuring from GND to VOUT, the embedded SCR in the proposed design can be triggered lower than ~2.5V, and then be latched to ~1.5V. The GND-to-VOUT It2 of general stacked-device output driver (Output Driver_10, Output Driver_30, and Output Driver_50) are 0.47A, 0.77A, and 1.02A, respectively, while that of proposed stacked-device output driver with embedded SCR (Driver + SCR_10_10, Driver + SCR_30_10, and Driver + SCR_50_10) are improved to 0.81A, 0.97A, and 1.26A, respectively, the test circuits of Driver + SCR_30_30, and Driver + SCR_50_50 can achieve the TLP-measured (It2) of 2.29A and 3.51A, respectively.. VOUT-to-3xVDD 1.2. Output Driver_10 Driver + SCR_10_10. TLP Current (A). 1.0. 0.8. 0.6. 0.4. 0.2. 0.0 0. 2. 4. 6. 8. 10. 12. 14. TLP Voltage (V). Fig. 3.19. Measured TLP I-V curves of Output Driver_10 and Driver + SCR_10_10, as zapping from VOUT to 3xVDD.. 54.

(67) GND-to-VOUT 1.0. Output Driver_10 Driver + SCR_10_10. TLP Current (A). 0.8. 0.6. 0.4. 0.2. 0.0 0. 2. 4. 6. 8. 10. TLP Voltage (V). Fig. 3.20. Measured TLP I-V curves of Output Driver_10 and Driver + SCR_10_10, as zapping from GND to VOUT.. Fig. 3.21. Measured TLP I-V curves of Output Driver_30 and Driver + SCR_30_10, as zapping from VOUT to 3xVDD. 55.

(68) Fig. 3.22. Measured TLP I-V curves of Output Driver_30 and Driver + SCR_30_10, as zapping from GND to VOUT.. Fig. 3.23. Measured TLP I-V curves of Output Driver_50 and Driver + SCR_50_10, as zapping from VOUT to 3xVDD. 56.



(71) Fig. 3.28. Measured TLP I-V curves of Output Driver_50 and Driver + SCR_50_50, as zapping from GND to VOUT.. In order to investigate the reliability of driver and ESD protection device, using 3 different dimensions in the output stage to collocation the different size with embedded SCR. TLP measurement results as shown in Fig. 3.29.. 59.

(72) Fig. 3.29. Measured TLP I-V curves, as zapping from GND to VOUT of driver with embedded SCR.. As measuring from VOUT to GND, the test circuits of Output Driver_10, Output Driver_30, and Output Driver_50 can achieve the TLP-measured It2 of 0.32A, 0.28A, and 0.33A, respectively as shown in Fig.3.30.. Fig. 3.30. Measured TLP I-V curves, as zapping from VOUT to GND. 60.