Abstract—Op-amps are crucial components in sigma–delta
modulators (SDMs). As device dimensions and supply voltages continue to scale down, it is increasingly critical to determine a suitable op-amp dc gain. If the dc gain is set too high, then the op-amp consumes too much power; if the dc gain is too small, then nonlinear distortion becomes serious. However, there exists no efficient approach for selecting dc gains. In this brief, we propose to use a nonlinear function to model nonlinear op-amp dc gain curves. Then, this nonlinear function is employed to derive an SDM nonlinear distortion model as a function of SDM system parameters. The obtained SDM nonlinear distortion model can subsequently be used to compute the minimum required op-amp dc gain such that nonlinear distortions are kept under a tolerable value. The nonlinear dc gain curve model and the SDM nonlinear distortion model proposed in this brief are verified by behavior simulations and transistor-level simulations.
Index Terms—Nonlinear distortion, op-amp dc gain, sigma–delta modulator (SDM).
I. INTRODUCTION
S
IGMA–DELTA modulators (SDMs) based on switched-capacitor circuits have been suitable for high-resolution applications. Recently, low-power designs have become a very important trend for SDM applications. Since op-amps consume most power in SDM, it is crucial to determine a suitable op-amp dc gain. If the dc gain is set too high, then the op-op-amp can consume too much power; if dc gain is too small, then nonlinear distortion can become serious. However, there exists no efficient and systematic approach for selecting dc gains.Currently, there are two major approaches for selecting op-amp dc gains. The first approach is ad hoc based [1]–[3], which usually suggests setting the dc gain at a sufficiently large value, e.g., 70 dB, so that nonlinear distortion can be small enough. This can be too conservative, since the dc gain can actually be smaller for certain applications. The other approach for selecting the op-amp dc gain requires intensive simulations and subsequent computations [4]–[6]. In this approach, time-consuming SPICE simulation is first used to identify the non-linear dc gain curve of a specific op-amp design, and then the magnitude of distortion is computed from the nonlinear Manuscript received April 28, 2009; revised July 9, 2009. Current version published September 16, 2009. This paper was recommended by Associate Editor P. Malcovati.
The authors are with the Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu 30050, Taiwan (e-mail: fcchen@cc. nctu.edu.tw; [email protected]).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2009.2027956
curve identified. If the computed distortion is too large or too conservative (too small), then the op-amp design has to be modified so that the dc gain can be adjusted. Then, one needs to carry out the aforementioned simulation and computation again. This iterative process would continue until a suitable dc gain is determined. Therefore, the existing approaches are either not accurate enough or not time efficient.
In this brief, we propose an accurate and efficient approach for selecting the op-amp dc gain. An essential first step in our method is the creation of a general model for nonlinear op-amp dc gain curves. The importance of this nonlinear dc gain model is that it eliminates the need for time-consuming SPICE simulations described above. Then, the nonlinear dc gain curve model can be employed to analytically derive the nonlinear distortion, which appears at the SDM output. Since the non-linear distortion model is expressed in terms of dc gain and other SDM parameters, it can be used to accurately compute the minimum required op-amp dc gain such that the nonlinear distortion is kept under a tolerable value. The nonlinear dc gain curve model and the nonlinear distortion model are verified by transistor-level simulations. Their application to SDMs is verified by behavior simulations.
II. OP-AMPNONLINEARDC GAINCURVES
A. DC Gain Distortion Can Be Severe
A second-order SDM with OSR = 20, VOS= 0.6, a 3-bit
quantizer, a 1-V sinusoidal input signal, and a relatively small dc gain AO= 50 dB will see a severe dc gain distortion at about −61 dB, which easily dominates other noises and distortions, e.g., quantization noise (−81 dB) and digital to analog converter distortion (−76 dB, without dynamic element matching), and results in a poor signal to noise plus distortion ratio at 60 dB.
B. Modeling Nonlinear DC Gain Curves
It is well known that the output resistance of op-amp output-stage transistors is dependent on the output voltage VO. This dependency results in nonlinear op-amp dc gain when VO changes, as shown in Fig. 1. A typical nonlinear dc gain curve can be approximated by the polynomial
AV(Vo) = A0
1 + q2Vo2+ q4Vo4
(1) where AV(Vo) is the nonlinear dc gain of the op-amp, and AO is the maximum dc gain when VOis in the neighborhood of 0 V.
Fig. 1. DC-gain curve versus output voltage with the rail-to-rail voltage of VDD.
Fig. 2. (a) Two nonlinear dc gain curves with identical VOSbut different AO. (b) Two nonlinear dc gain curves with similar AObut different VOS.
It is well known that the|VGSQ| of the output-stage
transis-tors and the maximum dc gain AOare the only two parameters that can affect the shape of the nonlinear curves AV(V0). It is
also well known that maximum output swing VOSand|VGSQ|
have a germane relation with each other. Since VOS makes
much more sense for practical designers, we replace |VGSQ|
by VOS, and in the rest of this brief, VOS and AO are the only two parameters that affect AV(Vo). To demonstrate the effects of VOSand AOon AV(Vo), SPICE op-amp simulations in Fig. 2(a) and (b) respectively show the effects that AO and
VOScan have on the shape of the dc gain curves.
To model the nonlinear gain AV(V0), we tried various
com-binations of AOand VOSto create a set of representative curves
for the family of nonlinear dc gain curves. Then, we endeavored to find out suitable q2and q4such that (1) can reasonably fit all
of these curves. After intensive trials and errors, we come up with q2and q4in (1) to be q2≡ −9 · A0.01 O (1 + VOS)2.6 2 (2) q4≡ −6 · A0.0001O (1 + VOS)0.83 4 . (3) Although q2 and q4 are obtained from trials and errors, the
searching and testing time for them is more than one year. We are confident that the model in (1)–(3) is sufficiently general and accurate, as is verified in the next section.
C. Verifying Nonlinear DC Gain Curve Model
Comparisons of dc gain curves from real op-amps and from our model (1)–(3) are shown in Fig. 3. The comparisons are deliberately planed to cover various op-amp structures and
rep-Fig. 3. Comparisons between op-amp nonlinear dc gain curves (solid line) from real op-amp and (dashed line) from our model.
resentative points in op-amp parameter space. The subfigures in Fig. 3 are cross related as follows.
1) Parts (a) and (c) show two-stage op-amps, and parts (b) and (d) show folded cascode op-amps.
2) Parts (a) and (b) show a large difference in the values of AO.
Fig. 5. Switch-capacitor integrator with nonlinear dc gain op-amp. (a) Sam-pling phase. (b) Integration phase.
For the four cases presented in Fig. 3, the errors between op-amp nonlinear dc gain curves from real op-op-amps and from our model range from 0.1% to 5%. This demonstrates that our model [see (1)–(3)] is sufficiently general and accurate.
III. SDM DISTORTIONDUE TO THENONLINEAR DC GAIN OF THEOPERATIONALAMPLIFIER In Section II, we analyzed the op-amp nonlinear dc gain phenomenon and obtained a nonlinear dc gain model (1)–(3). In this section, based on the model in (1)–(3), we want to derive a nonlinear distortion model for single-loop second-order SDM output distortions caused by nonlinear dc gain in op-amps. Fig. 4 shows the block diagram of an ideal SDM. We will first discuss the property of VS, which is the input to the first integrator. Then, the transfer characteristics of the integrator are analyzed, based on which the SDM nonlinear dc gain distortion model is derived. Distortion models for other SDM structures can be obtained following the approach in this section.
A. Properties ofVS
In Fig. 4, the switched-capacitor integrator input VS can be expressed as
VS(z) = (1− z−2)X(z)− (1 − z−1)2E(z) (4) which includes the signal and noise parts. The noise part can be ignored here. To analyze the signal part, with x(n) =
Ainsin(wnT ), we perform inverse z-transform in (4) and
obtain VS(nT ) = Ainsin(wnT ) − Ainsin (w(n− 2)T ) · u (w(n − 2)T ) ≈ Ain· sin 2π OSR · cos(wnT ). (5) Then, the amplitude of VS can be approximated as
|AV S|=|VS(2nT )|=|Ainsin(2wnT )| ∼= 2Ain· w · T. (6)
B. Transfer Characteristics of the First Integrator
The sampling and integration phases of a switch capacitor integrator are shown in Fig. 5. In the following discussion, signals VO((n + 1/2)T ), VO((n− 1/2)T ), and VS(nT ) will
expression: VO+−VO− = KS· 1+ 1 AO ·q2· VO+2+VO+VO−+VO−2 +q4− q22 ·VO+4+VO+3VO−1+VO+2VO−2 +VO+1VO−3+VO−4 +· · · 1 A∞O · VS (10) where KS is CS/CI. The problem with (10) is that the inte-grator output VO± also appears on the right-hand side of (10). However, since VO±can be shown to relate to VSin (5) as
VO±≈ − KS 1 + 1+KS AO · 1 4−4·KS AO · sin wT 2 · AV S· sin w n±1 2 T (11)
VO±and VSat the right-hand side of (10) can be substituted by (11) and (5), which results in
VO+− VO− = KS· 1 AO 3 4−4Ks AO · KS 1 +1+KS AO 2 · A2 V S· q2 · cot2 1.5708 OSR · sin2(wnT ) + 5 4−4KS AO 2 · KS 1 + 1+KS AO 4 · A4 V S ·q4− q22 · cot4 1.5708 OSR · sin4(wnT ) + 10 4−4KS AO 2 · KS 1 + A1 O 4 · A4 V S ·q4− q22 · cot2 1.5708 OSR · cos2(wnT ) · sin2(wnT ) + 1 4−4KS AO 2 · KS 1 + A1 O 4 · A4 V S· q4− q22 · cos4(wnT )
· {Ainsin(wnT )− Ainsin (w(n− 2)T )·u ((n−2)T )} .
Equation (12) can be used to compute the nonlinear dc gain distortions appearing at first integrator output.
C. Nonlinear DC Gain Distortions at SDM Output
It is known that if the gain of the second integrator is equal to 1, i.e., CS2/CI2= 1, then the same distortions appearing at the first integrator output would appear at the SDM output. Otherwise, some modification is needed on the distortions at the SDM output. Suppose the second integrator gain is equal to 1. Then, the third harmonic magnitude in dc gain distortions can be computed from (12) as Asin_3= KS· 1 AO · 1 16 · −12 4−4KS AO · cot2 1.5708 OSR + 4 4−4KS AO · KS 1 + 1+KS A0 2 · A2 V S· Ain· q2 + ⎡ ⎢ ⎣ −25 4−4KS AO 2·cot 4 1.5708 OSR + 10 4−4KS AO 2 · cot2 1.5708 OSR + 3 4−4KS AO 2 ⎤ ⎥ ⎦ · KS 1 + 1+KS A0 4 · A4 V S· Ain· q4− q22 · 1− cos 2π OSR (13) Acos_3= KS· 1 AO · 1 16 · ⎧ ⎪ ⎨ ⎪ ⎩ ⎡ ⎢ ⎣ −12 4−4KS AO 2·cot 2 1.5708 OSR − 4 4−4KS AO 2 ⎤ ⎥ ⎦ · KS 1 + 1+KS A0 2 · A2 V S· Ain· q2 + ⎡ ⎢ ⎣ −15 4−4KS AO 2·cot 4 1.5708 OSR − 10 4−4KS AO 2 · cot2 1.5708 OSR + 5 4−4KS AO 2 ⎤ ⎥ ⎦ · KS 1 + 1+KS A0 4 · A4 V S· Ain· q4− q22 ⎫ ⎪ ⎬ ⎪ ⎭ · sin 2π OSR . (14) TABLE I
RELATIONSHIPBETWEENEACHPARAMETER AND THEHARMONICDISTORTIONS
TABLE II
MINIMUMREQUIREDAOANDOSR
The forms for magnitudes of fifth harmonics Asin_5and Acos_5
can also be computed from (12), but are omitted here. Then, the powers of the third and fifth harmonic distortions are
HD3NFDCG(in decibels) =10 log
A2
sin_3+A2cos_3
2 (15)
HD5NFDCG(in decibels) =10 log
A2
sin_5+A2cos_5
2 . (16) The model in (13)–(16) indicates that the dc gain distortions at SDM output are related to CI, CS, Ain, AO, VOS, and
OSR. Some qualitative properties about how each parameter
can affect the distortion magnitude are obtained from (13)–(16) and listed in Table I.
Some quantitative investigation based on (13)–(16) shows that AOand OSR are the most influential parameters on SDM dc gain distortions. Therefore, an interesting example about how (13)–(16) can be utilized is that if the four parameters are fixed at Ain= 1 v, VOS= 0.8, CS = 1 pF, and CI = 2 pF, then (13)–(16) can be employed to determine the minimum AOand
OSR required so that the dc gain distortion can be kept under
a certain value. The results are tabulated in Table II.
Due to loop shaping, the dc gain nonlinearity in the second integrator degrades the performance to a much lesser extent, allowing a more relaxed design [7]. Therefore, only the dc gain distortion caused by first integrator is considered in this brief.
IV. TRANSISTOR-LEVELSIMULATIONRESULT The proposed model serves as a powerful tool for ana-lyzing the nonlinear dc gain distortion for SDMs. To verify the accuracy of our model at transistor level, the circuit of a general integrator has been realized using classical two-stage architecture in SPICE.
The specifications of the op-amp are AO= 80 dB, VOS=
±1.5 V, KS = 1, and the sinusoidal input frequency is 10 k. The integrator output fast Fourier transform (FFT) is shown in Fig. 6. The total harmonic distortion is mainly determined by the third harmonic distortion (HD3) and the fifth harmonic distortion (HD5). It is indicated in Fig. 6 that HD3 and HD5 are−56.9 and −67.3 dB, respectively, and the HD3 and HD5 generated from our model are−63.9 and −73.5978 dB, respec-tively. The theoretical and simulation results are close and listed in Table III.
Fig. 6. SPICE simulation FFT results with KS= 1, AO= 80 dB, VOS=
1.5 V, and Fin= 10 k.
TABLE III
COMPARISON OFTHEORETICRESULT ANDSPICE SIMULATION
Fig. 7. Second-order SDM behavior model with nonlinear dc gain. V. BEHAVIORMODELSIMULATIONRESULTS
A. Behavior Model of Nonlinear DC Gain
We use a calculable behavior model to verify our SDM non-linear dc gain distortion model. The z-domain transfer function of a delayed integrator of SDM is
H(z) = g· z
−1
1− α · z−1 (17) where g and α are the integrator gain and the leakage, respec-tively [8].
B. Behavior Model of SDM With Nonlinear DC Gain
Then, one can place the nonlinear dc gain behavior model in (17) into the complete SDM behavior simulation scheme. The diagram is shown in Fig. 7.
The behavior simulations are conducted for two different cases. The SDM output FFTs are shown in Fig. 8. The com-parisons between simulation results and theoretical results are shown in Table IV. The results from both simulation cases are very close to those obtained from our dc gain distortion model.
VI. CONCLUSION
In this brief, we have first derived the model for op-amp non-linear dc gain curves and then the model for dc gain distortion at SDM output. The nonlinear dc gain curve model has never been seen in the literature before. It can be useful and important for
Fig. 8. Modulator’s output power spectral density. TABLE IV
COMPARISON OFTHEORETICRESULT ANDSIMULINKSIMULATION
both industrial and academia applications. The completeness and precision of our dc gain distortion model are also new and important contributions. Both models are intensively verified by transistor-level and/or behavior simulations.
There are many different ways to apply the two models proposed in this brief, some of which have been suggested in Section III. In particular, our models will be very useful in model-based ΣΔ modulator design optimization. Behavior-simulation-based ΣΔ modulator design optimization has been reported in [9]. In comparison, model-based optimization can be much faster and provide more insights about the system under design.
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