796
Electromigration and Integration Aspects for the Copper-SiLK
System
H.S. TSENG,1BI-SHIOU CHIOU,1,3W.F. WU,1,2and C.C. HO1
1.—Department of Electronics Engineering and Institutes of Electronics, National Chiao Tung University, Hsinchu, Taiwan, Republic of China.. 2.—National Nano Device Laboratories, Hsinchu, Taiwan, Republic of China. 3.—bschiou@mail.nctu.edu.tw
In this study, the thermal characteristics and electromigration (EM) resistance of two dielectrics, SiLK™ and SiO2, are investigated to evaluate the feasibility
of low dielectric-constant SiLK for intermetal dielectric applications. Liftoff patterning was employed to fabricate the Cu interconnect for the EM test, and the Taguchi method was used in the experimental design to identify the key parameters for a successful liftoff. It was shown that the thermal impedance of the metal lines passivated with SiLK is 14% higher than that of metal lines passivated with SiO2. On the basis of the thermal impedance and temperature
rise of the interconnect, it was concluded that the major heat transfer path is via the underlayer dielectric to the Si substrate. The activation energy of EM for Cu passivated with SiLK is smaller, and the EM lifetime is shorter than that of Cu passivated with SiO2. Possible mechanisms are discussed.
Key words: Si, SiO2, Cu, electromigration, SiLK
(Received October 24, 2003; accepted February 13, 2004)
INTRODUCTION
As interconnect feature size decreases and clock frequencies increase, interconnect resistance ca-pacitance (RC) time delay and current density incre-ment become the major limitation to achieving high circuit speeds and reliability. Copper, with its high electrical conductivity and melting temperature, provides smaller RC time delay and electromigra-tion (EM) resistance than Al-based metallizaelectromigra-tion does.1–4However, the usage of a copper interconnect
poses many challenges, such as lack of a stable self-passivating oxide,5 poor adhesion of copper to the
dielectric,6difficulty in dry etching,7high diffusivity
in silicon and SiO2,8,9and deep levels in silicon.10
One of the primary problems with integrating Cu with a low-k dielectric into a multilevel metalliza-tion system is the difficulty in patterning the metal. There are several methods for patterned Cu inter-connects, such as selective electroless plating, selec-tive chemical-vapor deposition, high-temperature reactive-ion etching, and the liftoff technique.11,12
Liftoff patterning has been used here to study the integration issues of Cu and the SiLK™ system
(Dow Chemical Company, Midland, MI). SiLK is a low molecular-weight aromatic thermosetting poly-mer. The low molecular-weight polymer will flow to fill small gaps and planarize underlying topology. SiLK films are one of the most attractive interlayer dielectrics because of their good surface planariza-tion characteristics, low dielectric constant, and high toughness.13,14
In this study, direct current sputtering was em-ployed to deposit Cu films onto SiO2/Si substrates.
The Taguchi method15 was applied in the
experi-mental design to identify the key processing para-meters for the liftoff process of Cu metallization. Both SiLK and SiO2 were used as the passivation
layer of Cu, and the effects of the overlayer dielectric on the thermal characteristics and EM of copper were explored. The major focus of this work was to investigate the integration aspects of the Cu-SiLK system, including the liftoff process conditions of the Cu interconnect and reliability issues (such as heat dissipation and EM resistance) of the system.
EXPERIMENTAL PROCEDURE
Four-inch-diameter p-type (100) Si wafers with nominal resistivity of 1–10 Ω-cm were used as sub-strates. An interdigitated comb and serpentine test
structure, as shown in Fig. 1, was employed for liftoff and EM study. After standard RCA cleaning and spin drying, 500-nm thermal oxide was grown at 950°C in a steam atmosphere. Then, plasma-enhanced chemical vapor deposition (PECVD) was employed to grow 50 nm of Si3N4on top of the
ther-mal oxide. The parameters studied for the liftoff process include baking of photoresist, thickness of metal, type of barrier, room-temperature storage, os-cillation intensity, and osos-cillation time. The Taguchi method was employed to design the liftoff experi-ments. Sixty-five samples are studied for each condi-tion, and an optical microscope was used to examine whether the process was successful, i.e., whether an integral test structure was obtained. The optimum process parameters were employed in the liftoff for preparing specimens for the EM test.
The adhesion strength of Cu to the underlayer dielectric was evaluated with a direct pull tester (Sebastian Five, QUAD Group, Spokane, WA). A stud was bonded perpendicularly to the coating sur-face with epoxy by holding it in contact through a spring mounting chip designed especially for the stud. The assembly was cured at 150°C for 1 h. The stud was then put into the platen and gripped. The tester pulled the stud and samples down against the platen support ridge until the coating failed. The stress of adhesion, σa, is defined as
σa F/A. The area of A is the circular section of the
stud.
Specimens for EM tests were 250-nm Cu with a 30-nm TaN barrier. The metal film was obtained with the optimized liftoff process. After pattern delineation, wafers were passivated with 650-nm SiLK or 500-nm SiO2. The SiO2films were deposited by the
decompo-sition of tetraethyl orthosilicate with PECVD (Multi-chamber PECVD, STS-Multiplex Cluster System,
England) at 250°C and 100 mtorr. After contact hole opening, 1-µm-thick Al was deposited and pat-terned to form the contact pads. Finally, samples were annealed at 450°C for 1 h in a 100-torr N2purge
furnace.
Accelerated EM tests were carried out on a hot chuck of a probe station. The stressing current den-sity was 2.8 106A/cm2, and the ambient
tempera-ture ranged from 225°C to 300°C in air for the EM test.
RESULTS AND DISCUSSION
Figure 2 shows the photograph of the patterned interdigitated structure. A summary of the liftoff test designed with the Taguchi method is given in Table I. Among the parameters studied, employ-ment of a barrier layer appears to be a key factor to ensure successful liftoff. The barrier layer enhances the adhesion strength of the metal to the dielectric and helps in maintaining the pattern integrity dur-ing liftoff. The adhesion strength of Cu to SiO2
increases from 9.8 MPa to 37.5 MPa when a barrier layer is inserted. On the basis of the yield data shown in Table I, the optimum Cu liftoff conditions are curing the photoresist at 120°C for 3 min, using a metal thickness of 200 nm with a 30-nm TaN bar-rier layer, and using medium ultrasonic oscillation for an appropriate period of time (4 h in this study) to strip resist and liftoff the metal.
The joule heating induced by power consumption will raise the temperature of the interconnect and integrated circuit chips. The average temperature increase,∆T, in the Cu interconnect caused by joule heating is shown in Fig. 3. The ∆T of Cu passivated Fig. 1. Test structure for liftoff and EM study.
with SiLK (Cu-SiLK) is larger than that of Cu passi-vated with SiO2 (Cu-SiO2) especially at higher
cur-rent density. The temperature rise caused by joule heating is determined by measuring the temperature coefficient of resistance (TCR):16
(1) where R1, R2, and RTare the resistance at
tempera-tures T1, T2, and T (T is normally taken as 20°C),
respectively. Therefore, the average temperature rise in the interconnect is
(2) The TCRs of Cu-SiO2and Cu-SiLK are 3.22 103
C1and 3.21 103C1, respectively. The thermal conductivity of SiLK (1.9 103 W/cm-°C) is one eleventh of that of silicon dioxide (2.09 102 W/cm-°C).13The temperature rise induced by joule
heating is dissipated both through the underlayer insulator dielectric to the Si substrate, which acts as a heat sink, and through the overlayer passivation dielectric, as shown schematically in Fig. 4.
Table I. Summary of the Liftoff Test
Metal 25°°C Oscillation
Test Conditions Baking of Thickness Barrier Storage Oscillation Time Yield*** Test Run Photoresist* (nm) Layer (Days) Intensity** (Hour) (%)
1 Y† 200 N‡ 0 S 2 0 2 Y 250 Ta 2 M 4 9 3 Y 300 TaN 7 W 8 25 4 N‡ 200 N 2 M 8 0 5 N 250 Ta 7 W 2 6 6 N 300 TaN 0 S 4 28 7 Y 200 Ta 0 W 4 9 8 Y 250 TaN 2 S 8 51 9 Y 300 N 7 M 2 0 10 Y 200 TaN 7 M 4 66 11 Y 250 N 0 W 8 0 12 Y 300 Ta 2 S 2 3 13 N 200 Ta 7 S 8 3 14 N 250 TaN 0 M 2 38 15 N 300 N 2 W 4 0 16 N 200 TaN 2 W 2 51 17 N 250 N 7 S 4 0 18 N 300 Ta 0 M 8 0
*The photoresist used is TMHR iP-3650 from TOK Co., Japan; the baking is at 120°C for 3 min.
**The ultrasonic oscillation to lift the photoresist off. S: strong (~200 Watt), M: medium (~170 Watt), W: weak (~140 Watt). ***The sample size is 65.
†y is with baking.
‡N is without baking or barrier layer.
TCR T R R RT T T ( ) ( ) = − × − 1 2 1 2 ∆T T T R R TCR T RT = − = − × 1 2 1 2 ( )
Fig. 3. The average temperature increments of the Cu interconnect as a function of current density. Ambient temperature: 30°C;■: Cu
The difference in ∆T between SiLK and Cu-SiO2is not very significant. At a current density of
3 106A/cm2,∆T for Cu-SiLK and Cu-SiO
2are 3°C
and 2°C, respectively, as shown in Fig. 3. This suggests that most heat dissipated through the un-derlayer dielectric to the Si heat sink (substrate); hence, although thermal conductivity of SiLK and SiO2 differs by an order of magnitude, not much
difference is observed between the temperature rise of ∆T of Cu passivated with SiLK and that of Cu passivated with SiO2. Previous work indicates
that when using an underlayer dielectric with poor thermal conductivity, the joule heating could cause a huge temperature rise at the intercon-nects and, hence, accelerate the EM damage and, finally, lead to catastrophic interconnect failure as well as thermal decomposition of the underlayer
dielectric.1The thermal impedance,θ
j, is defined by
the expression:17
∆T P θj (3)
where P is the power input of the interconnect. The θj
of the Cu-SiLK specimen is 1,832°C/W, which is 14% higher than that of Cu-SiO2(1,604°C/W), as shown
in Fig. 5. As one compares the thermal impedances obtained in this study to those of a previous work that studied the effect of the underlayer dielectric on the thermal characteristics of the interconnect,1it is concluded that the thermal conductivity of the un-derlayer dielectric plays a crucial role in heat dissi-pation because most heat dissipated through the un-derlayer dielectric to the Si substrate, which has a larger thermal conductivity (6.28 101W/cm-°C) as compared to the dielectric. In the previous work, polyimide and SiO2were used as the underlayer
di-electric. The thermal conductivity of SiO2 is about
20 times that of polyimide (1.05 103 W/cm-°C). The thermal impedance of Cu on SiO2 and Cu on
polyimide are 234°C/W and 736°C/W, respectively, as compared to 1,604°C/W (Cu-SiO2) and 1,832°C/W
(Cu-SiLK) in this study. Besides, a temperature rise (∆T) of over 600°C was observed in the Cu on the polyimide system and caused the decomposition of the polyimide underlayer. In this study, the differ-ence in ∆T between Cu with different passivation layers is not as significant as that with different underlayers, and the magnitude of ∆T (i.e., 3°C (Cu-SiLK) and 2°C (Cu-SiO2)) is small. Hence, the
thermal conductivity of the passivation dielectric is not as crucial as that of the underlayer dielectric in respect to degradation induced by thermal stress.
The relative resistance, R/R0, as a function of time
at various temperatures is exhibited in Fig. 6. The Fig. 5. Temperature increment versus input power of Cu
intercon-nects with SiO2or SiLK passivation.
Fig. 6. Relative resistance as a function of current stressing time at various temperatures of Cu passivated with (a) SiO2and (b) SiLK. Current
density: 2.8 106A/cm2.
resistance increases more rapidly at higher soaking temperature. By defining a resistance change of 4.5% as the criterion of early stage failure, i.e., assuming the dimensions of the maximum voids are much less than the line width, the time rate change of electrical resistance, dR/dt, caused by EM damage is thermally activated and can be expressed by the following empirical equation:18
(4) where R0is the initial resistance at a given
temper-ature, A is a pre-exponential factor, Jnis the electron
current density raised to the nth power, T is temper-ature, and Q is the activation energy for EM. The ac-tivation energy can be obtained from the ln[(dR/dt) (1/R0)] versus 1/T plot shown in Fig. 7. As can be
seen from Figs. 6 and 7, both the time to failure and activation energy for EM of Cu-SiLK are smaller than those of Cu-SiO2. There are several possible
causes that could result in shorter EM lifetime and smaller activation for EM of Cu-SiLK as compared to Cu-SiO2. One is the smaller thermal conductivity
of SiLK, which causes a larger temperature gradient and accelerates the EM process.
The residual stress of the Cu film, resulting from the thermal expansion mismatch between the cop-per and the passivation layer, could also affect the EM process, the residual stress can be estimated as follows:
σ E(αp αCu)(T T0) (5)
where E is the Young’s modulus of the Cu film (11,252 kg/mm2), and α
pand αCuare the coefficients
of thermal expansion (CTE) of the passivation layer and Cu, respectively. The term To is the annealing
temperature (450°C), and T is testing temperature (225–300°C). The CTE of Cu, SiLK, and SiO2 are
16.5 ppm/°C, 66 ppm/°C, and 0.5 ppm/°C, respec-tively.13,19 Hence, SiLK exerts a compressive stress
of 83.54–125.32 kg/mm2 (300–225°C), while SiO 2
has a tensile stress of 27.01–40.51 kg/mm2 (300–
225°C). Previous works suggest that the presence of high compressive stress would enhance EM resis-tance.20,21 However, in this study, samples passi-vated with SiLK (presumably under compression) have shorter lifetimes than those passivated with SiO2(presumably under tension). A similar
phenom-enon was observed on Cu passivated with various polyimide films.22It is probably due to the
viscoelas-tic behavior of the polyimide and/or that at the test-ing temperature; the polymer flexes and relieves some of the stress present in a test line. Hence, the effect of the compressive stress on the EM resistance is not appreciable.
Table II summarizes the failure time and failure time ratio of Cu films stressed at 2.8 106 A/cm2 and various temperatures. The ratio of the failure time (tSiLK/tSiO2) between Cu passivated with SiLK
(tSiLK) and Cu passivated with SiO2(tSiO2) decreases
as temperature increases. The atomic diffusivity, D, of copper for passivated samples can be expressed as follows:23,24
D D0exp(Q/kt) D0exp[(Em fΩ)/kT] (6)
where f is the constrain force provided by passiva-tion,Ω is the atomic volume, and Em is the
activa-tion energy for diffusion. The Young’s modulus of SiO2 and SiLK are 72 GPa and 2.45 GPa,
respec-tively.13 The more rigid SiO2 exerts a larger
con-strain force on the metallization and retards the diffusion of the metal atoms. Hence, the lifetime for SiO2-passivated samples is longer than that of
SiLK-passivated ones. Besides, it is argued that at higher temperatures the polymer relaxes more, the constrain force decreases diffusion of Cu faster, and consequently, the tSiLK/tSiO2ratio decreases with the
increase of temperature.
CONCLUSIONS
The employment of a barrier layer appears to be a key factor to ensure a successful liftoff for Cu inter-connects because the barrier enhances the adhesion strength of metal to the dielectric and helps in maintaining the pattern integrity during liftoff. The thermal impedance of Cu interconnects passivated with SiLK (Cu-SiLK) is about 14% higher than that of Cu passivated with SiO2 (Cu-SiO2). Besides, the dR dt R AJ Q kT n × 1 = − 0 exp[ ]
Fig. 7. The ln[(dR/dt)(1/R0)] versus 1/T and activation energy, Q, for
Cu films passivated with SiO2(■) or SiLK (▲) during EM test. Current
density: 2.8 106A/cm2.
Table II. Failure Time and Failure Time Ratio of Cu Films Stressed at 2.8 106A/cm2and Various
Temperatures Temperature t*SiO2 t*SiLK
(°°C) (105s) (105s) t SiLK/tSiO2 225 5.59 4.18 0.75 250 3.10 2.09 0.67 275 1.58 1.05 0.66 300 0.54 0.29 0.54
*The terms tSiO2and tSiLKare time to failure for Cu films
difference in joule-heating-induced temperature increase, ∆T, between Cu-SiLK and Cu-SiO2 is not
significant. This suggests that most heat dissipated through the underlayer dielectric to the Si sub-strate, which acts as a heat sink. Hence, the thermal conductivity of the passivation dielectric is not as critical as that of the underlayer dielectric in re-spect to thermal-stress-induced degradation. The EM resistance and lifetime of SiLK-passivated Cu is poorer than those of the SiO2-passivated one. This is
attributed to the small thermal conductivity and low rigidity of the SiLK dielectric.
ACKNOWLEDGEMENTS
This work is sponsored by the National Science Council, Taiwan, under Contract Nos. NSC91-2216-E-009-023 and NSC 92-2216-E009-007.
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