Abstract—Drain current degradation in HfSiON gate dielectric
nMOSFETs by positive gate bias and temperature stress is in-vestigated by using a fast transient measurement technique. The degradation exhibits two stages, featuring a different degradation rate and stress temperature dependence. The first-stage degrada-tion is attributed to the charging of preexisting high-k dielectric traps and has a log(t) dependence on stress time, whereas the second-stage degradation is mainly caused by new high-k trap creation. The high-k trap growth rate is characterized by two tech-niques, namely 1) a recovery transient technique and 2) a charge-pumping technique. Finally, the effect of processing on high-k trap growth is evaluated.
Index Terms—HfSiON, positive bias temperature
instabil-ity (PBTI), transient measurement, trap generation, two-stage degradation.
I. INTRODUCTION
H
IGH-DIELECTRIC-CONSTANT (high-k) materialshave emerged as a replacement for SiO2 as gate
dielec-tric in CMOS devices [1] to boost device drivability (due to a smaller effective oxide thickness) or to alleviate gate leak-age current while keeping comparable device performance. Among various high-k gate dielectrics, Hf-based silicates (e.g., HfSiON) are considered to be the most promising and have been successfully integrated into CMOS devices for low-power applications with good reliability, comparable mobility to SiO2, and greatly reduced gate leakage current [2].
The reliability issues concerning high-k gate dielectrics include stress-induced leakage current (SILC) [3], dielectric breakdown (BD) [4]–[8], and bias temperature stress-induced threshold voltage instability (BTI) [9]–[13]. Crupi et al. con-cluded that SILC imposes no reliability constraint at room temperature in high-k devices [3]. Degraeve et al. indicated that high-k dielectric traps at shallow and deep energies are respec-tively responsible for Vthysteresis and SILC and that low stress gate voltage induces no degradation in high-k dielectrics due to energy loss in trap-assisted conduction [4]. They also claimed that charge-to-breakdown (QBD) in high-k gate dielectrics is
Manuscript received September 15, 2005; revised February 22, 2006. This work was supported by the National Science Council under Contract NSC93-2215-E009-032. The review of this paper was arranged by Editor G. Groeseneken.
C.-T. Chan, C.-J. Tang, and T. Wang are with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.
H. C.-H. Wang and D. D. Tang are with Taiwan Semiconductor Manufactur-ing Company, Hsinchu 300, Taiwan, R.O.C. (e-mail: twang@cc.nctu.edu.tw).
Digital Object Identifier 10.1109/TED.2006.874160
extrapolated to be virtually infinite at low stress voltages. More-over, a thermochemical model with leakage current acceleration was proposed for high-k dielectric BD in [8].
Unlike SiO2CMOS where negative bias temperature
insta-bility (NBTI) in pMOSFETs is considered to be a dominant reliability constraint [14], positive bias temperature instability (PBTI) in high-k nMOSFETs actually dictates device lifetime [15]. PBTI in HfSiON nMOSFETs arises from trap charging and creation in the high-k layer [9]–[13]. Various PBTI models have been proposed to explain the evolution of the Vt shift, although the measured results in literature are not consistent. For example, Zafar et al. found that PBTI-induced Vt shift increases with a stretched exponential dependence on stressing time and is saturated after prolonged stressing. In their model, they assumed that high-k traps have a continuous distribution in cross sections to derive the observed time dependence. Creation of additional high-k traps during stressing is ignored, and the Vt shift is solely due to trapping of electrons in preexisting high-k traps. On the other hand, Shanware et al. showed that the Vt shift has a log-time dependence and no saturation. They attributed the Vt shift to electron tunneling into high-k traps with a continuous distribution in space and also could explain the log-time dependence. Nevertheless, they ignored trap creation during stressing, too.
In this paper, we use a fast transient technique to characterize PBTI-induced drain current degradation. With this measure-ment setup, we are able to monitor the drain current evolution over seven decades of time (from 10−3to 104 s). We find that the drain current degradation exhibits two stages. The first stage has a log-time dependence, whereas the second stage follows a power-law dependence on stress time. The onset time of the second stage is related to stress voltage, stress temperature, and device process condition. To characterize high-k trap growth rate, a recovery transient technique is developed [16], [17]. We also perform charge-pumping (CP) measurement for compari-son. The impact of process effect on the two-stage degradation behavior is discussed.
II. EXPERIMENTAL
The gate stack in our measured devices consists of a poly-Si gate electrode, Hfpoly-SiON as the high-k layer with physical thickness of 2.5 nm, and a 1.3-nm-thick interfacial SiO2layer.
The transistors have an equivalent oxide thickness (EOT) of 1.8 nm, a gate length of 0.08–100 µm, and a gate width of
Fig. 1. (a) Setup for fast transient measurement. The high-speed switches minimize the transition delay down to microseconds between stress and drain current measurement. (b) Pulses applied to gate and drain for stress and mea-surement. The measurement time is chosen on a log-time base. The measure-ment condition is Vg,meas= 1.2 V, Vd,meas= 0.2 V, and tmeas= 50 µs.
0.16–100 µm. Detailed process conditions and device charac-teristics can be found in [2], [15].
Conventionally, BTI characterization is carried out by peri-odically interrupting stress to measure device electrical param-eters such as Vt or drain current (Id) degradation. A delay as long as a few seconds is introduced as a result of switch-ing between stress and measurement. Inasmuch as poststress HfSiON CMOS exhibits a large recovery effect in the milli-second range, the above delay will significantly underestimate the degradation and may lead to an erroneous interpretation [12], [16], [18]. Therefore, throughout this paper, a transient measurement technique illustrated in Fig. 1(a) is employed to measure PBTI-induced drain current degradation [12], [16]. The computer-automated transient measurement system con-sists of high-speed analog switches, an operational amplifier, and a digital oscilloscope. The high-speed switches minimize the switching delay down to microseconds. Id rather than Vt is monitored because measurement of Vt requires a sweep in Vg, thus requiring a longer measurement time. The wave-forms applied to the gate and drain are depicted in Fig. 1(b). Measurement phase is inserted into stress phase on a log-time base. The measurement bias is Vg/Vd= 1.2 V/0.2 V, and the measurement time (tmeas) is chosen to be 50 µs such that it is
long enough for integrating reliable signals and short enough to avoid introducing additional stress.
III. RESULTS ANDDISCUSSION
A. Two-Stage Degradation
As shown in Fig. 2, the drain current degradation initially evolves relatively slowly. After a certain stress time, denoted by
Fig. 2. Linear drain current degradation measured at Vg/Vd= 1.2 V/0.2 V.
The PBTI stress is at Vg= 2.2 and 2.4 V and T = 100◦C. The onset time
of the accelerated degradation is denoted by τc(corner time). The first-stage
degradation is before τc, whereas the second stage is after τc.
Fig. 3. Drain current degradation rate: (a) in the first stage and (b) in the second stage. The second-stage degradation is obtained by subtracting the extrapolation of the first-stage degradation from the measured Iddegradation.
τc in Fig. 2, accelerated degradation is observed. The accel-eration was also observed in literature [11, Figs. 4 and 5], whereas the authors attributed the imperfect log-time depen-dence to a nonuniform initial trap distribution. The drain current degradation versus stress time before τc (“the first stage” here-after) and after τc (“the second stage”) is plotted in Fig. 3(a) and (b), respectively. The stress conditions are Vg= 2−2.4 V and T = 100 ◦C. The second-stage degradation is obtained by subtracting the extrapolation of the first-stage degradation from the measured Id degradation. Notably, the first-stage Id degradation [Fig. 3(a)] has a log(t) dependence, whereas the second-stage Id degradation [Fig. 3(b)] exhibits a power-law time dependence with a power factor of 0.35 without regard
Fig. 4. Stress temperature effect on Id degradation at Vg= 1.8 V. A
crossover of the Iddegradation at T = 25◦C and 125◦C is noticed.
Fig. 5. Corner time τcversus stress Vg at T = 25◦C and 125◦C. The Id
degradation is driven into the second stage earlier (a smaller τc) at higher stress Vgand temperature.
to stress Vg. Stress temperature effect is also characterized in Figs. 4 and 5. Three points are worth noting.
1) At a higher stress temperature, the Iddegradation enters the second stage earlier or a smaller τc.
2) The first-stage current degradation has negative stress temperature dependence, i.e., a smaller drain current degradation at a higher stress temperature. Nevertheless, the second stage shows an opposite trend, a positive temperature effect. A crossover of the drain current degra-dations at T = 25 ◦C and 125 ◦C is noticed (Fig. 4). The opposite temperature dependence implies that the dominant degradation mechanisms in the first and second stages are different.
3) The degradation is driven into the second stage earlier at a higher stress Vg. For example, the corner time is around 10 s for Vg= 1.8 V and 1 s for Vg = 2.2 V in Fig. 5.
B. Degradation Model
The log(t) degradation rate in the first stage suggests that charging [11] and concomitant discharging [12] of preexisting high-k traps dominate the first-stage Id degradation. A higher
Vg induces a larger electron density in the inversion channel readily for trapping, thus causing a more severe Iddegradation. The negative temperature dependence can be explained as fol-lows. Inasmuch as the high-k charge detrapping rate increases with temperature [12], a higher temperature results in a smaller
Fig. 6. Characterization procedure of two high-k trap density extraction methods. (a) Drain current recovery transient technique. (b) Two-frequency CP technique.
net charge trapping rate and thus a smaller drain current degra-dation. On the other hand, new high-k traps are created during stress. At a certain stress time (the aforementioned “corner time”), the additionally created high-k trap density reaches a level comparable to or even more than preexisting ones. Charging and discharging of the preexisting traps are then no longer the limiting process. Thus, the drain current degradation is dictated by trap generation, which exhibits a power-law stress-time dependence [5]. Furthermore, larger stress Vg and higher temperatures lead to faster high-k trap generation in the second stage (Figs. 2–4) because of larger carrier fluence and energy [4], [5] and thus an accelerated thermochemical reaction for trap creation [8]. As a result, the device Id degradation is driven into the second stage earlier (or a smaller τc) at higher stress Vgand/or temperature.
C. High-k Trap Growth Rate
To characterize high-k trap growth, two techniques are em-ployed, namely 1) a recovery transient technique [16], [17] and 2) a CP technique [5]. The characterization procedure of these two techniques is shown in Fig. 6. The devices are first subject to PBTI stress followed by a discharging step to empty the high-k traps. The discharging step is necessary or the residual trapped charges generated by PBTI stress would detrap during the recovery transient or CP measurement, giving rise to incorrect results.
1) Recovery Transient Technique: After the discharging, a moderate Vg (= 1.2 V) is applied for 0.2 s to fill high-k traps with electrons, and the drain current is measured at Vg/Vd= 0.25 V/0.1 V immediately after the filling. Fig. 7 shows the drain current recovery transients in a fresh device, after 1-s stress, and after 2000-s stress. The device dimension is W/L = 100 µm/0.08 µm. A large transient in the millisecond range is observed, suggesting an underestimate of the stress effect from conventional measurement. All curves in Fig. 7 have log(t)
Fig. 7. Drain current recovery transients measured at Vg/Vd=
0.25 V/0.1 V for different PBTI stress times: t = 0, 1, and 2000 s. Device dimension is W/L = 100 µm/0.08 µm.
Fig. 8. Energy band diagram illustrating high-k trapped charge detrapping during drain current recovery transient.
dependence. The recovery rate (i.e., the slope in Fig. 7) at t = 1 s is about the same as in the fresh device and increases considerably at t = 2000 s. Our previous study has shown that the drain current recovery is caused by detrapping of charges spatially distributed in the high-k layer [16], [17]. Concerning a high-k trapped charge at a distance x from the HfSiON/SiO2
interface, as illustrated in Fig. 8, the charge tunneling emission time can be written as
τ (x) = A exp(αkx) (1)
where the prefactor A is a function of trap cross section, recovery Vgand temperature, thickness of the interfacial SiO2,
and the HfSiON/SiO2conduction band offset [17], and
αk=
22m∗kqEt
(2)
with m∗k as the electron effective mass in the high-k layer and Etas the trap energy. The threshold voltage shift as a result of high-k trapped charge emission thus can be approximated as
∆Vt(t) = x 0 qNV HK(x, 0) εHK (THK− x) × {1 − exp [−t/τ(x)]} dx ∝ qNHKV THK εHKαk log(t) (3)
Fig. 9. High-k trap density versus stress time from the recovery transient technique. The trap density is normalized to the initial high-k trap density.
where NHKV is the volumic trap density in the high-k gate di-electric, εHKis the dielectric constant, and THKis the thickness
of the HfSiON layer. Other variables have their usual defini-tion. The corresponding drain current change is then readily obtained as
∆Id(t)∝ Gm∆Vt(t)∝
qNHKV THK εHKαk
log(t) (4)
where Gm= dId/dVg is obtained from measurement. In the above equation, the slope of the ∆Id− log(t) plot is lin-early proportional to the high-k trap density. Therefore, we can extract the high-k trap density from the recovery slope, and the result is shown in Fig. 9. Our result shows that the high-k trap density in the first stage (τc∼ tens of seconds) is dominated by preexisting traps. The high-k trap density, however, increases drastically in the second stage. Moreover, as reported in our earlier paper [12], [16], individual electron detrapping from the high-k dielectric can be observed directly in a small-area device, which is manifested by a staircase evolution of the recovery drain current rather than a continuous log(t) increase with time. Fig. 10 compares the prestress and poststress recovery drain current evolutions in a small-area device (W = 0.16 µm, L = 0.08 µm). Each current jump in the current evolution accounts for a single charge detrapping. Apparently, the poststress device has more current jumps in the same measurement period than the prestress device (from one jump in a fresh device to five jumps after 100 s stress). This result, again, provides evidence of high-k trap generation during PBTI stress.
2) CP Technique: We also characterize high-k trap gener-ation by using a two-frequency CP method. The experimental procedure is described in Fig. 6(b). The PBTI stress condition is identical to that used in Fig. 6(a). The high-k trap density is obtained from the difference between CP results at two frequencies, i.e., NHK= 1 W Lq (ICPat 2 kHz) 2 kHz − (ICPat 1 MHz) 1 MHz . (5) Note that NHK in the above equation denotes the number of
traps per unit area. The choice of 2 kHz as the lower CP mea-surement frequency is somewhat arbitrary, and NHK reflects
only the relative high-k trap density. Fig. 11 shows normalized high-k trap growth in various stress conditions. A larger stress
Fig. 10. Drain current recovery transient in a small-area device with W/L = 0.16 µm/0.08 µm. (a) Fresh device where only one current jump appears. (b) After stress at Vg= 3 V, T = 100◦C for 100 s, five current jumps are
observed in the same measurement interval. The increase in the number of current jumps indicates new high-k trap generation.
Vg [Fig. 11(a)] and/or a higher stress temperature [Fig. 11(b)] result in a larger trap generation rate and drive the device into the second stage earlier. This is consistent with Fig. 5. Fig. 12 compares the high-k trap density measured from the recovery transient technique and from the CP technique. NHKV from the recovery slope method is multiplied by the thickness of the high-k layer in Fig. 12. Note that the areal high-k trap density extracted from the CP method is about three times lower than that from the recovery transient technique. The reason is that high-k dielectric traps are distributed in space. The inverse of the frequency used in CP measurement determines the depth into the high-k dielectric the electron tunneling front can reach. Thus, only high-k traps that has a tunneling time shorter than the inverse of the CP frequency can contribute to the CP current. In other words, only a small portion of high-k dielectric traps can be detected by the CP method. Despite the absolute value of the trap density, the trap growth rate from the two methods follows the same power-law time dependence with an exponent of∼ 0.33, which is close to that in Fig. 3(b).
D. Process Effect
Appropriate nitrogen incorporation into Hf-silicate can sub-stantially improve the gate dielectric electrical reliability [15]. To evaluate the nitrogen effect on HfSiON nMOSFET degra-dation, two devices, i.e., “optimal” versus “control,” which have different nitrogen profiles in the HfSiON gate dielectric, are compared. The high-k film in the optimal sample remains amorphous, whereas that in the control becomes crystallized after 1100◦C annealing of source/drain dopant activation [15].
Fig. 11. High-k trap density versus time from the CP technique. The trap density is normalized to the initial high-k trap density. (a) Stress temperature = 25◦C. (b) Stress voltage = 2 V.
Fig. 12. Generated high-k trap density versus stress time from the recovery transient and the CP techniques. The stress condition is Vg= 2.2 V and T = 25◦C.
The time-to-breakdown, hot carrier, and PBTI lifetime are improved, with other parameters such as Vtand gate leakage current not adversely affected. High-k bulk trap generation is suppressed in the optimal samples. Detailed comparisons and discussions are summarized in [15]. The two devices have almost identical Id−Vg characteristic, as shown in the inset of Fig. 13. After PBTI stress, the normalized trap density from the CP method for these two samples is shown in Fig. 13. A large trap density difference between high- and low-frequency CP measurements in the control sample suggests considerable high-k trap creation during stress. On the other hand, the optimal device shows better robustness against high-k trap generation. Correspondingly, Fig. 14 shows the drain current degradation versus stress time in the two samples. Again, the optimal device shows smaller degradation. We also evaluate
Fig. 13. Normalized trap density versus CP measurement frequency in the control and optimal samples. PBTI stress condition is Vg= 2.2 V and T =
125◦C. The prestress Id−Vgcharacteristics in the control and optimal samples are shown in the inset.
Fig. 14. Comparison of Id degradation in the two samples. The optimal
nitrogen incorporation sample shows lower initial trap density and better stress immunity.
Fig. 15. Stress temperature effect on Id degradation rate in the optimal
sample. The crossover is still observed, indicating the existence of two-stage degradation in the optimal sample.
the stress temperature effect in the optimal sample (Fig. 15). Opposite temperature dependence between the first stage and the second stage is still observed. The crossover time in the sample is about 104s, much longer than∼ 20 s in the control sample.
IV. CONCLUSION
HfSiON gate dielectric nMOSFETs exhibit two-stage drain current degradation in PBTI stress. The first-stage drain current degradation is attributed to the charging of preexisting high-k
ering both degradation stages.
ACKNOWLEDGMENT
The authors would like to thank Taiwan Semiconductor Manufacturing Company (TSMC/NCTU JDP program) for the technical support.
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Chien-Tai Chan (S’00) was born in Taoyuan,
Tai-wan, R.O.C., in 1978. He received the B.S. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 2000. He is currently working toward the Ph.D. degree at the same university.
His research interests include electrical characteri-zation and reliability study of high-k gate dielectrics and trapping storage memory devices.
Mr. Chan is the recipient of the Best Student Paper Award for the 2005 Symposium on VLSI Technol-ogy and the Best Paper Award in reliability for the 2004 IPFA. He is also the recipient of the 2003–2004 Chung Hwa Rotary Educational Foundation Scholarship, Taiwan.
Chun-Jung Tang was born in Tainan, Taiwan,
R.O.C., in 1982. He received the B.S. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 2004. He is currently working toward the Ph.D. degree at the same university.
His research interests include electrical charac-terization and reliability models in high-k CMOS devices.
Dr. Wang has served as Technical Committee Member of many international conferences, among them IEDM, IRPS, and VLSI-TSA. He was an Invited Speaker at the 2003 IEDM on the topic of nitride Flash reliability. He was granted the Best Teaching Award by the Ministry of Education, Taiwan, R.O.C.
Howard C.-H. Wang received the B.S. and Ph.D.
degrees in electronic engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1992 and 2002, respectively.
He joined Taiwan Semiconductor Manufacturing Company (TSMC) in 1995, where he was initially responsible for process integration for 0.5 and
0.6-µm technology. Between 1997 and 2002, he was
involved in the device design (front-end integration) for 0.18-µm, 0.15-µm, 0.13-µm, and 90-nm technol-ogy in the Advanced Device Technoltechnol-ogy Department at TSMC. Since 2002, he has been a Manager in the Exploratory Technology Development-1 Department under the supervision of Dr. C. Hu. He is currently working on the development of high-k gate dielectric, metal gate, and strained-Si technologies for sub-65-nm node CMOS device technology. He has authored or coauthored 15 papers in technical journals and conferences. He is a holder of 13 U.S. patents.
Dr. Wang is a member (2004, 2005) of the CMOS Devices Subcommittee for the IEDM.
Denny D. Tang, photograph and biography not available at the time of
