A-68.5 dB IM3 Low-Voltage CMOS Transconductor with Wide Tuning Range

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(1)IEICE TRANS. FUNDAMENTALS, VOL.E93–A, NO.8 AUGUST 2010. 1556. LETTER. A −68.5 dB IM3 Low-Voltage CMOS Transconductor with Wide Tuning Range Tien-Yu LO† , Nonmember, Chung-Chih HUNG†a) , Member, and Chi-Hsiang LO†† , Nonmember. SUMMARY A CMOS transconductor for multi-mode application is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier, which operates in the weak inversion region, provides a wide transconductance tuning range without degrading the linearity. The transconductor was designed and fabricated in the TSMC 0.18-μm CMOS process. The results show the transconductance tuning ratio of 23 and the IM3 performance of −68.5 dB. key words: transconductor, IM3, CMFF, tuning. 1.. Introduction. A circuit that converts the voltage applied to the input terminals into current at output nodes is generally referred as a voltage-to-current converter or a transconductor. The transconductor is a basic building block in analog VLSI applications, including continuous-time Gm-C filters, voltage controlled oscillators and continuous-time delta-sigma modulators [1], [2]. The transconductance would be an important parameter to the resonant frequency of these applications. Also, the linearity of the voltage-to-current should be maintained owing to the open loop design in the applications. The Recent trend in system-on-a-chip solutions is to include multiple applications in a high-integration system. Therefore, cost efficiency of VLSI implementations has been greatly enhanced with the emergence of multi-mode technology. To meet different specifications in multi-mode technology, new basic analog building blocks should be designed. Therefore, the transconductor requires a wide tuning range for multi-mode technology, and the linearity should be well maintained. 2.. Proposed Transconductor Circuit and Performance. The transconductor using triode region transistors have been reported in the past decade [3]–[5]. The transconductance is proportional to the Klin VDS , where Klin is the device parameter of input transistors and VDS is the drain-to-source voltage. However, these circuits behave limited tuning range Manuscript received August 11, 2009. Manuscript revised March 19, 2010. † The authors are with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan. †† The author is with the Department of Electronic Engineering, National Ilan University, Ilan, Taiwan. a) E-mail: cchung@mail.nctu.edu.tw DOI: 10.1587/transfun.E93.A.1556. and require extra common-mode feed-forward (CMFF) circuit. Figure 1 shows the proposed transconductor circuit. The voltage-to-current conversion is composed of transistors M1 to M6, M17 and M18. The conversion is designed based on the flipped voltage follower (FVF) [6], which is composed of transistors M5 and M6. The main voltage-tocurrent conversion is provided by transistors M1 and M2 in the linear region. The gate voltage of transistor M5 is used to provide a bias voltage for transistors M3 and M4, and ensure the linear region operation of transistors M1 and M2. Thus, the drain voltage of transistors M1 and M2 would be kept to a constant value. In the circuit, the input transistors operate in the linear region, rather than the saturation region proposed in [6]. Besides, the source of transistors M1 and M2 is fixed to a constant value owing to the FVF feedback loop. From analysis, it is shown that the low impedance can be obtained at the source of transistor M6. The structure suppresses the variation at the source of transistors M1 and M2, and thus the circuit would operate under class AB topology. To obtain the voltage-to-current characteristic of our proposed circuit, the input differential voltages at the gate of transistors M1 and M2 can be written as Vi+ = Vcm + (vd /2) and Vi− = Vcm − (vd /2), where Vcm is the input commonmode voltage and vd is the input differential-mode voltage. The currents which flow through transistors M1, M2, and M6 are expressed by vd 1 2 ID1 = K1 Vcm + −Vth −VX (VD1 −VX )− (VD1 −VX ) (1) 2 2 vd 1 2 ID2 = K2 Vcm − −Vth −VX (VD2 −VX )− (VD2 −VX ) (2) 2 2 1 (3) Ib = K6 (Vcm − VX − Vth )2 2 where VD1 and VD2 are the drain voltages of transistors M1 and M2, respectively, and V x is the source voltage of transistor M6. The aspect ratios of transistors M1, M2, and M6 are set to the same value. In addition, the aspect ratios of M3 and M4 are twice the aspect ratios of M1 and M2. Note that VD1 = VGS 5 − VGS 3 and VD2 = VGS 5 − VGS 4 . We assume VGS 5 would be very close to VGS 6 since transistors M1 and M2 work in the linear region and a small drain current is produced. Moreover, a slightly larger aspect ratio of transistor M5 can be designed to support this assumption. VGS 3 and VGS 4 could be obtained by using the square law equation of saturated transistors. Therefore,. c 2010 The Institute of Electronics, Information and Communication Engineers Copyright .

(2) LETTER. 1557. Fig. 1. The implementation of the proposed transconductor circuit.. VD1 = VGS 6 − VGS 3 = (2Ib /K)1/2 − (ID1 /K)1/2 and VD2 = VGS 6 − VGS 4 = (2Ib /K)1/2 − (ID2 /K)1/2 . Also, from (3), Vcm − VX − Vth = (2Ib /K)1/2 and VX = Vcm − Vth − (2Ib /K)1/2 . By inserting these results into (1), with only one variable ID1 left in the equation, ID1 can be solved and obtained. Similarly, ID2 can be solved from (2) as well. The currents ID1 and ID2 would be a function of the input differential voltage. To analyze the linearity of the output current iout = ID1 − ID2 against the input voltage under the differential structure, a Taylor series expansion has been used, where the relationship could be summarized by. 3 (β − 2α)3 α (6) 2 (β − α) β2 − 2αβ − α2 3 2Ib and β = Vcm −Vth where K1 = K2 = K6 = K, α = K. circuit. This is because the input common-mode voltage is directly sensed at the gate terminal of transistor M6. If the input common-mode voltage is changed, the variation would appear at the source node of transistor M6, that is, the source nodes of transistors M1 and M2. Therefore, the common-mode current would not be changed since the gate and source voltage of transistors M1 and M2 vary in the same direction simultaneously. Low distortion voltage-to-current conversion is obtained under the defined bias conditions, and furthermore, a transconductance tuning ability can be added with a high linearity current multiplier circuit, which is composed of transistors M7 to M10 in Fig. 1. The transistors would operate in the weak inversion region while proper sizing is required. For a MOSFET operating in the weak inversion region with VDS larger than a few times the thermal voltage UT , its current exhibits an exponential dependence on VGS and can be expressed as VGS W ID = ID0 exp (8) L nUT. In (4), the output current can be seen to be a nonlinear function of the input differential voltage. Since the evenorder harmonic terms could be cancelled out by the differential structure, the third-order harmonic distortion would become the dominant component. We can find that to minimize the third-order distortion term, the following equation should be satisfied. 2Ib Vcm − Vth (7) = K6 2. where W and L are the width and the length of the transistor, respectively, ID0 is the reverse saturation current, n is the subthreshold slope factor, and UT is the thermal voltage. From the above equation, we can find that ID7 L7 VS G7 = nUT ln (9) ID0 W7 ID8 L8 (10) VS G8 = nUT ln ID0 W8. If the above condition is held, only the fifth or higher order distortion terms are left in (4) and these nonlinear terms have very low contribution to the proposed circuit. The input common-mode voltage is detected by using extra resistors, and the resistors are designed without degrading the input signal performance. In addition, this circuit would not need extra common-mode feedfoward (CMFF). The device sizes of transistors M7 and M8 are set to be the same. We can obtain from the linear voltage-to-current conversion circuit, ID7 = I1 + ii and ID8 = I1 − ii . Therefore, I1 +ii (11) ΔV = VS G7 −VS G8 = VGS 9 −VGS 10 = nUT ln I1 −ii. iout = a1,out vd + a2,out v2d + a3,out v3d + a4,out v4d + L ⎛ ⎞ 1 ⎜⎜⎜⎜ β2 − 3βα + α2 ⎟⎟⎟⎟ a1,out = Gm = K ⎜⎝α − ⎟⎠ 2 α2 + 2βα − β2. (4) (5). a3,out = −. The subthreshold slope factor n is equal to (Cox +.

(3) IEICE TRANS. FUNDAMENTALS, VOL.E93–A, NO.8 AUGUST 2010. 1558. Fig. 3. Fig. 2. Die photograph.. The simulated Gm range of the proposed transconductor.. Cdepl )/Cox [7], where Cox and Cdepl are the gate and depletion capacitance per unit area, respectively. We can find that the factor Cox is almost equal for NMOS and PMOS devices from the process device model. Besides, Cdepl would be changed according to the size of MOSFET, and we can design a specified ratio of NMOS and PMOS to obtain the same capacitance. The current output from the differential pair of transistors M9 and M10 can be expressed by ID9 =. ID10 =. 2I2 1+e. ΔV nUT. 2I2 −ΔV. 1 + e nUT. 2I2 I2 = I2 − ii I1 I1 + ii 1+ I1 − ii 2I2 I2 = I2 + ii = I1 I1 − ii 1+ I1 + ii. =. (13). Finally, the output current io is given by io = ID10 − I2 = I2 − ID9 =. I2 ii I1. Fig. 4. (12). (14). With the weak inversion characteristic, the input voltage should be logarithmically determined at first and through the exponential function, the output current would have a linear relationship. In other words, the output current is equal to a scaled version of the input current where the scaling factor is determined by the ratio of two bias currents. In our proposed circuit, the output current can be tuned by tuning the bias current I2 at the output stage. The high linearity characteristic can also be maintained when the circuit operates from the weak inversion region to the moderate inversion region, and thus the tuning range could be further extended. The transconductor was designed in the TSMC 0.18-μm Deep N-Well CMOS process, with a 1V supply. The power consumption is less than 0.24 mW. Figure 2 shows the large signal simulation of the transconductance with respect to the function of applied differential input voltage. With the scalable tuning current, the tuning range of 10 μS to 230 μS can be obtained. The chip photograph is shown in Fig. 3 with the active area less than 0.03 mm2 . The third-order inter-modulation (IM3) distortion measured with two sinusoidal tones of 400 mV pp am-. The measured IM3 of the proposed transconductor.. plitude at the transconductance of 100 μS is shown in Fig. 4. The IM3 is shown to be less than −68.5 dB at a frequency of 2 MHz. When we increase the transconductoance value to 230 μS, the IM3 is kept at −68.3 dB. The IM3 becomes −70 dB at the transconductance of 10 μS. The IIP3 can be obtained by using the IM3 results in different input signal swings. In this design, the IIP3 is 28 dBm. However, due to the limited supply voltage of 1 V, the P1 dB is 6.5 dBm. The circuit works under the differential fashion, and thus the noise performance is highly dependent on the aspect ratio of input transistors M1 and M2. In this circuit, a large aspect ratio of input transistors is designed and the measured √ input-referred noise of the transconductor is 9 nV/ Hz at 1 MHz. 3.. Paragraphs and Itemizations. A CMOS implementation of a wide tuning range transconductor is presented. Linear region MOS transistors are used to perform the voltage-to-current conversion and the thirdorder harmonic distortion term can be minimized by providing suitable bias conditions. The current multiplier makes use of weak inversion region MOS transistors to achieve high linearity. The theoretical analysis of the high performance operation and the results are provided to demonstrate the validity of the transconductor..

(4) LETTER. 1559. Acknowledgments The authors would like to thank the National Chip Implementation Center of Taiwan for supporting the chip fabrication. References [1] T.Y. Lo and C.C. Hung, “A 40 MHz double differential-pair CMOS OTA with −60 dB IM3,” IEEE Trans. Circuits Syst. I, vol.55, no.2, pp.258–265, Feb. 2008. [2] S.R. Zarabadi, M. Ismail, and C.C. Hung, “High performance analog VLSI computational circuits,” IEEE J. Solid-State Circuits, vol.33,. no.4, pp.644–649, April 1998. [3] J.L. Pennock, “CMOS Triode transconductor continuous time filters,” Proc. IEEE CICC, pp.378–381, 1986. [4] C. Yoo, S.W. Lee, and W. Kim, “A ±1.5-V, 4-MHz CMOS continuoustime filter with a single-integrator based tuning,” IEEE J. Solid-State Circuits, vol.33, no.1, pp.18–27, Jan. 1998. [5] F. Yang and C.C. Enz, “A low-distortion BiCMOS seventh-order Bessel filter operating at 2.5 V supply,” IEEE J. Solid-State Circuits, vol.31, no.3, pp.321–330, March 1995. [6] R.G. Carvajal, J. Ramirez-Angulo, A.J. Lopez-Martin, A. Torralba, J.A.G. Galan, A. Carlosena, and F.M. Chavero, “The flipped voltage follower: A useful cell for low-voltage low-power circuit design,” IEEE Trans. Circuits Syst. I, vol.52, no.7, pp.1276–1291, July 2005. [7] D.A. Johns and K. Martin, Analog Integrated Circuit Design., John Wiley & Sons, New Jersey, 1997..

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