行政院國家科學委員會專題研究計畫 成果報告
電路中間聯結的模式簡化-基於平衡實現的方法(II)
計畫類別： 個別型計畫 計畫編號： NSC91-2215-E-009-069- 執行期間： 91 年 08 月 01 日至 92 年 07 月 31 日 執行單位： 國立交通大學電機與控制工程學系 計畫主持人： 林清安 計畫參與人員： 吳建賢 報告類型： 精簡報告 處理方式： 本計畫可公開查詢中 華 民 國 92 年 11 月 10 日
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1
Introduction
It has been asserted that interconnect de-lay dominates gate dede-lay in next generation nanometer scale IC’s [1]. Rapid and accurate analysis of interconnect delay is crucial for the success of nano-scale IC design. Accurate anal-ysis of interconnect delay taking into account
the transmission line effect is computationally unrealistic. Lump approximations usually re-sult in RLC circuits of sufficient high order that are too computation intensive for simulation tools such as SPICE. Circuit model order re-duction is thus an important research topic and many techniques have been proposed over the last 10 years.
The techniques can be classified into two groups: one based on moment matching and the other based on balanced realization. Both approaches have their origin in system and con-trol theory. The idea of moment matching is first applied to circuit model order reduction in the name of asymptotic waveform evaluation (AWE) [2]. The method of balanced realiza-tion [3] appears more recently [9], [8]. It is well-known that the moment matching method may yield unstable reduced models. Our study shows that for RLC trees, even a second-order reduced model may be unstable [4]. For high-order circuits, direct computation of moments becomes very ill-conditioned. Much effort is devoted to improving numerical robustness [7] with some success, but the stability problem remains. The method of balanced realization on the other hand guarantees stability of re-duced model at the expense of higher computa-tion complexity. For high order circuits,
putation of the balancing transformation may also be ill-conditioned.
We study application of balanced realization method and its variations to circuit model or-der reduction. The report is organized as fol-lows. Section 2 introduces balanced realization method, properties of the reduced model, and variations of the method. A method that re-duces computation complexity based on low-rank Lyapunov solutions is discussed in Section 3. Simulation results are shown in Section 4 and brief conclusions are given in Section 5.
2
Method of balanced realization
A linear time-invariant passive RLC circuit, possibly obtained from lump approximation of an interconnect, can be described by a standard linear state equation
˙x(t) = Ax(t) + bu(t)
y(t) = cx(t) (1) where u(t) is the source input, y(t) is the out-put of interest, x(t) is the state, A ∈ Rn×n,
b ∈ Rn×1, and c ∈ R1×n. The transfer function
H(s) = c(sI −A)−1b is nth-order. By model
or-der reduction we mean finding a transfer func-tion Hr(s), of order r < n, so that Hr(s) is close
to H(s) in some sense. In moment matching ap-proach, the two transfer function are consider close in that their first r moments are identical. In balanced realization approach, the order re-duction is obtained through a rere-duction in state space dimension. The two transfer functions, or equivalently the input-output relations, are close in that only the most important (most controllable and most observable) subspace is kept in the reduction.
2.1
Model reduction procedureA standard balanced realization procedure to obtain reduced order model is as follows: Step0: Given A ∈ Rn×n, b ∈ Rn×1, and
c ∈ R1×n.
Step1: Solve the Lyapunov equations
AWc+ WcAT + bbT = 0 (2)
ATWo+ WoA + cTc = 0 (3)
for the controllability gramian Wcand
ob-servability gramin Wo.
Step2: Compute the similarity transformation T by
(1) Cholesky factorization of Wc
Wc = RRT
(2) forming W = RTW 0R
(3) singular value decomposition W = V Σ2VT
where Σ = diag(σ1, · · · , σn), σ1 ≥
σ2 ≥ · · · ≥ σn> 0
(4) setting T = RV Σ−1/2.
Step3: Obtain the balanced system ˙x = Ax + bu y = c x
where A = T−1AT , b = T−1b, and c =
cT .
Step4: To obtain a rth order reduced model, partition compatibly A, b, and c as
A = A11 A12 A21 A22 b = b1 b2 c = c1 c2
where A11 ∈ Rr×r, and the reduced order
model is
˙x = A11x + b1u
y = c1x
with transfer function
2.2
Properties of reduced models Two most important properties of reduced model are (i) stability and (ii) exact error bound. More precisely, the first property means that if the original model is stable, then the re-duced model is also stable. We note that this property is very desirable and the lack of it is the main disadvantage of the moment matching method.The error bound is expressed in term of fre-quency response and it is tight. More precisely, for the original nth order circuit model and the rth order reduced model, the error frequency response E(jω) = H(jω) − Hr(jω) satisfies
max 0≤ω<∞ |E(jω)| ≤ 2 n X k=r+1 σk
The main disadvantage of balanced realiza-tion method is its computarealiza-tion complexity. To find a reduced model, we need to find the bal-ancing transformation T which requires the so-lutions of two Lyapunov equations in addition to the singular value decompositions that fol-low. For high order circuits, the amount of computation is huge. Furthermore, if the cir-cuit contains modes that are either nearly un-controllable or nearly unobservable, the com-putation leading to a balanced system is ill-conditioned and serious numerical difficulties may occur.
The error frequency response spreads (in general, quite evenly) over the entire frequency range. In particular, the dc-gains of the models do not match. This is undesirable, since many interconnect (especially gate-to-gate intercon-nect) do have unit dc-gain and it is important to maintain this property in the reduced model. (The moment matching method, in contrast, al-ways maintain this property by matching the 0th moment.)
2.3
Modification of balanced realiza-tionTo remove some of the disadvantages of the method, a number of modifications have been
proposed. We mention three of them below. (i) DC-gain matching
Consider the balanced system ˙x1 ˙x2 = A11 A12 A21 A22 x1 x2 + b1 b2 u y = c1 c2 x1 x2
Instead of removing the state component x2 completely as is done in the original
balanced realization method, the modifi-cation keep the steady-state value of x2in
order to make the dc-gain of the reduced model the same as that of the original model. The idea is borrowed from the so called singular perturbation method: the state x1 contains the ‘slow’ dynamics and
the state x2 contains the ‘fast’ dynamics.
In considering the slow dynamics, the fast dynamics can be assumed to be at steady state. More precisely, for a given x1(t),
the steady-state value of x2(t) satisfies
0 = A21x1(t) + A22x2(t) + b2u(t)
that is
x2(t) = −A−122(A21x1(t) + b2u(t))
Putting x2(t) into the first equation, we
get the reduced model as
˙x1= (A11− A12A−1
22A21)x1+ (b1− A12A−122b2)u y= (c1− c2A−122A21)x1+ (−c2A−122b2)u
The reduced model now has the same dc-gain as the original model.
(ii) Frequency weighting
Many interconnect parameters, such as delay time and rise time, depends mainly on the low-frequency characteris-tics of the transfer function. A good low-order reduced model should have small approximation error in the low-frequency band, while larger error in the high-frequency band can be tolerated. In
the balanced realization framework, fre-quency weighting techniques are intro-duced to achieve this desirable property [5], [6]. The basic idea is to augment the system with low-pass filter and then compute balancing transformation for an “equivalent ” system. This method is shown to be effective [6].
(iii) The Schur method
The computation of balancing trans-formation is usually ill-conditioned, this is especially so for RLC circuits of high or-der. Chiang and Safonov [10] proposes a method to obtain the same reduced model as the balanced realization method but without explicitly computing a balanced realization of the original system. Their idea is to compute the Schur decomposi-tion of the product gramian WcWo which
then provides an orthogonal basis for the eigenspace associated with the selected (large) Hankel singular values. Restrict the dynamics to this subspace gives the reduced model. The method is shown to be numerically stable even the system is nearly uncontrollable or unobservable. All the three modifications mentioned above still require solving the Lyapunov equations for the controllability and observability gramians, each of which amounts to solving a set of n(n+1)2 linear equations for an nth order system. To obtain an efficient method for model reduction, it is very desirable to avoid solving large Lya-punov equations.
3
Reducing computation
com-plexity
Much of the computation in obtaining a re-duced model using balanced realization method is devoted to the solutions of two large Lya-punov equations. To reduce computation, the Lyapunov equations can be solved approxi-mately. The basic approach is to restrict the solutions, respectively, to the Krylov subspace
Km(A, b) and Km(AT, cT), where
Km(A, b) = span{b, Ab, · · · , Am−1b}
and
Km(AT, cT) = span{cT, ATcT, · · · , (AT)m−1cT}
A procedure to obtain a set of m orthonormal basis of Km(A, b), known as the Arnoldi
proce-dure, is as follows. Arnoldi Procedure
(1) Choose b and compute q1 = b/kbk2
(2) for j = 1, 2, · · · , m (a) Compute w = Aqj (b) for i = 1, 2, · · · , m, hij = w Tq i w = w − hi,jqi (c) hj+1,j = kwk2 and qj+1= w/hj+1,j.
The procedure gives the set {q1· · · qm} as
orthonormal basis of Km(A, b). Let Qm =
[q1· · · qm], we have
QTmQm = Im
and
R(Qm) = Km(A, b)
The Arnoldi procedure produces a Hessenberg matrix Hm satisfying
QTmAQm= Hm
The matrix Hm is the representation of A,
re-stricted to Km(A, b), with respect to {q1· · · qm}.
A method proposed by Saad [11] to approx-imately solve the controllability gramian Wc is
as follows.
Step1: Using Arnoldi procedure to find Qm so
that
QTmAQm = Hm
Step2: Solving the low rank Lyapunov equa-tion
HmGm+ GmHmT + β2e1eT1 = 0
where β = kbk2 and e1 = [1 0 · · · 0]T
Step3: The approximate controllability gramian is
ˆ
Wc= QmGmQTm
Now the ˆWc∈ Rn×n has rank at most m
is a low rank approximation of Wc.
Similar procedure is used to compute a low rank approximation ˆWo ∈ Rn×n of Wo, the
observability gramian. With the gramian ˆWc
and ˆWo obtained, the Chiang-Safonov
proce-dure can then be used to obtain a rth order reduced model.
In general, the stability and accuracy of the reduced model is not guaranteed especially when m, the Krylov space dimension, is chosen small compared with n.
4
Simulation results
We consider a 19th order RLC circuit shown in Figure 1, the input is a voltage source and the output of interest is the voltage at node 9. The original transfer function is 19th order with unit dc-gain.
By direct balanced realization, the 2nd-order, 4th-order and 6th-order reduced mod-els are constructed. The dc-gains of the re-duced models are respectively 0.8526, 0.9984, and 1.0001. Step responses of the original model and the reduced models, shown in Fig-ure 3, show that 4th- and 6th-order models give very good match, while the steady-state error of the 2nd-order model is about 15%. Figure 3 show that both 4th-order and 6th-order mod-els have very small frequency response error, the error of the 2nd-order model concentrates mostly in the low frequency range ≤ 0.3GHz and spreads quite evenly beyond.
By dc-gain matching, the frequency re-sponse error in low-frequency range is greatly suppressed, for the 2nd-order model the error spreads quite evenly up to 1GHz as shown in Figure 5. Step responses show that with dc-gain matching, in Figure 4, a 2nd-order reduced model is quite accurate as far delay time and rise time are concerned.
Figure 6 shows the step response of reduced models computed through low rank Lyapunov solution. The dimension of Krylov subspace is chosen 16 and the reduced model is 7th-order. The model exhibits good transient response, while substantial steady state error is observed. The dc-gain mismatch is then corrected by scal-ing , the error in transient response, however, is then increased.
5
Conclusions
We consider the balanced realization method as a tool for model order reduction of RLC interconnect circuits. The method has many advantages over the moment-matching based methods. The need to solving Lyapunov equations of large size seems to be the main disadvantage associated with the method. Our study shows the method now available for low-rank Lyapunov solution does not substantially reduced computations and further investigation is need if the balanced realization method is to become an efficient tool for interconnect model reduction.
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[9] Y. Liu, and B. D. O. Anderson “Sin-gular perturbation approximation of bal-anced systems,” in IEEE Proc. 28th CDC , Florida, vol. 2, pp. 1355-1360, 1989. [10] M. G. Safonov, and R. Y. Chiang, “A
Schur Method for Balanced-Truncation Model Reduction,” IEEE Trans. Automat. Control, vol.34, No. 7, pp. 729-733, 1989. [11] Y. Saad “Numerical Solution for Large
Lyapunov Equation,” Proc. Intl. Symp. MTNS-1989, pp. 856-869, 1989. R: Ω L: nH C: pF + − vs(t) 7 2 4 7 6 6 5 2 3 10 7 0.01 9 0.02 10 12 7 11 0.03 7 0.08 8 9 3 7 0.03 5 0.05 6 3 3 6 0.3 3 0.1 4 4 5 5 0.2 1 0.1 2 Figure 1: An RLC circuit
0 5 10 15 20 25 30 −0.2 0 0.2 0.4 0.6 0.8 1
1.2 step response of node 9
time (ns) voltage (v) exact BR2 BR4 BR6
Figure 2: Step responses of original and reduced mod-els 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1 frequency magnitude response
frequency (GH) |E(j ω )| original BR2 error BR4 error BR6 error
Figure 3: Frequency (magnitude) response of original and error transfer functions
0 5 10 15 20 25 30 −0.2 0 0.2 0.4 0.6 0.8 1
1.2 step response of node 9
time (ns) voltage (v) exact SP2 SP4 SP6
Figure 4: Step responses of original and reduced mod-els after dc-gain matching
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1 frequency magnitude response
frequency (GH) |E(j ω )| original SP2 error SP4 error SP6 error
Figure 5: Frequency (magnitude) response of original and error transfer functions after dc-gain matching
0 5 10 15 20 25 30 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 time (ns) voltage (v) node 9 exact m=16,k=7 scaling
Figure 6: With low rank Lyapunov solution step re-sponses of the original system and a 7th-order reduced model
