EELE 414 – Introduction to VLSI Design Module #2 – MOSFET Operation
•
Agenda
1. MOSFET Operation - Device Physics - MOSFET Structure - IV Characteristics - Scaling
- Small Geometry Effects - Capacitance
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Announcements
1. Read Chapter 3
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MOSFET
- Metal Oxide Semiconductor Field Effect Transistor
- we need to understand the detailed operation of the MOSFET in order to use it to build larger blocks such as Inverters, NAND gates, adders, etc…
- we will cover the theory of the device physics, energy bands, and circuit operation - we will do homework to analyze the behavior by hand
- in the real world, we typically use SPICE simulations to quickly analyze the MOSFET behavior - but we need to understand what SPICE is calculating or:
1) we won’t be able to understand performance problems
2) we won’t be able to troubleshoot (is it the tool, is it the circuit, is it the process?)
Semiconductors
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Semiconductors
- a semiconductor is a solid material which acts as an insulator at absolute zero. As the temperature increases, a semiconductor begins to conduct
- a single element can be a semiconductor:
Carbon (C), Silicon (Si)
- a compound material can also form a semiconductors (i.e., two or more materials chemically bonded)
Gallium Arsenide (GaAs), Indium Phosphide (InP) - an alloy material can also form semiconductors
(i.e., a mixture of elements of which one is a metal):
Silicon Germanium (SiGe), Aluminum Gallium Arsenide (AlGaAs) - Silicon is the most widely used semiconductors for VLSI circuits due to:
- it is the 2ndmost abundant element (25.7%) of the earth’s crust (after oxygen) - it remains a semiconductor at a higher temperature
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Charge Carriers
- since we want to use Si to form electronics, we are interested in its ability to conduct current.
A good conductor has a high concentration of charge carriers.
- an electron can be a charge carrier.
- a hole (the absence of an electron) can be a charge carrier.
- “Intrinsic” Silicon means silicon that is pure or it has no impurities. We sometimes called this i-typed Silicon
- Since there are no impurities, the number of charge carriers is determined by the properties of the Silicon itself.
- We can define the Mobile Carrier Concentrations as:
n = the concentration of conducting electrons p = the concentration of conducting holes - these are defined per unit volume (1/cm3)
Semiconductors
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Charge Carriers
- Intrinsic Silicon has a carrier concentration of : ni = 1.45 x 1010 cm-3
- notice the units are “carriers per cubic centimeter”
- notice that we give the subscript “i” to indicate “intrinsic”
- this value is dependant on temperature and is defined above at T=300 K (i.e., room temperature)
- there are about 5x1022Atoms of Silicon per cubic centimeter in a perfect intrinsic lattice
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Charge Carriers
- The equilibrium of the carriers in a semiconductor always follows the Mass Action Law
- this means there is an equal number of p and n charge carriers in intrinsic Silicon
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Electrons vs. Holes
- electrons have a charge of q=-1.6x10-19 Coulomb (C) - holes are the “absence” of electrons in an orbital
of an atom. When an electron moves out of an orbital, it leaves a void (or hole). This hole can “accept” another electron
- as electrons move from atom to atom, the holes effectively move in the opposite direction and give the impression of a positive charge moving
2
n
ip
n
Energy Bands
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Energy Bands
- the mobility of a semiconductor increases as its temperature increase.
- Increasing the mobility of a semiconductor eventually turns the material into a conductor.
- this is of interest to electronics because we can control the flow of current - we can also cause conduction using an applied voltage to provide the energy - we are interested in how much energy it takes to alter the behavior of the material
- Energy Band Diagrams are a graphical way to describe the energy needed to change the behavior of a material.
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Energy Bands
- Quantum Mechanics created the concept of bands to represent the levels of energy that are present at each “state” of an atom.
- the electrons on an atom occupy these energy states
- For a given number of electrons in an atom, we begin filling in the energy bands from lowest to highest energy until all of the electrons have been used.
- electrons only exist in the bands. By convention, electrons are forbidden from existing in between bands
- there is a finite amount of energy that exists to move an electron from one band to another - if given enough energy (via heat or E-fields), electrons can receive enough energy to jump to
a higher energy band.
Energy Bands
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Energy Bands
Valence Band : the highest range of electron energies where electrons are normally present at absolute zero.
: this is the highest “filled” band
Conduction Band : the range of electron energy sufficient to make the electrons free to accelerate under the influence of an applied electric field (i.e., current).
: this is the lowest “unfilled” band
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Band Gap
- the band gap energy is the energy between the lowest level of the "conduction band" and the top of the "valence band"
- this can be thought of as the amount of energy needed to release an electron for use as current at absolute zero.
Energy Bands
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Fermi Level
- the Fermi Level (or energy) represents an energy level that at absolute zero:
- all bands below this level are filled - all bands above this level are unfilled
- the Fermi Level at room temperatures is the energy at which the probability of a state being occupied has fallen to 0.5
- at higher temperatures, in order for an electron to be used as current, it needs to have an energy level close to the Fermi Level
- this can also be thought of as the equilibrium point of the material
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Band Gap Comparisons
- the following shows the relationship of Band Gap energies between insulators, semiconductors, and metals
- notice that the only difference between an insulator and a semiconductor is that the band gap is smaller in a semiconductor.
- notice that there is an overlap between the conduction and valence bands in metals. This means that metals are always capable of conducting current.
Energy Bands
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Band Gap Comparisons
Insulator Band Gap : it is large enough so that at ordinary temperatures, no electrons reach the conduction band
Semiconductor Band Gap : it is small enough so that at ordinary temperatures, thermal energy can give an electron enough energy to jump to the conduction band : we can also change the semiconductor into a conductor by introducing
impurities
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Band Gap Comparisons
- we typically describe the amount of energy to jump a band in terms of “Electron Volts” (eV)
- 1 eV is the amount of energy gained by an unbound electron when passed through an electrostatic potential of 1 volt
- it is equal to (1 volt) x (unsigned charge of single electron) - 1 Volt = (Joule / Coulomb)
- (V x C) = (J/C) x (C) = units of Joules - 1eV = 1.6x10-19 Joules
- we call materials with a band gap of
~ 1eV a “semiconductor”
- we call materials with a band gap of much greater than 1eV an “insulator”
- and if there isn’t a band gap, it is a “metal”
Energy Bands
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Band Diagram
- in a band diagram, we tabulate the relative locations of important energy levels
- Note that EO is where the electron has enough energy to leave the material all together (an example would be a CRT monitor)
- as electrons get enough energy to reach near the Fermi level, conduction begins to occur
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Band Diagram of Intrinsic Silicon
- Intrinsic Silicon has a band gap energy of 1.1 eV - @ 0 K, Eg=1.17 eV
- @ 300 K, Eg=1.14 eV
Doping
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Doping
- the most exploitable characteristic of a semiconductor is that impurities can be introduced to alter its conduction ability - Silicon has a valence of 4 which allows it to form a perfect
lattice structure. This lattice can be broken in order to accommodate impurities
- VLSI electronics use Silicon as the base material and then alter its properties to form:
1) n-type Silicon : material whose majority carriers are electrons
: introducing a valence-of-5 material increases the # of free negative charge carriers
: Phosphorus (P) or Arsenic (As) are typically used (group V elements) 2) p-type Silicon : material whose majority carriers are holes
: introducing a valence-of-3 material increases the # of free positive charge carriers
: Boron (B) is typically used (a group III element)
- when Silicon is doped, it is called “Extrinsic Silicon” due to the presence of impurities
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N-type Doping
- a perfect Silicon lattice forms covalent bonds with neighbors on each side - there is an equal number of p and n charge carriers (n∙p=ni2)
- inserting an element into the lattice with a valence of 5 will form 4 covalent bonds PLUS have an extra electron
N-type Doping
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N-type Doping
- this extra electron increases the n-type charge carriers
- we call the additional element that provides the extra electron a Donor - the concentration of donor charge carriers is now denoted as ND
- we call ND the doping concentration of an n-type material - we can use the Mass Action Law to say:
type n
i D
i type n D
p N n
n p
N
2
2
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N-type Doping
- Doping Silicon can achieve a Donor Carrier Concentration between 1013 cm-3 to 1018 cm-3 - Doping above 1018 cm-3 is considered degenerate (i.e., it starts to reduce the desired effect) - We give postscripts to denote the levels of doping (normal, light, or heavy)
- Remember that Silicon has a density of ~1021 atoms per cm Example:
n- : light doping : ND = 1013cm-3 : 1 in 100,000,000 atoms n : normal doping : ND = 1015cm-3 : 1 in 1,000,000 atoms n+ : heavy doping : ND > 1017cm-3 : 1 in 10,000 atoms
N-type Doping
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Effect on the Band Structure
- by adding more electron charge carriers to a material, we create new energy states
- by adding more electrons to Silicon, we decrease the energy that it takes for an electron to reach the conduction band
- this moves the Fermi Level (the highest filled energy state at equilibrium) closer to the conduction band
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Effect on the Band Structure
- We can define the Fermi Potential (F) as the difference between the intrinsic Fermi Level (Ei) and the new doped Fermi Level (EFn)
- note: that Fn has units of volts and is positive since EFn>Ei,
- note: that Ei and EFn have units of eV, which we convert to volts by dividing by q - note: we use q=1.6x10-19C, which is a positive quantity
- the Boltzmann approximation gives a relationship between the Fermi Level and the charge carrier concentration of a material (a.k.a, the Quasi Fermi Energy).
- This expression relates the change in the Fermi Level (from intrinsic) to the additional charge carriers due to n-type doping.
where, kB = the Boltzmann Constant = 8.62x10-5 (eV/K) or
= 1.38x10-23 (J/K)
q E E
F iF
n n
T k
E E i
B n i F
e n
n
N-type Doping
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Effect on the Band Structure
- if we rearrange terms and substitute n=ND…
- since ND>ni, the natural log is taken on a quantity that is greater than one
- this makes Fn POSITIVE
F i
i D B
B i F
i D
T k
E E
i D
T k
E E i D
E n E
T N k
T k
E E
n N n e N
e n N
n n
B n i F
B n i F
ln ln
i D B
F
i F
F
n N q
T k
q E E
n
n n
ln
Then plug into the Fermi
potential
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P-type Doping
- inserting an element into the silicon lattice with a valence of 3 will form 3 covalent bonds but leave one orbital empty
- this is called a hole and since it “attracts an electron”, it can be considered a positive charge with a value of +1.6e-19 C
P-type Doping
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P-type Doping
- this extra electron increases the p-type charge carriers
- we call this type of charge carrier an Acceptor since it provides a location for an electron to go - the concentration of acceptor charge carriers is now denoted as NA
- we call NA the doping concentration of a p-type material - we can use the Mass Action Law to say:
type p
i A
i A type p
n N n
n N
n
2
2
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Effect on the Band Structure
- by adding more hole charge carriers to a material, we also create new energy states - holes create new “unfilled” energy states
- this moves the Fermi level down closer to the Valence band
P-type Doping
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Effect on the Band Structure
- We again define the Fermi Potential (F) as the difference between the intrinsic Fermi Level (Ei) and the new doped Fermi Level (EFp)
- we again use the Boltzmann approximation, which gives a relationship between the Fermi Level and the electron concentration of a material.
- notice that the (EFp - Ei) term yields a negative potential since EFp < Ei
- note that for the P-type doping the Fermi level moves down below the original Intrinsic level.
This original expression stated the increase in electron energy achieved by the doping.
So we need to swap the p and ni terms to use this equation.
notice that the (Ei - EFp) term in the exponent represents a positive voltage since Ei > EFp
q E E
F iF
p p
T k
E E i
T k
E E i
B Fp i B
Fp i
e p n e
n
p
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Effect on the Band Structure
- if we rearrange terms and substitute p=NA…
- since NA>ni, the natural log is taken on a quantity that is between 0 and 1
- this makes Fp NEGATIVE
i F
A i B
Fp i
A i B
B F i
A i
T k
E E
A i
T k
E E A i
E N E
T n k
E N E
T n k
T k
E E N
n N e
n
e N n
p p B
Fp i
B Fp i
ln ln ln
A i B
F
i F
F
N n q
T k
q E E
p
p p
ln
Then plug into the Fermi
potential
Work Function
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Electron Affinity & Work Function
- another metric of a material is the amount of energy it takes to move an electron into Free Space (E0)
Electron Affinity : the amount of energy to move an electron from the conduction band into Free Space.
Work Function : the amount of energy to move an electron from the Fermi Level into Free Space.
C
O
E
E q
C F
S
q E E
q
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Work Function of Different Materials
- When materials are separate, we can compare their band energies by lining up their Free Space energies
MOS Structure
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MOS Structure
- When materials are bonded together, their Fermi Levels in the band diagrams line up to reflect the
thermodynamic equilibrium.
- of special interest to VLSI is the combination of a Metal Oxide Semiconductor (p-type) structure
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Built-In Potential
- there is a built in potential due to the mismatches in work functions that causes the bands to bend down at the oxide-semiconductor junction
- this is due to the PN junction that forms due to the p-type Si and the oxide. The oxide polarizes slightly at the surface
MOS Structure
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Built-In Potential Example
- Example 3.1 in text. Given q∅Fp=0.2eV, what is the built in potential in the following MOS structure?
Solution: We need to find the difference in work functions between the Silicon substrate and the metal gate. We are given the metal gate work function (4.1eV) so we need to find the Silicon work function:
Now we just subtract the Silicon work function from the Metal Gate work function:
eV eV eV
eV
q
S0 . 2 4 . 9
2 1 . 15 1
.
4
eV eV
eV q
q 4 . 1 4 . 9 0 . 8
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MOS Accumulation
- If we apply an external bias voltage to the MOS, we can monitor how the charge carriers are affected - assume a "body" voltage of 0v (VB=0)
1) let's first apply a negative voltage to the "gate" (VG=negative) - the holes of the p-type semiconductor are
attracted to the Oxide surface
- this causes the concentration of charge carriers at the surface to be greater
than that of the normal concentration (NA) - this is called the Accumulation of
charge carriers in the semiconductor
MOS Under Bias
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MOS Accumulation
- applying a negative voltage to the metal raises its highest electron energy state by q·VG - the surface accumulation of energy can be reflected in the energy bands "bending up" near
the Oxide-Semiconductor surface
- note also that the minority carriers (electrons) in the p-type semiconductor are pushed away from the oxide surface (not shown)
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MOS Depletion
2) now let's apply a small positive voltage to the gate
- the holes of the p-type semiconductor are repelled back away from the oxide surface - as VG increases, it will approach a level where there are no mobile carriers near the
Oxide-Semiconductor junction
- the region without mobile carriers is called the Depletion Region
MOS Under Bias
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MOS Depletion
- the positive voltage that develops at the Oxide-Semiconductor surface bends the energy bands downward to reflect the decrease in electron energy in this region.
- the thickness of the depletion region is denoted as xd
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MOS Depletion
- the depletion depth xd is a function of the surface potential ∅S
- if we model the holes as a sheet of charge parallel to the oxide surface, then the surface potential (∅S) to move the charge sheet a distance xd away can be solved using
the Poisson equation.
- the solutions of interest are:
1) the depth of the depletion region:
2) the depletion region charge density:
A F S Si
d
q N
x
2
F S Si A d
A
x q N
N q
Q 2
MOS Under Bias
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MOS Inversion
3) now let's apply a larger positive voltage to the gate
- the positive surface charge in the Oxide is strong enough to pull the minority carrier electrons to the surface.
- this can be seen in the band diagrams by “bending” the mid-gap (or Ei) energy at the surface of the Oxide and semiconductor until it falls below the Fermi Level (EFp)
- the n-type region created near the Oxide-Semiconductor barrier is called the Inversion layer
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MOS Inversion
- this region has a higher density of minority carriers than majority carriers during inversion - by definition, the region is said to be “inverted” when the density of mobile electrons
is equal to the density of mobile holes
- this requires that the surface potential has the same magnitude as the bulk Fermi potential,
- as we increase the Gate voltage beyond inversion, more minority carriers (electrons) will be pulled to the surface and increase the carrier concentration
- however, the inversion depth does not increase past its depth at the onset of inversion:
- this means that the maximum depletion depth (xdm) that can be achieved is given by:
- once an inversion layer is created, the electrons in the layer can be moved using an external E-field
F
s
A F Si
dm
q N
x
2 2
FMOSFET Operation
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MOSFET Operation
- we saw last time that if we have a MOS structure, we can use VG to alter the charge concentration at the oxide-semiconductor surface:
1) Accumulation : VG < 0
: when the majority carriers of the semiconductor are pulled toward the oxide-Si junction
2) Depletion : VG > 0 (small)
when the majority carriers of the Si are pushed away from the oxide-Si junction until there is a region with no mobile charge carriers
3) Inversion : VG > 0 (large)
: when VG is large enough to attract the minority carriers to the oxide-Si junction forming an inversion layer
•
MOSFET Operation (p-type substrate)
- Inversion is of special interest because we havecreated a controllable n-type channel that can be used to conduct current.
- these electrons have enough energy that they can be moved by an electric field
- if we applied an E-field at both ends of this channel, the electrons would move
NOTE: In a p-type material, the holes are also charge carriers. But since they exist in all parts of the Si, we can’t control where the current goes.
We use the minority charge carriers in inversion because we can induce a channel using the MOS structure.
MOSFET Operation
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MOSFET Operation (p-type substrate)
- in order to access the channel created by inversion, we add two doped regions at either end of the MOS structure
- these doped regions are of the minority carrier type (i.e., n-type)
- current can flow between these terminals if an inversion is created in the p-type silicon by VG - since we are controlling the flow of current with a 3rd terminal, this becomes a “transistor”
- since we use an E-field to control the flow, this becomes the MOS Field Effect Transistor
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Terminal Definition
Gate : The terminal attached to the metal of the MOS structure.
Source : One of the doped regions on either side of the MOS structure.
Defined as the terminal at the lower potential (vs. the Drain)
Drain : One of the doped regions on either side of the MOS structure.
Defined as the terminal at the higher potential (vs. the Source)
Body : The substrate
NOTE:we often don’t show the Body connection
MOSFET Operation
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MOSFET Dimensions
Length : the length of the channel. This is defined as the distance between the Source and Drain diffusion regions
Width : the width of the channel. Notice that the metal, oxide, source, and drain each run this distance
tox : the thickness of the oxide between the metal and semiconductor
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MOSFET Materials
Metal : Polysilicon. This is a silicon that has a heavy concentration of charge carriers. This is put on using Chemical Vapor Deposition (CVD). It is naturally conductive so it acts like a metal.
Oxide : Silicon-Oxide (SiO2). This is an oxide that is grown by exposing the Silicon to oxygen and then adding heat. The oxide will grow upwards on the Silicon surface
Semiconductor : Silicon is the most widely used semiconductor.
P-type Silicon : Silicon doped with Boron
N-type Silicon : Silicon doped with either Phosphorus or Arsenic
MOSFET Operation
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MOSFET Type
- we can create a MOSFET using either a p-type or n-type substrate. We then can move current between the source and drain using the minority carriers in inversion to form the conduction channel - we describe the type of MOSFET by describing what material is used to form the channel
N-Channel MOSFET P-Channel MOSFET
- p-type Substrate - n-type Substrate
- n-type Source/Drain - p-type Source/Drain
- current carried in n-type channel - current carried in p-type channel
•
Enhancement vs. Depletion MOSFETS
Enhancement Type : when a MOSFET has no conduction channel at VG=0v : also called enhancement-mode
: we apply a voltage at the gate to turn ON the channel
: this is used most frequently and what we will use to learn VLSI Depletion Type : when a MOSFET does have a conducting channel at VG=0v
: also called depletion-mode
: we apply a voltage at the gate to turn OFF the channel : we won’t use this type of transistor for now
Note: We will learn VLSI circuits using enhancement-type, n-channel MOSFETS.
All of the principles apply directly to Depletion-type MOSFETs as well as p-channel MOSFETs.
MOSFET Operation
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MOSFET Symbols
- there are multiple symbols for enhancement-type MOSFETs that can be used
•
Terminal Voltages
- all voltages in a MOSFET are defined relative to the Source terminal
VGS : Gate to Source Voltage
VDS : Drain to Source Voltage
VBS : Body to Source Voltage
MOSFET Operation Under Bias
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MOSFET under Bias (Depletion)
- let’s begin with an n-channel, enhancement-type MOSFET - we bias the Source, Drain, and Body to 0v
- we apply a small positive voltage to the gate, VGS > 0 (small)
- this creates a depletion region beneath the Gate, Source, and Drain that is void of all charge carriers
•
MOSFET under Bias (Inversion)
- as VGS gets larger, it will form an inversion layer beneath the Gate oxide by attracting the minority carriers in the substrate to the oxide-Si surface.
- when the surface potential of the gate reaches the bulk Fermi potential, the surface inversion will be established and an n-channel will form - this channel forms a path between the Source and Drain
F
s
Threshold Voltage
•
MOSFET under Bias (Inversion)
- as VGS gets larger, it will form an inversion layer beneath the Gate oxide by attracting the minority carriers in the substrate to the oxide-Si surface.
- when the surface potential of the gate reaches the bulk Fermi potential, the surface inversion will be established and an n-channel will form - this channel forms a path between the Source and Drain
F
s
•
MOSFET under Bias (Inversion)
- we are very interested when an inversion channel forms because it represents when the transistor is ON
- we define the Gate-Source voltage (VGS) necessary to cause inversion the Threshold Voltage (VT0)
when VGS < VT0 there is no channel so no current can flow between the Source and Drain terminals
when VGS > VT0 an inversion channel is formed so current can flow between the Source and Drain terminals
NOTE: We are only establishing the channel for current to flow between the Drain and Source.
We still have not provided the necessary VDS voltage in order to induce the current.
- just as in the MOS inversion, increasing VGS beyond VTO does not increase the surface potential or depletion region depth beyond their values at the onset of inversion.
It does however increase the concentration of charge carriers in the inversion channel.
Threshold Voltage
•
Threshold Voltage
- the threshold voltage depends on the following:
1) the work function difference between the Gate and the Channel
2) the gate voltage necessary to change the surface potential
3) the gate voltage component to offset the depletion region charge
4) the gate voltage necessary to offset the fixed charges in the Gate-Oxide and Si-Oxide junction
- putting this all together gives us the expression for the threshold voltage at Zero Substrate Voltage
ox ox ox
B F
GC
T
C
Q C
V
0 2 Q
0
GC
F 2
ox B
C Q
0ox ox
C
Q
•
Threshold Voltage with Non-Zero Substrate Bias
- sometimes we can't guarantee that the substrate will be zero at all points of the IC:
- when a potential develops in the substrate, it pushes the Source terminal of the MOSFET to a higher potential. We typically describe this as VSB (instead of VBS)
- to predict the effect of a substrate bias voltage (VSB), we must alter the expression for the depletion charge density term:
- this changes the expression for the Threshold Voltage to:
ox ox ox
B F
GC
T
C
Q C
V 2 Q
ox B ox
B
C Q C
Q
0
Threshold Voltage
•
Threshold Voltage with Non-Zero Substrate Bias cont…
- VT0is hard to predict due to uncertainties in the doping concentrations during fabrication.
As a result, VT0 is measured instead of calculated.
- this means for a typical transistor, it is a given quantity
- however, the non-zero Substrate Bias is a quantity that still must be considered.
- we want to get an expression for VTthat includes VT0 (a given)
- the depletion charge density is a function of the material and the substrate bias:
ox B B
T ox
B B
ox ox ox
B F
GC
T
C
Q V Q
C Q Q
C Q C
V 2 Q
0
0
0
0
F SB F
ox Si A ox
B
B
V
C N q C
Q
Q
2 2 2
0
•
Threshold Voltage with Non-Zero Substrate Bias cont…
- we can separate the material dependant term into its own parameter separate from VSB
where is called the substrate-bias or body-effect coefficient - this leaves our complete expression for threshold voltage as:
- a few notes on this expression:
1) in an n-channel, the following signs apply:
2) in a p-channel, the following signs apply
F SB F
T
T
V V
V
0 2 2
ox Si A
C N
q
2
SB
F
V
Threshold Voltage
•
Threshold Voltage with Non-Zero Substrate Bias cont…
- the following plot shows an example of threshold dependence on substrate bias for an enhancement-type, n-channel MOSFET
- the threshold voltage increases with Substrate bias. This means as noise gets on the substrate, it takes more energy to create the channel in the MOSFET. This is a BAD thing…
F SB F
T
T
V V
V
0 2 2
•
MOSFET I-V Characteristics
- we have seen how the Gate-to-Source voltage (VGS) induces a channel between the Source and Drain for current to flow through
- this current is denoted IDS
- remember that this current doesn't flow unless a potential exists between VD and VS - the voltage that controls the current flow is denoted as VDS
- once again, we start by applying a small voltage and watching how IDS responds
- notice that now we actually have two control variables that effect the current flow, VGS and VDS - this is typical operating behavior for a 3-terminal device or transistor
- we can use an enhancement n-channel MOSFET to understand the IV characteristics and then directly apply them to p-channel and depletion-type devices
MOSFET I-V Characteristics
•
MOSFET I-V Characteristics : Cutoff Region
- when VGS < VT, there is no channel formed between the Drain and Source and hence IDS=0 A - this region is called the Cutoff Region
- this region of operation is when the Transistor is OFF
•
MOSFET I-V Characteristics : Linear Region
- When VGS > VT, a channel is formed. IDS is dependant on the VDS voltage - When VDS = 0v, no current flows
MOSFET I-V Characteristics
•
MOSFET I-V Characteristics : Linear Region
- If VGS > VT and VDS > 0, then a current will flow from the Drain to Source (IDS)
- the MOSFET operates like a voltage controlled resistor which yields a linear relationship between the applied voltage (VDS) and the resulting current (IDS)
- for this reason, this mode of operation is called the Linear Region
- this region is also sometimes called the triode region (we'll use the term "linear")
- VDS can increase up to a point where the current ceases to increase linearly (saturation) - we denote the highest voltage that VDS can reach and still yield a linear increase in current
as the saturation voltage or VDSAT
•
MOSFET I-V Characteristics : Linear Region
- when a voltage is applied at VD, its positive chargepushes the majority charge carriers (holes) that exist at the edge of the depletion region further from the Drain.
- as the depletion region increases, it becomes more
difficult for the Gate voltage to induce an inversion layer.
This results in the inversion layer depth decreasing near the drain.
- as VD increases further, it eventually causes the inversion layer to be pinched-off and prevents the current flow to increase any further.
- this point is defined as the saturation voltage (VDSAT) - from this, we can define the linear region as:
VGS>VT 0 < V < V
MOSFET I-V Characteristics
•
MOSFET I-V Characteristics : Linear Region
- the Drain to Source current (IDS) is given by the expression:
- where:
un = electron surface mobility (units in cm2/V·s) Cox = Unit Oxide Capacitance (units in F/cm2) W = width of the gate
L = length of the gate
- remember this expression is only valid when : VGS>VT
0 < VDS < VDSAT
2
0 2
2
GS T DS DSox n
DS
V V V V
L W C
I u
linear
A note on electron mobility (un):
unrelates the drift velocity to the applied E-field
Drift velocity is the average velocity that an electron can attain due to an E-field.
We are interested in Drift Velocity because it tells us how fast the electron can get from the Source to the Drain.
Since current is defined as I=∆Q/ ∆t, un relates how much charge can move
•
MOSFET I-V Characteristics : Linear Region
- what is linear about this equation?- most of the parameters are constants during evaluation. They are sometimes lumped into single parameters
or
- Notice that W and L are parameters that the designers have control over. Most of the other parameters are defined by the fabrication process and are out of the control of the IC designer.
2
0 2
2
GS T DS DSox n
DS
V V V V
L W C
I u
linear
ox n
C u
k ' 2
0
2
2 '
DS DS
T GS
DS
V V V V
L W I k
linear
L C W u
k
n
ox 2
0
2
2
GS T DS DSDS
k V V V V
I
linear
MOSFET I-V Characteristics
•
MOSFET I-V Characteristics : Linear Region
- what is linear about this equation?- the -VDS2 term alters the function shape in the linear region. As it becomes large enough to significantly decrease IDS in this function, the transistor enters saturation and this expression is no longer valid.
2
0 2
2
GS T DS DSDS
k V V V V
I
linear
For a fixed VGS, then
IDS depends on VDS
VDS2has a smaller effect on IDS at low values of VDS since it is
not multiplied by anything
•
MOSFET I-V Characteristics : Linear Region
- since we know what the current will not decrease as VDS increases past VDSAT, we can use this expression to define VDSAT:
- when VDS>(VGS-VT), then IDS in this expression begins to decrease
- we can then define VDSAT = (VGS-VT)
- so now we have the formal limits on the linear region and the validity of this expression:
Linear Region : VGS>VT
0 < VDS < (VGS-VT)
2
0 2
2
GS T DS DSDS
k V V V V
I
linear
MOSFET I-V Characteristics
•
MOSFET I-V Characteristics : Saturation Region
- a MOSFET is defined as being in saturation when:
Saturation Region : VGS > VT
VDS > (VGS-VT)
- an increase in VDS does not increase IDS because the channel is pinched-off
- However, an increase in VGS DOES increase IDS by increasing the channel depth and hence the amount of current that can be conducted.
- measurements on MOSFETS have shown that the dependence of IDS on VGS tends to remain approximately constant around the peak value reached for VDS=VDSAT
- a substitution of VDS=(VGS-VT0) yields:
0
22 0 0
2
02
T GS DS
T GS T
GS T
GS DS
V k V
I
V V
V V
V k V
I
sa t
•
MOSFET I-V Characteristics : IV Curves
- now we have 1st order expressions for all three regions of operation for the MOSFET
Region Conditions IDS
Cutoff VGS < VT Linear VGS > VT
VDS < (VGS-VT) Saturation VGS > VT
VDS > (VGS-VT)
0
22
GS TDS
k V V
I
sat
2
0 2
2
GS T DS DSDS
k V V V V
I
linear
0
cutoff
I
DSMOSFET I-V 2nd Order Effects
•
Channel Length Modulation
- the 1st order IV equations derived earlier are not 100% accurate. They are sufficient for 1st order (gut-feel) hand calculations
- we can modify these IV equations to include other effects that alter the IV characteristics of a MOSFET
- Channel Length Modulation refers to additional IDS current that exists in the saturation mode that is not modeled by the 1st order IV equations
- when the channel is pinched off in saturation by a distance ΔL, a depletion region is created next to the Drain that is ΔL wide
- given enough energy, electrons in the inversion layer can move through this depletion region and into the Drain thus adding additional current to IDS
•
Channel Length Modulation
- we can model this additional saturation current by multiplying the IDS expression by:
- λ is called the channel length modulation coefficient and is determined via empirical methods - this term alters the IDSSAT expression to be:
1 V
DS
GS T
DS
DS
k V V V
I
sat 1 2
2 0
MOSFET I-V 2nd Order Effects
•
Substrate Bias Effect
- another effect that the 1st order IV equations don't model is substrate bias
- we have assumed that the Silicon substrate is at the same potential as the Source of the MOSFET - if this is not the case, then the Threshold Voltage may increase and take more energy to induce
a channel
- we've already seen how we can model the change in threshold voltage due to substrate bias:
- for the IV equations to accurately model the substrate bias effect, we must use VT instead of VT0
F SB F
T
T
V V
V
0 2 2
2
2
2
GS T DS DSDS
k V V V V
I
linear
GS T
DS
DS
k V V V
I
sat 1 2
2
• What is Scaling?
- Moving VLSI designs to new fabrication processes - Shrinking the size of the circuitry
1961
First Planar Integrated Circuit Two Transistors
2001
Pentium 4 Processor 42 Million Transistors
2006
Itanium 2 Dual Processor 1.7 Billion Transistors
Scaling Theory
• Why do we Scale?
1) Improve Performance
• More complex systems
2) Increase Transistor Density
• Reduce cost per transistor & size of system
3) Reduce Power
• Smaller transistors require less supply voltage
300mm wafer
• Scaling Predictions
- In 1965, Gordon Moore of Intel predicted the exponential growth of the number of transistors on an IC.
- Transistor count will doubled every 2-3 years - Predicting >65,000 transistors in 1975
Moore’s Prediction (1965)
Scaling Theory
• More than just a prediction
- Transistor count has doubled every 26 months for the past 30 years
- Today this trend is used to target future process performance and prepare necessary infrastructure (Design Tools, Test, Manufacturing, Engineering Skills, etc…)
• Timeline of Major Events
First Integrated Circuit (Noyce/Fairchild & Kilby/Texas Instruments)
First Transistor (Bell Labs) 1947
1958
Noyce and Moore Form Intel 1968
1971
Intel Introduces the 4004, 1st single chip uP
(2300 transistors)
2006
Intel Ships 1st Billion Transistor uP
Scaling Theory
X Y
• How much can we shrink?
- Chip Area (A)
Chip Area for a Circuit (A) scales following : 1 S
2Note: In addition, the die sizes have increased steadily, allowing
A
1 S 1 S
1
1 1
S
1 S
A
• Full Scaling (Constant-Field)
- Reduce physical size of structures by 30% in the subsequent process
W = Width of Gate
L = Length of Gate
tox = thickness of Oxide xj = depth of doping
- Reduce power supplies and thresholds by 30%
- we define: S ≡ Scaling Factor > 1
- Historically, S has come in between 1.2 and 1.5 for the past 30 years
- sometimes we use √2 = 1.4 for easy math
Full Scaling
• Full Scaling (Constant Field)
- The following quantities are altered during fabrication - we use a prime (‘) to denote the new scaled quantity
- Note that the doping concentration has to be increased to keep achieve the desired Fermi level movement due to doping since the overall size of the junction is reduced
Before After
Quantity Scaling Scaling
Channel Length L L’ = L/S
Channel Width W W’ = W/S
Gate Oxide Thickness tox tox’ = tox/S Junction depth xj xj’ = xj/S Power Supply Voltage VDD VDD’ = VDD/S Threshold Voltage VT0 VT0’ = VT0/S Doping Densities NA NA’ = NA•S