Paralleled DC/DC Converter Via Primary Current Droop Current Sharing Control

Paralleled DC/DC converter via primary current droop current sharing control

J. B. Wang, IEEE Member Rossi Lo and J. H. Chang

Department of Electrical Engineering, AcBel Polytech Inc.,

Ching Yun University of Technology a940201@apitech.com.tw

jbw@cyu.edu.tw jernhuo_chang@apitech.com.tw

Abstract –The paralleling DC/DC converters via primary current droop current sharing control is presented in this paper. Firstly, the steady state droop voltage characteristics are deduced from the output voltage regulation specification and then the parameters of the feedback weighted voltage resistor network can be determined accordingly. Hereafter, the inner loop voltage controller of the converter is designed by using pole placement scheme at a given bandwidth and phase margin.

Furthermore, when single DC/DC converter is operated, one can find that the loop gain characteristics will not affect significantly via output, inductor and primary currents sensing schemes. Unfortunately, the cross coupling effect will occurs at paralleling operation. In order to improve the cross coupling effects, a droop voltage controller is proposed. Finally, an interleaved dual switch forward converter with an output inductor was used to verify the proposed control method. The effectiveness of the proposed scheme will be demonstrated by the simulation and experimental results..

I. INTRODUCTION

The paralleled operating DC/DC converter can have the advantages of improving system reliability, well thermal distribution and high efficiency and thus be widely used in the frond end and load converters. However, to obtain equal current sharing among converters is one of the important characteristics of the paralleling distributed power system. In order to achieve this goal, there are a lot of current sharing schemes have been proposed in the literature [1]. Among them, the droop current sharing method is claimed that is very easy to implement and expand, no wire connection among converters and also having high modularity [1-6].

But, it suffers poor load regulation characteristics due to droop voltage characteristics; furthermore, the accuracy current sharing is primarily depended on the accuracy of the initial referent voltage setting and circuit parameters. In order to obtain the reliability of the equal current sharing capability through the product life cycle, the parameters of the droop voltage control loop and initial referent voltage setting must be stable in the entire life cycle [2].

In the previous studies, most of the droop current sharing control was obtained by sensing the output and inductor current. Therefore, the major object of this paper is to design and analysis the current sharing control of DC/DC converter via primary current droop current sharing control method.

Firstly, a systematic design procedure was deduced to determine the parameters of the feedback resistor network based on the output voltage regulation specification. In the next, the droop current sharing control loop is studied. It can be found that the droop current sharing loop forms an extra control loop to synthesize control efforts from its duty ratio to the other paralleled operation DC/DC converters and result in

cross coupling effect. In order to reduce the cross coupling effect of the droop current sharing scheme, a droop voltage controller is designed to augment in its original voltage controller. Finally, the design procedures of the proposed method will provide, furthermore, the effectiveness of the proposed method will be verified by the simulation and experimental results.

II OUTPUT DROOP VOLTAGE CHARACTERISTICS Fig. 1 shows an interleaved dual switch forward converter (IDSFC) via an output inductor is under studied in this paper, where the symbols V , n ,

_i

V ,

_o

I and

_o

I are denoted as

_i

input voltage, transformer turn ratio, output voltage, output current and input current, respectively. Furthermore, the output stage is comprised of the output inductor L , output capacitor C and equivalent load resistance R . Through distributed power and magnetic devices structure, well thermal management and high efficiency operation can be obtained. It is worth to note the control strategy of the IDSFC shown in Fig. 1 may be used current or voltage mode controls due to one output inductor topology and leads to the primary side currents of the two forward converters can be equal current sharing automatically. Therefore, the voltage mode control scheme is adopted here for ease of implementation. A simple two parameters configuration controller G

_c1

( s ) ,

)

2

( s

G

_c

to incorporate with the primary current droop current sharing controller G

_dr

( s ) was used as a voltage controller,

Fig. 1 The interleaved dual switch forward converter with primary current droop current sharing control

L

C R

+

−

⁺

−

^Vo

Io

Vi

iL

Ii

1 : n

1 : n

i converter dc dc/

+ Vrefi

−

generator signalsphasePWM

two G_c1(s)

) (s G_dr )

(s G_f

)

2(s G_c

R2 R3

R6

R4

R1 C1 C4

R3 R6 C₄

droop V

V

o

I

o max

,

V

o

min ,

V

o

max , Io max

5 , . 0 I_o margin

margin

point set maximum

point set minimum o*

V

which is comprised of a simple operational amplifier, resistors R

1

to R

₆

and capacitors C

₁

and C

₄

. For simplicity, the droop voltage current sharing controller is used the injected voltage method to adjust output voltage [7]. There is also a low pass filter G

_f

(s ) to sense input primary current and to generate the designed droop voltage command with respect to different load currents so the equal current sharing can be obtained among the DC/DC converters.

In general, the droop voltage characteristics of a DC/DC converter is depended on output voltage regulation range specification with a predetermined design margin as shown in Fig. 2, where the maximum, nominal and minimum output voltages are denoted as V

_o,max

, V

_o^*

and V

_o,min

, respectively.

Since the steady state droop voltage performance is determined by feedback weighted voltage resistors R

₁

, R

₂

,

R

3

and referent command setting V

_refi

, where the sub index i denotes the ith DC/DC converter, then one can find the steady state output voltage due to droop voltage as

d o refi

o

K

V V V

V =

*

+ Δ

0

=

max

,

(1)

d droop cs d

o refi

o

K V K K

V V V

V =

*

− Δ

0

= −

min

,

(2)

where 2 i = 1 or and

3 2 3 1 2 1

3 1

R R R R R R

R K

_d

R

+

= + ,

3 2 3 1 2 1

2 1

R R R R R R

R K

_cs

R

+

= +

From (1) and (2), the output voltage deviation Δ V

₀

due to droop voltage characteristics can be expressed in term of droop voltage as

3 2

2 R V R

V

_o

=

_droop

Δ (3) As a result, the design procedures of the DC droop voltage characteristics can be summaried as

(1)Let R

1

′ = kV

_refi

and ^k > 0 , where R

₁

′ = R

₁

R

₃

( R

₁

+ R

₃

) . (2)From the maximum output voltage listed in (1), K

_d

and

R

1

′ , the resistance R

2

can be determined.

(3)When the specification of the output voltage deviation and droop voltage are given, the resistance R

₁

and R

₃

can be found from (3) and R

₁

′ .

Fig. 2 The droop voltage characteristics of a DC/DC converter

Finally, the resistance values of the R

₁

, R

₂

and R

₃

can be determined in according to output voltage regulation specification and designed primary current droop voltage in the proposed design method.

III CONTROLLER DESIGN AND ANALYSIS Fig. 3 is the equivalent small signal circuits of the ith DC/DC converter of the paralleled power system from the secondary side viewpoint, where the nominal duty ratio, equivalent secondary voltage, load current, equivalent series resistance and output wire resistance are V

_g

, D , I

_oi

, r and r

w

, respectively, and V

_g

= V

_i

n [8]. Furthermore, the lower case symbols v

_g

, d

_i

, i

_i

, i

_o

and i

_oi

are denoted the small signal variables with respect to the aforementioned upper case notations. It is worth to note that the output wire connected resistance r

_w

is very smaller than the load resistance R and thus can be neglected in the following analysis. Therefore, the output voltage v

_oi

of the ith DC/DC converter can be assumed equal to the actual load voltage v

_o

. From Fig. 3, the output current of the ith DC/DC converter I

_oi

is equal to

o

2

I in an equal current sharing condition and I

_o

is the total load current. Furthermore, it shows an extra coupling effect between input current i

_i

and duty ratio d

_i

. As a result, the droop current sharing control performance will be different to the droop characteristics via output and inductor current feedback scheme. From Fig. 3 and assuming the perturbation of the secondary voltage is neglected, one can find that the key transfer functions of DC/DC converter controlled by duty ratio to be used for design and analysis latterly are

2

) 1 ) (

( Δ

= +

= V R sCr

s d H

v

g

i

o

(4)

2

2 (2 ) ( ) )

) (

( Δ

+ + +

= +

= Ls

R Rr L s r R LC s s V d F

i g

i dLi

Li

(5)

2

2 ( ) ( ) )

) (

( Δ

+ + +

= +

= Ls

R Rr L s r R LC s s V d F

i g

i doi

oi

(6)

2 2 2 2 2

3 (1 ) ( 2 2 ) (2 ) )

( ) (

Δ

+ + + + + +

+

=

=

nLs

R RrC L s r R LC

s C

L s D V

s d F

i

C RL rR

g i di i

(7)

2

2

1 )

) (

( Δ

+ +

= −

= Ls

sCr LC s R s V

d F

i

g

j doj

oi

(8)

2

) 1 ) (

( Δ

+

= −

= Ls

sCr R s V

d F

i

g

j dLj

Li

(9)

n DF s d F

i

dj dLj

j

i

= ( ) = / (10)

+

−

−

⁺

vg

nii 1:D

i oid I

i gd

V L

C

R r

io

iLi i_oi

i converter dc dc/

j converter dc dc/ vo

−

0 + refi= v

) (s G_dr

−

^di

ii

vo

) (s G_f

) (s H

) (s F_di +

) (s F_dj

−

dj

io

+

−

Zout K

Tv

droop T

vc

−

0 + refj= v

) (s G_dr

−

^dk

ij

) (s G_f

) (s H

) (s F_dk +

) (s F_dj

−

di c K

v converter DC DC ith /

converter DC DC jth /

)

1(s G_c

)

2(s G_c

)

1(s G_c

)

2(s G_c Fig. 3 The small signal model of the paralleled DC/DC converter

2

) 1 (

Δ

= +

= sLR sCr

i Z v

o

out o

(11) where

) 1 2

) ((

2

2 ) 2 ( ) 2 (

2 2 2 2

+ +

≅

+ +

+ +

= Δ

s s R

R RCr L s r R LC s

n

ξ ω

n

ω

(12)

and

n

= 1 LC

ω ^,

n LR

Cr ξ ω

2 ) (

₂

2

= +

From Fig. 1, one can find the equivalent control block diagram of the paralleled operation DC/DC converters system can be obtained from Fig. 4. The voltage and droop loop gains of the ith DC/DC converter operating alone are denoted as T and

_v

droop

T , respectively, and can be derived as KH G G

T

_v

=

_{c1 c2}

(13)

di f dr c

droop

G KG G F

T =

₁

(14) where K is denoted as the gain of the PWM comparator. As a result, the total loop gain of the single ith DC/DC converter is

droop v

loop

T T

T = + (15) It is worth to note that the control performance of the ith DC/DC converter is affected by the cross coupling effect of the droop loop gain T

_droop

by the other converters and thus required to further investigation. In order to reduce the coupling effects due to extra droop voltage loop, properly design the droop voltage controller G

_dr

(s ) is indispensable.

In general, the voltage loop of the single DC/DC converter must be designed firstly for a redundant power system. After that, the outer current sharing loop control is designed so the well current sharing control performance can be obtained.

(1) Voltage loop design

From Figs. 1 and 4, the duty ratio to output voltage transfer function of the single converter can be obtained from (4) as

1 ) ( 2 ) (

) 1 (

) (

2 1 3

+ +

= +

n n

g z

s s

V s s

H

ζ ω ω

ω (16) and the two parameter configuration controller are

) 1 (

) 1 (

) (

2 1 1 1

+

= +

p

c

s s

z

s s

G

α ω ω

) 1 (

) 1 (

) (

2 2 2 2

+

= +

p

c

K s

z

s s G

ω

ω ₍₁₇₎

There are two pole-zero assignment methods suggested in the

literature [8, 9]. Basically, it assigns a pole ω

_p1

to cancel the zero ω

_z3

produced by the equivalent series resistance of the output capacitor and uses two zeros ω

_z2

^and ω

z3

to reduce the resonant peak effect caused by the output filter. At last, to place a pole ω

_o

is for desired gain crossover frequency and phase margin, and another pole ω

_p2

is used to filter out the high frequency switching noise. Using aforementioned pole assignment scheme, the desired voltage loop gain can be simplified as

) 1 )(

(

1

2 0

≈ +

p o

v

s s

T

ω ω

2 2

K

K V

_g

o

α

ω = (18) However, the parameter variation of the transfer function

) (s

H is occurred at different load current operating condition and led to modeling errors. In order to reduce the modeling error, it is suggested to increase gain margin of the DC/DC converter. If the gain margin is designed to greater than 10dB, the control performance due to parameters mismatch can be reduced significantly.

(2)Droop current sharing controller design

If the droop controller G

_dr

(s ) is a simple resistor R

₃

as in the previous study [2], the Bode plots of the loop gain transfer function (15) via output and primary current feedback droop schemes for the single ith DC/DC converter are shown in Fig. 5. From Fig. 5, one can find the gain crossover frequency of the designed DC/DC converter voltage loop gain

Fig. 4 the equivalent control block diagram of the paralleled operation DC/DC converters system

Gain / dB Y2

-80 -60 -40 -20 0 20 40 60 80

freq / Hertz

10 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k

Phase / degrees

Y1

-150 -100 -50 0 50 100 150

gain i T_loop(_o)−

phase i T_loop(_o)− gain

i T_loop(_i)−

phase i T_loop(_i)−

0 10 20 30 40 50 60 70

11.8 11.9 12 12.1 12.2 12.3 12.4 12.5

Vo

A V

case nominal 1

converter DC/DC

2 converter DC/DC

Fig. 5 The loop gains of the DC/DC converter via output and primary droop current sharing controls

T

Loop

of both cases is 10kHz and phase margin is 50

⁰

. It is interest to find that loop gain T

_loop

( i

_i

) by using primary current droop current sharing scheme is similar to the output current droop current sharing scheme T

_loop

( i

_o

) , but using primary current droop current sharing method will reduce 3

⁰

of the phase margin for single converter operation. In the preliminary simulated result showed that the control performance of the DC/DC converter seems not to affect by cross effect due to the droop voltage controller. In order to improve the effects of the cross coupling effects, the paralleled DC/DC converters are investigated in the following. Let the cross couple voltage loop from other DC/DC converters be denoted as T

_cross

. Using (13), (14) and let the designed droop controller ) G

_dr

(s is set equal to k

_d

G

_c2

( s ) , where

3 2

/ R R

k

_d

= . Finally, the total loop gain T

_loop

of the ith DC/DC converter at paralleled operating can be simplified as

) 1

( W

T

T

_loop

=

_v

+ Δ , Δ W = k

_d

G

_f

F

_di

/ H (19) As a result, the total loop gain T

_loop

of the ith DC/DC converter at paralleled operation will be similar to original designed loop gain profile approximately by proposed droop voltage controller G

_dr

(s ) = k

_d

G

_c2

( s ) and proper designed low pass filter G

_f

(s ) .

IV SIMULATIONS AND EXPERIMENTS Design case

After detailed the design and analysis methodology, the specified 800W output power with 12V/66A is used to evaluate aforementioned primary current droop current sharing scheme. The key design parameters are listed as follow.

Primary side DC bus voltage V =385V

_i

Primary switching frequency f =125kHz

_s

Nominal output voltage V =12V

_o

Nominal output current I =66A

_o

Transformer PQ32/30 N =20 turns,

_P

N =1 turn and n =20

_s

Output inductor MS10675 N =5 turns ,

_c

L = 1 . 94 uH Output capacitance C =5400 uF , esr=4 m Ω

Nominal duty ratio D =0.62 in the secondary side of the interleaved dual switch forward converter with an output inductor

The gain of the PWM comparator K =0.25

In general, the nominal output voltage of the designed DC/DC converter and output voltage regulation specification is 12.2V and ± 3% tolerance, respectively. Let droop voltage V

_droop

be 5V at full load current operation condition. Therefore, the design margin is set as 1% of the nominal voltage. In according to the steady state droop voltage design procedures, let V

_refi

and k be 2.5V and 1, respectively, and then from (1) to (3), one can find the parameters of the feedback weighted voltage network R

₁

, R

₂

and R

₃

are 2.563k Ω ^{, 9.94k} Ω ^and 101.844k Ω , respectively. But, it is very hard to find the designed resistance in the commercial part list. Therefore, the parameters of the resistors R

₁

, R

₂

and R

₃

are chosen as 2.56k Ω ^{, 10k} Ω ^{and 100k} Ω with 5% tolerance as an alternative selection. Fig. 6 shows the steady state droop voltage characteristics of the output voltage with respect to different load currents. It shows the output voltage of the designed DC/DC converters can follow the designed droop voltage characteristics with a smaller error. The results were demonstrated the effectiveness of the proposed designed proced ures. Once the stead y state dro op vo ltage characteristics have been determined, the control system design and analysis of the paralleled DC/DC converter was carried out subsequently. Accordingly, one can obtain the equivalent secondary voltage V

_g

of the IDSFC is 19V.

Furthermore, the 30A load current of the IDSFC is chosen as a nominal model to design voltage controller. Let the desired loop gain model (18) is designed to have at least 45

⁰

phase margin and 10kHz bandwidth approximately. Following the pole placement design procedures, the poles and zeros of the voltage controller and the parameters of the voltage controller

Fig. 6 The droop voltage characteristics of the DC/DC converters

10¹ 10² 10³ 10⁴ 10⁵ -40

-20 0 20 40 60 80

Hz A

15 →From30A→left45toA→right65A

dB Magnitude

10¹ 10² 10³ 10⁴ 10⁵

-150 -100 -50 0 50 100

150 degree phase

Hz A

15 →From30A→left45toA→right65A

can be estimated and listed in the appendix. Using Simplis circuit simulator, the Bode plot of the DC/DC converter is depicted in Fig. 5. It can find the phase margin is 50

⁰

and the gain cross-over frequency is around 10kHz that is quite similar to previous design specification. After simulation has verified the loop gain of the DC/DC converter, the actual Bode plot measurement was carried out subsequently via AP102B network analyzer made by AP Instrument which was used an isolated transformer to inject swept sinusoidal signal into converter. Fig. 7 shows the Bode plot of the DC/DC converter with primary current droop current sharing control. The measurement results were also depicted the gain crossover frequency is around 10kHz, furthermore, the phase response was shown in Fig. 7(b) with 50

⁰

phase margin.

In order to demonstrate the proposed design method, a measurement of the paralleled operating DC/DC converters in hot swap operation is provided and shown in Fig. 8. Fig. 8(a) depicts the hot swap operation of the DC/DC converter at a 66A full load current. A very good dynamic current sharing response can be observed; furthermore, equal current sharing among the DC/DC converter can also be obtained.

Furthermore, Fig. 8(b) and (c) are shown the Bode plot of the paralleled DC/DC converter and also provided 10kHz bandwidth and 50

⁰

phase margin as the original designed loop gain characteristics.

V CONCLUSIONS

A systematic method to design and analysis of the droop current sharing control via primary current sensing is presented in this paper. Through the output voltage regulation specification, the desired feedback weighted voltage resistors can be determined. Then, the voltage and droop voltage controllers are designed in according with the small signal modeling of the paralleled DC/DC converter system.

VI ACKNOWLEDGEMENT

Special thanks to National Science Council of Taiwan support a research project: NSC98-2221-E231-024.

VII REFERENCES

[1] Shiguo Luo, Zhihong Ye, Ray-Lee Lin and F. C. Lee, “A classification and evaluation of paralleling methods for power supply modules,” PESC 99 Record of 30th Annual IEEE Power Electronics Specialists Conference, vol. 2, pp. 901 – 908, 1999.

[2] B. T. Irving and M. M. Jovanovic, “Analysis, design, and performance evaluation of droop current-sharing method,” APEC 2000 Conference Proceedings of Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition, vol. 1, pp. 235 - 241, 2000.

[3] Jung-Won Kim, Hang-Seok Choi and Bo Hyung Cho, “ A novel droop method for converter parallel operation,” IEEE Transactions on Power Electronics, vol. 17,Issue 1, pp. 25-22, 2002.

[4] Zhou Xunwei, Xu Peng and F. C. Lee, “A novel current-sharing control technique for low-voltage high-current voltage regulator module applications,” IEEE Transactions on Power Electronics, vol.

12, pp. 1153-1162, 2000.

[5] J. A. A. Qahouq, Lilly Huang, Lilly and D. Huard, “Sensorless Current Sharing Analysis and Scheme for Multiphase Converters,”

PESC 2007 IEEE Power Electronics Specialists Conference, pp.

2029-2036, 2007.

[6] Hong Mao, Liangbin Yao, Caisheng Wang and I. Batarseh, “Analysis of Inductor Current Sharing in Nonisolated and Isolated Multiphase dc–dc Converters,“ IEEE Transactions on Industrial Electronics, vol.

54, Issue 6, pp. 3379-3388, 2007.

[7] J. B. Wang and Jerry Lee, “Weighted voltage control design for DC/DC converter,” ICIT 2005 Proceeding of IEEE International Conference on Industrial Technology, pp.1319-1324, 2005.

[8] R. W. Erickson and D. Maksimovic, Fundamentals of power electronics, 2e, Kluwer Academic Publishers, 2001.

[9] Marty Brown, Power supply cookbook, Butterworth Heinemann, 1994.

APPENDIX

Circuit parameters of the voltage controller G

_dr

(s ) and low pass filter G

_f

(s )

1 the voltage controller G

_dr

(s )

R

1

R

₂

R

₃

R

₄

R

₅

R

₆ 2.56k

Ω

^10k

Ω

^100k

Ω

^1k

Ω

^33k

Ω

^10k

Ω

C

1

C

₂

C

₃

C

₄ 4700pF 6800pF 680pF 440pF

(a)

(b)

Fig.. 7 The Bode plot of the DC/DC converter with primary current droop current sharing control

1

Io

2

Io

2

Vo

A 60

A 30

V 0

V 12

ms 5

10¹ 10² 10³ 10⁴ 10⁵

-20 -10 0 10 20 30 40 50 60

Hz dB

current load A 30

Magnitude

10¹ 10² 10³ 10⁴ 10⁵

-60 -40 -20 0 20 40 60 80 100 120

current Hz load A 30

phase degree

(a)

(b)

(c)

Fig. 8 (a)The hot swap operation of the paralleled DC converter; (b) the magnitude response; (c)the phase response of the paralleled DC/DC converter via primary current droop current sharing control

2 low pass filter G

_f

(s )

) (s G

_f

=

1 ) )

( (

1

2 2 2 1 1 2

1 2

2

R

f1

R

f

C

f

C

f

+ s R

f

C

f

+ C

f

+ R

f

C

f

+ s

1

R

f

R

_f2

C

_f1

C

_f2 1k

Ω

¹⁰⁰

Ω

^0.1

μ

^{F 0.01}

μ

^F

5 1 23

1

R

p

= C

ω ,

4

2 1

1

R

p

= C

ω ,

5

1 2

1

R

z

= C

ω ,

) (

1

4 2

2

C

1

R R

z

= +

ω , α

₂

= C

₂

+ C

₃

,

3 2

3

23

C

2

C

C C C

= + ,

2

2

R

K = ,

2 2

K

K V

_g

o

α

ω =

3 The desired location of the poles and zeros

ω

0 =66845rad/sec,

ω

p1 =49019.6rad/sec,

ω

p2 =212765.95rad/sec, 1

ω

z =4456.33rad/sec,

ω

z2=20263.24 rad/sec