68HC05 INTERNAL DATA BUS

An Introduction to Motorola’s An Introduction to Motorola’s 68HC05 Family of 8-Bit

68HC05 Family of 8-Bit Microcontrollers Microcontrollers

 Table of Contents Table of Contents

Ç CPU Overview

Ç Instruction Set

Ç Addressing Modes

Ç Sample HC05 Code Example

Ç Smart Light Dimmer Application Example

Ç Bicycling Computer Application Example

Ç Other 68HC05 Family Peripherals

 68HC05 Memory Organization 68HC05 Memory Organization

$xxF0

$0100

$xx00

$0020

$0000

$0200

$0201

$0202

$0203

$0204

$0205

$0206

$0207

LDA $0400,X STA $11 JSR $1120

RESET VECTOR ($0100) SWI VECTOR

($02F0) IRQ VECTOR

($03CD) I/O & CONTROL

REGISTERS

RAM

ROM/EPROM

BOOT ROM

VECTORS

$CD

$11

$20

$B7

$11

$D6

$04

$00

$xxFA

$xxFB

$xxFC

$xxFD

$xxFE

$xxFF

$03

$CD

$02

$F0

$01

$00

 68HC05 Programmer’s Model 68HC05 Programmer’s Model

Half Carry Flag Interrupt Mask Negative Flag Zero Flag Carry/Borrow Flag

Accumulator (A)

7 6 5 4 3 2 1 0

Index Register (X)

7 6 5 4 3 2 1 0

Stack Pointer (SP)

7

1

0

1

6 5 4 3 2 1

15

0

8

0 0

14

0

13

0

12

0

11

0

10

0

9

Program Counter (PC)

7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8

Condition Code Register (CCR)

7

1

0

C 1

6

1

5

H

4

I

3

N

2

Z

1

 Program Counter Operation Program Counter Operation

P ro g ra m Co unte r Opc o de /Ope ra nd Re a d Ins truc tio n

$ 1 0 0 0 $ B6 LDA $ 8 0

$ 1 0 0 1 $ 8 0

$ 1 0 0 2 $ 4 7 ASRA

$ 1 0 0 3 $ 4 7 ASRA

$ 1 0 0 4 $ 4 C I NCA

$ 1 0 0 5 $ B7 STA $ 8 0

$ 1 0 0 6 $ 8 0

$ 1 0 0 7 $ CD J SR $ 1 3 FE

$ 1 0 0 8 $ 1 3

$ 1 0 0 9 $ FE

The program counter (PC) increments by one after each byte of an instruction or

operand is read. Jumps, branches, returns, and interrupts load the PC with a new value.

 Stack Pointer Operation Stack Pointer Operation

‘xx’ indicates that contents of memory location are not known

xx

$00FF

$00FE

$00FD

$00FC

before

JSR SUBROUTINE

SP

xx

xx

xx

Low Byte of Return Address

xx

xx

$00FF

$00FE

$00FD

$00FC

High Byte of Return Address

SP after

JSR SUBROUTINE

Low Byte of Return Address

xx

xx High Byte of Return Address

$00FF

$00FE

$00FD

$00FC

SP after

RTS

$00FF xx

$00FE

$00FD

$00FC

before

INTERRUPT

SP

xx xx xx

Low Byte of Return Address

Index Register Accumulator

$00FF

$00FE

$00FD

$00FC

High Byte of Return Address

SP after

INTERRUPT

Low Byte of Return Address

High Byte of Return Address

$00FF

$00FE

$00FD

$00FC

SP after

RTI

xx Condition Code

Register xx

$00FB

$00FA xx

$00FB

$00FA

Index Register Accumulator Condition Code

Register xx

$00FB

$00FA

 68HC05 Instruction Set — Part 1 68HC05 Instruction Set — Part 1 Memory Reads & Writes

LDA load the accumulator LDX load the index register STA store the accumulator STX store the index register

Register Transfers

TAX transfer the accumulator to the index register TXA transfer the index register to the accumulator

Clear Memory & Registers

CLR clear a memory location CLRA clear the accumulator CLRX clear the index register

 68HC05 Instruction Set — Part 2 68HC05 Instruction Set — Part 2 Arithmetic

ADD add to the accumulator

ADC add to the accumulator with carry SUB subtract from the accumulator

SBC subtract from the accumulator with borrow MUL multiply the accumulator by the index register

NEG negate (take the 2’s complement of) a memory location NEGA negate (take the 2’s complement of) the accumulator NEGX negate (take the 2’s complement of) the index register

 68HC05 Instruction Set — Part 3 68HC05 Instruction Set — Part 3 Decrement & Increment Memory & Registers

INC increment a memory location by one INCA increment the accumulator by one INCX increment the index register by one DEC decrement a memory location by one DECA decrement the accumulator by one DECX decrement the index register by one

Boolean Logic

AND logical AND of the accumulator and an operand ORA inclusive OR of the accumulator and an operand EOR exclusive OR of the accumulator and an operand

COM take the one’s complement of (invert) a memory location COMA take the one’s complement of (invert) the accumulator COMX take the one’s complement of (invert) the index register

 68HC05 Instruction Set — Part 4 68HC05 Instruction Set — Part 4 Shift Memory & Registers

ASL arithmetically shift a memory location left by one bit ASLA arithmetically shift the accumulator left by one bit ASLX arithmetically shift the index register left by one bit ASR arithmetically shift a memory location right by one bit ASRA arithmetically shift the accumulator right by one bit ASRX arithmetically shift the index register right by one bit LSL logically shift a memory location left by one bit

LSLA logically shift the accumulator left by one bit LSLX logically shift the index register left by one bit LSR logically shift a memory location right by one bit LSRA logically shift the accumulator right by one bit LSRX logically shift the index register right by one bit

 68HC05 Instruction Set — Part 5 68HC05 Instruction Set — Part 5 Rotate Memory & Registers

ROL rotate a memory location left by one bit ROLA rotate the accumulator left by one bit ROLX rotate the index register left by one bit ROR rotate a memory location right by one bit RORA rotate the accumulator right by one bit RORX rotate the index register right by one bit

Test Registers & Memory

BIT bit test the accumulator and set the N or Z flags CMP compare an operand to the accumulator

CPX compare an operand to the index register

TST test a memory location and set the N or Z flags TSTA test the accumulator and set the N or Z flags TSTX test the index register and set the N or Z flags

 68HC05 Instruction Set — Part 6 68HC05 Instruction Set — Part 6 Branches on Condition Code Register Bits

BCC branch if carry clear (C = 0) BCS branch if carry set (C = 1) BEQ branch if equal (Z = 0) BNE branch if not equal (Z = 1)

BHCC branch if half carry clear (H = 0) BHCS branch if half carry set (H = 1) BHI branch if higher (C or Z = 0) BHS branch if higher or same (C = 0) BLS branch if lower or same (C or Z = 1) BLO branch if lower (C = 1)

BMI branch if minus (N = 1) BPL branch if plus (N = 0)

BMC branch if interrupts are not masked (I = 0) BMS branch if interrupts are masked (I = 1)

 68HC05 Instruction Set — Part 7 68HC05 Instruction Set — Part 7 Other Branches

BIH branch if IRQ pin is high BIL branch if IRQ pin is low

BRA branch always

BRN branch never

BSR branch to subroutine and save return address on stack

Single Bit Operations

BCLR clear the designated memory bit BSET set the designated memory bit

BRCLR branch if the designated memory bit is clear BRSET branch if the designated memory bit is set

 68HC05 Instruction Set — Part 8 68HC05 Instruction Set — Part 8 Jumps & Returns

JMP jump to specified address

JSR jump to subroutine and save return address on stack RTS pull address from stack and return from subroutine RTI pull registers from stack and return from interrupt

Miscellaneous Control

CLC clear the condition code register carry bit SEC set the condition code register carry bit

CLI clear the condition code register interrupt mask bit SEI set the condition code register interrupt mask bit SWI software initiated interrupt

RSP reset the stack pointer to $00FF

NOP no operation

WAIT enable interrupts and halt the CPU

STOP enable interrupts and stop the oscillator

 Addressing Modes — Summary Addressing Modes — Summary

Several different addressing modes are available to support the data requirements of different 68HC05 instructions.

Inherent (INH)

Immediate (IMM)

Extended (EXT)

Direct (DIR)

Indexed, 16-Bit Offset (IX2)

Indexed, 8-Bit Offset (IX1)

Indexed, No Offset (IX)

Relative (REL)

Bit Set and Clear (BSC)

Bit Test and Branch (BTB)

 Addressing Modes — INH Addressing Modes — INH

The operand of an instruction that uses inherent addressing is implied by or inherent in the instruction’s opcode.

Some instructions explicitly name registers…

ASLA, CLRX, DECA, INCX, ROLA, RORX, RSP, TAX, TXA

Others explicitly name condition code register bits…

CLC, CLI, SEC, SEI

Still others affect one or more unnamed registers…

MUL, RTI, RTS, STOP, SWI, WAIT And some have no operands whatsoever…

NOP

 Addressing Modes — IMM Addressing Modes — IMM

The operand of an instruction that uses immediate addressing immediately follows the instruction’s opcode in memory.

Immediate addressing is often using with LDA and LDX… LDA #$40

LDX #$80

As well as with ADC, ADD, SBC, and SUB for arithmetic operations…

ADC #$01 SUB #$02

…CMP, CPX, and BIT for register comparison and testing…

BIT #$C4 CPX #$FF

And with AND, EOR, and ORA for combinatorial logic…

AND #$03 ORA #$FC

 Addressing Modes — EXT Addressing Modes — EXT

Instructions that use extended addressing can read from or write to any location in the 68HC05 memory map.

Extended addressing is often used with LDA, LDX, STA, and STX… LDA $4000

STX $0130

As well as with ADC, ADD, SBC, and SUB for arithmetic operations…

SBC $01F1

…CMP, CPX, and BIT for register comparison and memory testing…

CMP $08C3

…with AND, EOR, and ORA for combinatorial logic…

EOR $0325

And with JMP and JSR for program flow changes…

JMP $1200 JSR $3040

 Addressing Modes — DIR Addressing Modes — DIR

Instructions that use direct addressing can only read from or write to memory locations

$00 to $FF.

All read-modify-write instructions support direct addressing…

ASL $00 ASR $FF CLR $02 COM $FD DEC $04 INC $FB LSL $06 LSR $F9 NEG $08 ROL $F7 ROR $0A TST $F5

All instructions that support extended addressing also support direct addressing.

 Addressing Modes — IX2 Addressing Modes — IX2

When indexed addressing with 16-bit offsets is used, target addresses are calculated by taking the unsigned sum of the contents of the index register and the 16-bit offset.

Example instructions include loads and stores…

LDA $4000,X STX $03F8,X

…arithmetic and combinatorial logic operations…

SBC $01F1,X EOR $18FF,X

…CMP, CPX, and BIT for register comparison and memory testing…

CMP $08C3,X

And JMP and JSR for program flow changes…

JSR $0F4C,X

The same group of instructions that can use extended addressing is also the only group of instructions that can use indexed addressing with 16-bit offsets.

 Addressing Modes — IX1 Addressing Modes — IX1

Instructions that use indexed addressing with 8-bit offsets can read from or write to any memory location between $0000 and $01FE inclusive.

All read-modify-write instructions support this addressing mode…

ASL $00,X ASR $FF,X CLR $02,X COM $FD,X DEC $04,X INC $FB,X LSL $06,X LSR $F9,X NEG $08,X ROL $F7,X ROR $0A,X TST $F5,X

Likewise, all instructions that can use direct addressing can also use indexed addressing with 8-bit offsets.

 Addressing Modes — IX Addressing Modes — IX

The target address for an instruction that uses indexed addressing without an offset is simply the contents of the index register zero extended to 16 bits.

All read-modify-write instructions support this addressing mode…

ASL ,X ASR ,X CLR ,X COM ,X DEC ,X INC ,X LSL ,X LSR ,X NEG ,X ROL ,X ROR ,X TST ,X

All instructions that can use direct addressing and indexed addressing with 8-bit offsets can also use indexed addressing without offsets.

 Addressing Modes — REL Addressing Modes — REL

Relative addressing is used only by branch instructions to calculate the target address of a change in program flow relative to the value of the program counter (PC).

Each branch instruction requires two bytes of storage — one for the branch opcode and one for the signed two’s complement 8-bit relative offset.

This offset is relative to the address of the next instruction, which is the address of the branch instruction plus two.

Consider the following line of code…

HERE BEQ THERE

If the label HERE equates to address $1000 and this is a FORWARD branch, the target address can be between $1002 (offset of $00) and $1081 (offset of $7F).

Similarly, if the label HERE equates to address $1000 and this is a REVERSE branch, the target address can be between $0F82 (offset of $80) and $1000 (offset of $FE).

 Bit Set and Clear — BSC Bit Set and Clear — BSC

The bit set and clear (BSC) addressing mode is used only by the BSET and BCLR instructions. Like other read-modify-write instructions, BSET and BCLR take a direct address. There are eight BSET and BCLR opcodes, one for each bit in a byte.

Consider the following line of code…

BSET n, $00

In this example, 0

≤

ⁿ

≤

7 and denotes one of the eight bits in a byte. This assembles to one of the BSET opcodes (calculated at $10 + 2n) and the direct address $00.

BCLR instructions are formed the same way…

BCLR n, $00

As above, 0

≤

ⁿ

≤

7 and denotes one of the eight bits in a byte. This assembles to one of the BCLR opcodes (calculated at $11 + 2n) and the direct address $00.

 Bit Test and Branch — BTB Bit Test and Branch — BTB

The bit test and branch (BTB) addressing mode is used only by the BRSET and BRCLR instructions. BRSET and BRCLR take a direct address and have eight opcodes to denote each bit in a byte, just like BSET and BCLR.

Consider the following line of code…

BRSET n, $00, TARGET

In this example, 0

≤

ⁿ

≤

7 and denotes one of the eight bits in a byte. This assembles to one of the BRSET opcodes (calculated at $00 + 2n), the direct address $00, and an

offset to TARGET relative to the address of the instruction that follows BRSET. BRCLR instructions are formed the same way…

BRCLR n, $00, TARGET

As above, 0

≤

ⁿ

≤

7 and denotes one of the eight bits in a byte. This assembles to one of the BRCLR opcodes (calculated at $01 + 2n) , the direct address $00, and an offset to

 A Sample 68HC05 Program A Sample 68HC05 Program

The sample function that follows finds the cosine of an angle between 0 and 180 degrees inclusive by interpolating the result from a look up table.

The table consists of 46 elements representing the cosine of every fourth degree, again, from 0 to 180 degrees inclusive, scaled by 127.

A simple linear interpolation is performed using these standardized equations:

Cosine of Given θ = Cosine of Known θ - DELTA

DELTA =

Cosine of Known Lower θ - Cosine of Known Upper θ

Known Upper θ - Known Lower θ × (Given θ - Known Lower θ)

 Sample Program Listing — Part 1 Sample Program Listing — Part 1

* The function begins by reading the given angle, THETA, from

* on-chip RAM (using direct mode addressing) and dividing it by

* four. This is used as an offset into the look up table.

FIND_COSINE ldx THETA lsrx

lsrx

* Using indexed addressing with a 16-bit offset, the cosine of

* the known lower angle is loaded into the accumulator, and the

* cosine of the known upper angle is subtracted from it. This

* difference is then divided by four, which is the difference

* between the known upper angle and the known lower angle. Save

* this result in the index register to take the delta product.

lda COSINE_TABLE,X

sub COSINE_TABLE + 1,X lsra

lsra tax

 Sample Program Listing — Part 2 Sample Program Listing — Part 2

* Take the difference between the given angle and the known lower

* angle by logically ANDing the given angle with three. Now take

* the product of the two DELTA terms. MUL stores its product MSB

* in the index register and LSB in the accumulator.

lda THETA and #$03 mul

* Because this product is always a small number, it will reside

* only in the accumulator; the index register will be zero. Once

* again, use the given angle to look up the cosine of the known

* lower angle. Negating the accumulator and adding the cosine of

* the known lower angle returns the cosine of the given angle.

ldx THETA lsrx

lsrx nega

add COSINE_TABLE ,X sta THETA_COSINE

 Sample Program Listing — Part 3 Sample Program Listing — Part 3

* This is the look up table used for the cosine interpolation

* function.

* 0, 4, 8, 12, 16, 20, 24, 28, 32 COSINE_TABLE fcb $7F, $7E, $7D, $7C, $7A, $77, $74, $70, $6B

* 36, 40, 44, 48, 52, 56, 60, 64, 68 fcb $66, $61, $5B, $54, $4E, $47, $3F, $37, $2F

* 72, 76, 80, 84, 88, 92, 96, 100, 104 fcb $27, $1E, $16, $0D, $04, $FC, $F3, $EA, $E2

* 108, 112, 116, 120, 124, 128, 132, 136, 140 fcb $D9, $D1, $C9, $C1, $B9, $B2, $AC, $A5, $9F

* 144, 148, 152, 156, 160, 164, 168, 172, 176 fcb $9A, $95, $90, $8C, $89, $86, $84, $83, $82

* 180

fcb $81

 Smart Light Dimmer Application Smart Light Dimmer Application

Ç Smart Light Dimmer

Õ MC68HC705KJ1 Overview Õ Schematics

Õ Input & Output Ports

Õ Multifunction Timer

 MC68HC705KJ1 Features MC68HC705KJ1 Features

Ç 16-Pin Plastic DIP, Ceramic DIP, and SOIC Packages

Ç 4 MHz Maximum Operating Frequency at 5 Volts

Ç 1240 Bytes of EPROM

Ç 64 Bytes of RAM

Ç Multifunction Timer with 15-Stage Ripple Counter

Ç Computer Operating Properly (COP) Watchdog Timer

Ç 10 Bidirectional I/O Pins

Õ Software Programmable Pulldown Devices on All I/O Pins Õ 10 mA Current Sink Capability on All I/O Pins

Õ Optional Active High Interrupt Capability on 4 I/O Pins

Ç Selectable Sensitivity on External Interrupt Request Line

Ç On-Chip Oscillator for Crystal, Ceramic Resonator, or Resistor-Capacitor Network

Ç Internal Steering Diode and Pullup Device from RESET Pin to VDD

 Smart Light Dimmer Schematic Smart Light Dimmer Schematic

D4 zener 5.6V C3 100 µF +5 vdc

common D6

1N914

C2 0.22 µF

R16 820 Ω 0.5 W

light bulb

hot terminal

neutral terminal R5

100 kΩ R8

220 kΩ R6

100 kΩ R7

220 kΩ common

R9 22 kΩ

FIRE_TRIAC

NEGATIVE_ZERO_CROSSING

POSITIVE ZERO CROSSING

MC68HRC705KJ1

VDD

IRQ

PA0

VSS

PA7

PA6 OSC1 OSC2

M1 M2

R17 47 kΩ R4

100 Ω

 ^{Bi Bi} -directional Port Pin Logic -directional Port Pin Logic

MASK-SPECIFIED PULLUP LOGIC

DATA DIRECTION

OUTPUT DATA

PULLDOWN INHIBIT LOGIC

READ DATA DIRECTION

WRITE DATA DIRECTION

WRITE PORT DATA

READ PORT DATA

RESET

PULLUP INHIBIT LOGIC

68HC05 INTERNAL DATA BUS

MASK-SPECIFIED PULLDOWN LOGIC

I/O PIN

 Multifunction Timer (MFT) Multifunction Timer (MFT)

TIMER STATUS/CONTROL REGISTER (TSCR)

TMR0 TMR1 TMR2 TMR3 TMR4 TMR5 TMR6 TMR7

OVERFLOW DETECT

˜2

˜2

˜2

˜2

˜2

˜2

˜2

RT0 RT1 RTIFR TOFR RTIE TOIE RTIF TOF

RTI RATE SELECT lower 8 bits of 15-bit ripple counter

upper 7 bits of 15-bit ripple counter TIMER COUNTER

REGISTER (TCR)

TIMER INTERRUPT ENABLE, REQUEST, AND CLEAR LOGIC

INTERRUPT REQUEST

˜4 INTERNAL

MCU CLOCK

 Bicycling Computer Application Bicycling Computer Application

Ç Bicycling Computer

Õ MC68HC705P6A Overview Õ Block Diagram

Õ Analog-to-Digital Converter

Õ 16-bit Capture/Compare Timer

Õ Serial Input/Output Port

 MC68HC705P6A Features MC68HC705P6A Features

Ç 28-Pin Plastic DIP, Ceramic DIP, and SOIC Packages

Ç 2.1 MHz Maximum Operating Frequency at 5 Volts

Ç 4672 Bytes of EPROM

Ç 176 Bytes of RAM

Ç 16-Bit Timer with Input Capture, Output Compare, and Counter Overflow

Ç Computer Operating Properly (COP) Watchdog Timer

Ç Full Duplex, Bidirectional Serial Input/Output Port (SIOP) with 4 Baud Rates

Ç 4-Channel, 8-Bit Analog-to-Digital Converter

Ç 21 Discrete Input/Output Pins

Õ 20 Bidirectional Pins (Port A[7:0], Port C[7:0], Port D5) Õ 1 Input Only Pin (Port D7)

Õ Software Programmable Pullup Devices on Port A[7:0]

Õ Optional Active High Interrupt Capability on Port A[7:0]

Õ 10 mA Current Sink Capability on Port C[1:0]

 Cycling Computer Block Diagram Cycling Computer Block Diagram

EKG CONTACTS TEMPERATURE

SENSOR HUMIDITY

SENSOR

SERIAL LCD

WHEEL SPEED SENSOR

MC68HC705P6A

SERIAL INPUT/OUTPUT PORT A-TO-D CONVERTER

CAPTURE/COMPARE TIMER MENU

PUSHBUTTONS PORT A INPUTS

 Analog-to-Digital Converter (ADC) Analog-to-Digital Converter (ADC)

VRL is not bonded on the MC68HC705P6A, but instead, is tied directly to VSS.

AN0 AN1 AN2 AN3 VRH VRL (VRH+VRL)/2

A/D Result

Register (ADDATA)

A/D Status & Control Register (ADSTAT)

VRH

capacitor array and 8-bit VRL DAC with sample and hold

successive approximation register (SAR) and control

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

CC ADRC ADON 0 CH3 CH2 CH1 CH0

Channel Selection Analog Multiplexer

AN4 AN5 AN6 AN7

These inputs are not present on the MC68HC705P6A.

 EKG Signal Conditioning for the ADC EKG Signal Conditioning for the ADC

+ -

+ LEFT -

HANDLEBAR GRIP

R3 100 Ω

R5 8.2 kΩ

R6 680 Ω

C2 4.7 µF

- + C3 1 µF

R2 4.7 kΩ

C4 0.02 µF

- +

+ -

+ -

+5 vdc PC6/AN0

2.5 VDC OFFSET

INSTRUMENTATION AMPLIFIER

(gain = 2000)

CHEBYSHEV LOW PASS FILTER

(cut off frequency = 10 Hz, 90 dB attenuation per decade)

HIGH PASS FILTER

(cut off frequency = 7.2 Hz)

RIGHT HANDLEBAR GRIP

C1 4.7 µF

R1 4.7 kΩ

R48.2 kΩ

R7 680 Ω

+ -

R9 8.2 kΩ

R8 8.2 kΩ

R10 100 kΩ

R11 100 kΩ

R12 100 kΩ

C6 0.2 µF 0.47 µFC5

R13 100 kΩ R14

20 kΩ

R15 10 kΩ R16

20 kΩ

20 kΩR17

R18 R19

R20 20 kΩ

 16-Bit Timer Overflow 16-Bit Timer Overflow

INTERNAL ˜4 MCU CLOCK

TIMER CONTROL REGISTER (TCR) TIMER STATUS REGISTER (TSR)

TIMER OVERFLOW INTERRUPT REQUEST

ICIE OCIE TOIE 0 0 0 IEDG OLVL 0 0 0 0 0 ICF OCF TOF

TIMER REGISTER HIGH (TRH) ALTERNATE TIMER REGISTER HIGH (ATRH)

ALTERNATE TIMER REGISTER LOW (ATRL)

TIMER REGISTER LOW (TRL)

 16-Bit Timer Output Compare 16-Bit Timer Output Compare

OUTPUT COMPARE INTERRUPT REQUEST

OUTPUT COMPARE REGISTER HIGH (OCRH)

OUTPUT COMPARE REGISTER LOW (OCRL) 16-BIT COMPARATOR

PIN CONTROL TCMP

INTERNAL ˜4 MCU CLOCK

TIMER REGISTER HIGH (TRH) ALTERNATE TIMER REGISTER HIGH (ATRH)

ALTERNATE TIMER REGISTER LOW (ATRL)

TIMER REGISTER LOW (TRL)

TIMER CONTROL REGISTER (TCR) TIMER STATUS REGISTER (TSR)

ICIE OCIE TOIE 0 0 0 IEDG OLVL 0 0 0 0 0 ICF OCF TOF

 16-Bit Timer Input Capture 16-Bit Timer Input Capture

+5 vdc

SW1 magnetic

switch C1

0.1 µF

TIMER CONTROL REGISTER (TCR)

ICIE OCIE TOIE 0 0 0 IEDG OLVL

INPUT CAPTURE INTERRUPT REQUEST

EDGE DETECTOR

TCAP INPUT CAPTURE

REGISTER HIGH (ICRH)

INPUT CAPTURE REGISTER LOW (ICRL)

TIMER STATUS REGISTER (TSR)

ICF OCF TOF

0 0 0 0 0

TIMER REGISTER HIGH (TRH) ALTERNATE TIMER REGISTER HIGH (ATRH)

ALTERNATE TIMER REGISTER LOW (ATRL)

TIMER REGISTER LOW (TRL) INTERNAL

MCU CLOCK

˜4

R2 10 kΩ 10 kΩR1

MC68HC705P6A

WHEEL SPEED SENSOR

 Serial Input/Output Port (SIOP) Serial Input/Output Port (SIOP)

INTERNAL MCU CLOCK

SHIFT CLOCK GENERATOR

SERIAL INPUT/OUTPUT PORT DATA REGISTER (SDR) 8-BIT BI-DIRECTIONAL SHIFT REGISTER

SCK SDI SDO MSTR

SPIF DCOL LSBF

PIN CONTROL

LOGIC

SDI/PB6

SDO/PB5 SCK/PB7 SPR1

SPR0

 SIOP to LCD Interface SIOP to LCD Interface

PLANAR STANDISH 8-DIGIT LCD MODEL 4228 A2

A1 A0

DCLK

DIN

ENB OSC1

OSC2 VLCD +5 vdc

VSS

FRONTPLANES 1 to 32 BACKPLANES 1 to 4

SCK/PB7

PC2

SDO/PB5

R1 470 kΩ

VDD

R2 10 kΩ

MC145LC003

 Other 68HC05 Family Peripherals Other 68HC05 Family Peripherals

Ç Serial Peripheral Interface

Ç Serial Communications Interface

Ç Enhanced Serial Communications Interface

Ç Pulse Length Modulation Timer

Ç Liquid Crystal Display Driver

 Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI)

S

M

SPE MSTR

CLOCK INTERNAL

MCU CLOCK

SPI STATUS REGISTER (SPSR) DIVIDER

÷2 ÷4 ÷16 ÷32

SELECT

SPI DATA REGISTER (SPDR)

SPI INTERRUPT

REQUEST SPI CONTROL

SPIF WCOL MODF

8-BIT SHIFT REGISTER READ DATA BUFFER

MSB LSB

SPI CLOCK (MASTER)

CLOCK CONTROL

LOGIC

SPI CONTROL REGISTER (SPCR)

SPIE CPOL CPHA SPR1 SPR0

SPR1 SPR0 MSTR SPEPIN CONTROL LOGIC

S M M S

MISO/PD2

MOSI/PD3

SCK/PD4

SS/PD5

 Serial Communications Interface (SCI) Serial Communications Interface (SCI)

The serial communications interface (SCI) is the universal asynchronous

receiver/transmitter (UART) on 68HC05 devices. It has the following features:

Ç Full duplex operation Ç 32 baud rate selections

Ç 8- or 9-bit character lengths

Ç Separately enabled receiver and transmitter Ç Wake up on idle line or address mark

Ç Optional interrupt generation upon transmit data register empty, transmission complete, receive data register full, receiver over-run, and idle line conditions

Ç Detection of receiver framing, noise, and over-run errors

 An Enhanced SCI — The SCI+ An Enhanced SCI — The SCI+

In addition to the capabilities of the standard SCI, the enhanced serial communications interface (SCI+) supports…

Ç Separate transmitter and receiver baud rates

Ç Output of the transmitter clock on the dedicated SCLK pin Ç SCLK phase and polarity control

Ç Output-only, least significant bit first, synchronous transfers

The SCI+ essentially adds a simple, master mode, SPI-like, synchronous

transfer capability to the standard SCI’s UART features.

 Pulse Length Modulation Timer Pulse Length Modulation Timer

COMPARATOR

BUFFER LATCH PLMB

ZERO DETECTOR PLMB SLOW/FAST

SELECT BIT (SFB)

PLMB REGISTER

INTERNAL

MCU CLOCK ÷4 16-BIT TIMER COUNTER

ZERO DETECTOR

SLOW/FAST SELECT MUX

SLOW/FAST SELECT MUX PLMA SLOW/FAST

SELECT BIT (SFA)

PLMA LATCH

COMPARATOR BUFFER

PLMA REGISTER

 Liquid Crystal Display (LCD) Driver Liquid Crystal Display (LCD) Driver

CONTROL LOGIC

BACKPLANE DRIVERS

BP0 BP1 BP2 BP3 VDD FRONTPLANE

DRIVERS

FP0 FP1

FP38

••

• DISPLAY RAM

ADDRESS BUS

DATA BUS

VLCD1 VLCD2 VLCD3