This work was supported by the National Science Council, Taipei, Taiwan, R.O.C. Project no. NSC 94-2213-E-009-146
Load Current Adaptive Control of a Monolithic CMOS
DC/DC Converter for Dynamic Power Management
Wei-Chi Su and Ying-Yu Tzou, Member, IEEE
Power Electronics Systems & Chips Lab., Advance Power Electronics Center,
Department of Electrical and Control Engineering, National Chiao Tung University, Taiwan.
Abstract This paper presents the design of a monolithic
current-mode CMOS DC/DC converter with integrated power switches and an on-chip passive adaptive controller with the sensed average inductor current. The sensed switched current, combined with the integration of inductor voltage, and a voltage-controlled floating resistor, can be used for the adaptive control of a CMOS DC/DC converter. The nonlinear carrier control can adjust carrier according to input voltage to reduce the input disturbance. The proposed control scheme has been design and simulation verified based on the TSMC 0.35ȝm technology. The designed CMOS DC/DC switching regulator is based on a rated output current of 500mA with an adjustable output voltage from 1.0V to 1.8V. Simulation results shows the proposed adaptive control scheme can achieve a fast dynamic power on transient response as well as a robust voltage regulation against large loading current variation.
Index Terms CMOS DC/DC converters, synchronous buck
regulator, load current adaptive control, nonlinear carrier, fast dynamic response, dynamic power management.
I. INTRODUCTION
Applications of system-on-a-chip (SOC) can be broadly classified according to their high-performance (HP) or low-power (LP) characteristics. Advanced microprocessors and high-end graphic processors are examples of high performance applications, while portable wireless applications such as PDAs, digital cameras, and bluetooth devices are examples of low-power SOCs. In either application, the power supplying to the SOC systems needs to satisfy the dynamic power management, fast dynamic response, and low power consumption [1]-[3].
To accommodate the diverse power requirements of a portable device, we need to design dedicated dc-dc converters for target point-of-load (POL) applications. CMOS based synchronous buck regulators are widely employed in portable information appliances. Low power consumption with low standby power, high power density with integrated magnetic components, high efficiency with large input voltage range, fast power on response time, robust voltage regulation without external components, and voltage scaling capability, etc., are important design issues for integrated dc-dc converters [4]-[6]. In order to achieve robust control performance, current-mode control schemes are usually employed with the control loops. Among various realization schemes, the peak current mode (PCM)
control with negative slope compensation is probably the most frequently adopted scheme in realization of PWM control ICs [7]. The PCM control with negative slope compensation can eliminate subharmonic oscillations within the inner current loop when operating duties are high [8]. The sensing scheme for the monolithic CMOS DC/DC needs to be realized with high bandwidth as well as low power consumption. An on-chip current sensing scheme without using a series connected resistor is proposed in [9], however, this scheme need sophisticated design of circuit parameters to match the high temperature sensitivity of on-chip CMOS buffer circuits.
To simplify the design of control loops of a CMOS DC/DC converter, various voltage-mode control schemes, such as second-order slope compensation [10], observer-based sensorless current mode control [11], end-point prediction [12], adaptive parameter scheduling [13], and digital control [14], have been developed to provide robust performance as well as simple circuit realization. However, these control schemes still can not meet the requirement of low-cost design with robust performance. In this paper, a simple load-current adaptive gain control scheme with a feedforward nonlinear carrier control has been proposed to achieve simple and robust control of a monolithic DC/DC converter without current mode control.
A monolithic current-mode CMOS DC/DC converter with integrated power switches and a novel on-chip adaptive controller is presented in this paper. The proposed analog adaptive voltage loop control scheme is shown in Fig. 1. With the sensed switch current, combined with the
Fig. 1. Proposed analog adaptive voltage loop control scheme.
-integration of inductor voltage, and a voltage-controlled floating resistor, an analog adaptive control scheme is proposed for the regulation of a CMOS DC/DC converter. The inductor current is sensed by using an on-chip sensing circuit in measuring the current of the complementary switches, however, because this measured current is used for the tuning of the control gain for the voltage mode controller, it can be much slower compared with the current mode sensing circuit and furthermore, the requirement on its accuracy much less stringent. Therefore, simple current sensing scheme can be employed in design of the on-chip current sensing circuit.
The designed CMOS DC/DC converter has been verified by using a system-level simulation software tool PSIM and also by a device-level simulation tool HSPICE based on the TMSC 0.35ȝm technology. Simulation results shows the proposed adaptive control scheme can achieve a fast dynamic power on transient response as well as a robust voltage regulation against large load current variations.
II. ANALOGADAPTIVE CONTROLLER
A. Feedforward Nonlinear Carrier Control
In general, a fixed frequency tooth carrier is used in pulse-width generator to generate driving signal for power stage because of it is easy to design and realize. But if the input voltage of converter suffers from disturbance in circuit or noise, the output voltage of converter will blend the disturbance component and become changeable. If the voltage loop compensator of converter doesn’t design well, the input disturbance may cause the converter unstable.
The feedforward nonlinear carrier can reduce the influence of input disturbance on output voltage of converter. As shown in Fig. 2, it generates the carrier according to the input voltage. If the input voltage has any change, the amplitude of carrier will adjust itself to decrease the change of output voltage.
Fig. 3 is the simulation results of compared with fixed frequency tooth carrier and nonlinear carrier. A 1000Hz sine wave with 2V peak-to-peak voltage is added on input voltage as a disturbance. Without any voltage loop compensation, use fixed frequency tooth carrier can’t adjust
itself and hence occurs a variation which equals to 0.6V on output voltage, but the variation can be reduced to 0.25V if nonlinear carrier is used.
If the way descripted in Fig. 2(a) is used, the output of voltage loop compensator will be in low level and may cause the transistors in compensator to leave saturation region. Therefore, the way to generate nonlinear carrier is as Fig. 2(b) in this paper.
B. Adaptive Voltage Loop Compensator
In the design of a loop compensator for a high bandwidth switching regulator we need take careful considerations in determination of gain crossover frequency and compensation of the resonant peak inherent in the output LC filter. The resonant peak of a switching regulator becomes more spiky at light load and more flat as load becomes heavy. Conventional approach is employing current-mode control to ensure robust response under large lard load disturbances. However, this approach needs complicated control circuit and still requires proper phase compensation to ensure a guaranteed phase margin for large load variations. Voltage-mode control with matched load compensation emerges as a competitive solution for dedicated applications due to its simplicity and fast dynamic response. However, this approach still requires a careful design of the voltage loop compensator. Fig. 4 shows the block diagram of voltage-mode control loop of a switching regulator. In order to ease the applications of switching regulators for more versatile applications without the need of loop compensator design, we need to develop an adaptive controller to accommodate various loading conditions and to eliminate the compensation circuit to simplify the circuit implementation. This papers proposes a simple analog circuit oriented adaptive control scheme by tuning the control loop gain with a nonlinear function of the measured average inductor current.
A proportional-integral (PI) phase-lead compensator with adjustable gain is adopted in the realization of the voltage-mode controller. Fig. 5 shows the schematic of the
Vin Integrator Integrator reset reset (a) Vin reset (b)
Fig. 2. The ways to generate nonlinear carrier.
Input voltage
Output voltage Fixed frequency tooth carrier
Nonlinear carrier
Fig. 3. Simulation results of compared with fixed frequency tooth carrier and nonlinear carrier when input voltage is variable.
Buck converter
G(s)
Voltage loop
Compensator C(s) Pulse-width generatorP(s) T(s)
vref ve vc d vo
+
-^ ^ ^ ^ ^
voltage-loop error amplifier with its compensator circuit and its transfer function is
) )( ( ) )( ( ) ( 2 1 2 1 p s p s s z s z s K s C p (1) where 3 3 1 3 1 2 3 2 1 2 1 2 1 3 1 3 1 2 2 2 3 1 1 1 1 C R R R R K C R C R z C R z C C C C R p C R p p . By using a voltage-controlled floating resistor [15], the control gain is proportionally adjusted according to the loading condition. The proposed control scheme can achieve a robust fast dynamic response and provides a
simple realization of the CMOS DC/DC synchronous buck converter without any external compensation components.
The loading condition can be determined by the inductance current. The transfer function of voltage loop compensator can be rewritten as
) )( ( ) )( ( ) ( 2 1 2 1 p s p s s z s z s i K s C L p D (2)
where D is a factor repersents the amount that inductance current influences the gain of compensator.
Fig. 6 shows the simulation results of adaptive control with a step change of reference voltage. The reference voltage switches from 1.5V to 2.5V at t = 10ms. In Fig. 6(a), the simulation condition is D less or equal to 1. The response waveform will approach the waveform without adaptive control. It causes the voltage control loop unstable
vref vc vo R1 R3 C2 R2 C1 C3 Zi Zf + + vx vy
Fig. 5. Schematic of the voltage loop compensator.
Output voltage D= 1 D= 0.5 D= 0.33 Without adaptive control
(a) D less or equal to 1.
Output voltage D= 2 D= 3 D= 1 Without adaptive control (b) D large or equal to 1.
Fig. 6. Simulation result of adaptive control with a step change of reference voltage. 1 0.9 0.8 0.7 0.8 0.6 1 0.4 Kp,r Kp Iload,r Iload
Fig. 7. The relationship between loading condition and adaptive control gain. Ibias Vdd M1 M2 M3 M4 M6 M8 M5 M7 in2_op in1_op Rz Cc C L out_op gnd
Fig. 8. Schematic of voltage error amplifier.
vin + -gm2vin ro2//ro4 C1 + -vx Cc gm6vx ro6 //ro7 CL Rz Nulling resistor
if is smaller. In Fig. 6(b), the simulation condition is D large or equal to 1. The rise time and settling time will be extend if D is large. In other words, when D becomes large, the gain of compensator decreases and hence the bandwidth of compensator becomes narrow.
The relationship between loading condition and adaptive control gain in this paper is shown in Fig. 7, where
Iload,r is the rated output current and Kp,r is the compensator
gain in full loading. According to loading condition, the adaptive control gain will adjust to corresponding value.
III. CIRCUITIMPLEMENTATION
In this section, the circuit implementation of the load-current adaptive gain control scheme with a feedforward nonlinear carrier control is addressed and the design is based on the structure shown in Fig. 1. Design details of each sub-circuit are presented as follows.
A. Voltage Loop Compensator
Fig. 8 shows the schematic of voltage error amplifier. Compared with other topologies of operational amplifier (OPA) such as telescopic or folded-cascode, two-stage OPA has advantages of high gain and large output swing. Fig. 9 shows its small signal model and its gain, poles and zero are ) 1 ( 1 , ) // ( ) // ( 6 1 1 1 6 2 2 1 7 6 6 4 2 2 z m c L L c c c m c v m o o m o o m v R g C z C C C C C C C g p C A g p r r g r r g A (3)
Note that the nulling resistor Rz should larger than 1/gm6 to generate a negative zero and p1 is the dominant pole.
In order to reduce the input offset voltage, Vds3 should equal to Vds4. This condition occurs when
7 5 6 4 6 3 ) ( ) ( 2 1 ) ( ) ( ) ( ) ( L WL W L WL W L WL W . (4) All MOS are designed to operate in saturation region. Decide the bias current is 2PA and the dominant pole locates 100Hz, the W/L ratio of each MOS can be calculated: 2 12 ) ( ) ( ) ( 2 6 ) ( ) ( ) ( ) ( ) ( 8 7 5 6 4 3 2 1 L W L W L W L W L W L W L W L W
The Bode plot of designed loop gain C(s)P(s)G(s) is
shown in Fig. 10. The designed compensator provides 50o
phase margin and the bandwidth of voltage loop is 80kHz.
B. On-Chip Current-Sensing Circuit
Fig. 11 shows the schematic of on-chip current-sensing circuit. During the converter ON-state, M1 and Ms1 turn on, the Vds of M1 and M2 are almost the same because the OPA
in this circuit is used as a voltage mirror. Therefore, ID1 : ID2 will equal to (W/L)1 : (W/L)2 and the inductance current is
sensed. The drain current of M2 through Rsense to generate a sensing voltage Vsense used to control the voltage controlled floating resistor in voltage loop compensator. During the converter OFF-state, M1 and Ms1 turn off and Ms2 turn on. The voltage at the negative input node of OPA is closed to
Vdd. The drain current of M1 is zero and M2 is the same.
Assume all MOS operate in saturation region, the calculated results of the W/L ratio of each MOS are listed below: 2 . 0 ) ( ) ( ) ( ) ( ) ( 26 ) ( , 5 . 3 ) ( ) ( 5 4 3 2 1 2 1 MCS MCS MCS MCS MCS Mrs MS MS L W L W L W L W L W L W L W L W C. Low-Pass Filter
Because the on-chip current sensing circuit mentioned before only senses the switch current during ON-state, a low-pass filter should be used to get the average inductance current. The cutoff frequency should much lower than switching frequency of converter, but improperly low cutoff frequency will cause the adaptive control gain adjust insensitively. In this paper, the cutoff frequency is decided at a tenth of switching frequency of converter.
D. Voltage-Controlled Floating Resistor
Fig. 12 shows the schematic of voltage controlled -200 -150 -100 -50 0 50 100 M a gni tude ( d B) 102 103 104 105 106 107 108 109 -270 -225 -180 -135 -90 -45 0 P h a s e (de g )
Bode plot of voltage loop
Frequency (Hz)
Fig. 10. Bode plot of loop gain
floating resistor. The gate of M4 and M6 are the two
terminals of the resistor. Because of Ix = Iy:
) )( 2 ( 2 , 1 2 y x a b n th y x b a n D D y x V V V V V V V V V K I I I I (5) where Kn = PnCox(W/L)1,2. The drain current of the matched
transistors M3 and M4 are equal:
dd g x b p th dd g p p th dd g p V V V V V V V K V V V K 3 , 3 , 3 ( ) 2 ) ( 2 (6) where Kp = PpCox(W/L)3,4. Similarly, from the matched
transistors M5 and M6, Va can be express as
dd g y a V V V V 3 . (7) Vg3 can be express as n th sense g V V V3 , . (8)
From (5), (6), (7) and (8), Ix and Iy can be rewritten as
. ) ( 2 1 ) )( ( 2 value resistor V V K I V V V V V V K Iy Ix sense dd n x y x y x sense dd n (9) Obviously, the resistor value is controlled by Vsense.
E. Comparator in PWM Modulator
The comparator, shown in Fig. 13, is implemented by a source-coupled differential pair with positive feedback. The
gate-to source voltages of M1 and M2 can be calculated
from their respective drain currents and are given by
2 2 , 2 1 1 , 1 ) ( ' , ) ( ' p M D n th GS M p D n th GS L W k i V v L W k i V v (10)
where kp’ = 0.5PpCox. The hysteresis VH can be calculated as
E E 1 1 ) ( ' 2 ) ) ( ' ) ( ' ( 2 ) ( 2 2 1 11 1 1 2 2 1 2 M p D M p D M p D GS GS trig H L W k i L W k i L W k i v v V V (11) where 6 4 5 3 ) ( ) ( ) ( ) ( L W L W L W L W E .
Note that the comparator has hysteresis characteristic only when E is larger than 1.
IV. SIMULATION RESULTS
The designed CMOS DC/DC converter is simulated by using a system-level simulation software tool PSIM and synthesized by a device-level simulation tool HSPICE based on the TMSC 0.35ȝm technology. The input voltage of converter and the supply voltage of control circuit are DC 5V, the operated frequency of converter is 500kHz. The component values are shown in Table I.
TABLEI
COMPONENT VALUES OF THE SIMULATION SETUP
L 10PH C 4.7PF Buck converter RL 3: Rint 16.6k: Nonlinear carrier generator C int 88.9pF Rz (in OPA) 16k: Cc (in OPA) 3pF R2 30k: R3 135: C1 1nF C2 886pF Compensator C3 1pF Rfil 1.59k: Low-pass filter Cfil 2nF
Fig. 14 shows the simulation results for a large step load change. Converter is operated in discontinuous mode when load current is 50mA. In closed loop simulation with adaptive control, the output voltage variation is 30mV and the settling time is 10Ps. It’s better than the closed loop simulation without adaptive control.
Fig. 12. Schematic of voltage controlled floating resistor.
Fig. 15 shows the simulation results for a step change of reference voltage from 1.5V to 1.525V. The load current
only has little change and hence the gain of compensator in adaptive control has little adjustment. Therefore, the transient response of closed loop simulation is similar to closed loop simulation with adaptive control.
Fig. 16 shows the frequency response of output impedance. The resonant frequency is 23kHz. The output impedance is reduced in magnitude after closed loop with adaptive control. After the crossover frequency of the voltage loop, the loop gain is small and hence the frequency response of output impedance is almost the same as open loop control.
Fig. 17, Fig. 18, and Fig. 19 are simulated by HSPICE. Fig. 17 shows the simulation results for a large step load change and Fig. 18 shows the simulation results for a step reference voltage change which are corresponding to the simulation results in Fig. 14 and Fig. 15. Fig. 19 shows the simulation results for a step change of input voltage from 5V to 6V. The variation of average output voltage in transient response is 1%. It means the input disturbance can be reduced by using a feedforward nonlinear carrier control.
Load current
Output voltage
Open loop Closed loop
Closed loop with adaptive control
(a) Switches to light loading.
Load current
Output voltage
Open loop
Closed loop
Closed loop with adaptive control
(b) Switches to heavy loading. Fig. 14. Simulation results for a step load change.
Open loop
Closed loop
Closed loop with adaptive control
Output voltage
Fig. 15. Simulation results for a step change of reference voltage.
101 102 103 104 105 106 -160 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz) M agni tude ( dB)
Bode plot of output impedance
Open-loop
Closed-loop with adaptive control
Fig. 16. Frequency response of output impedance.
Load current change
Output voltage
14Ps
18Ps 'Vo= 43mV
'Vo= 36mV
Fig. 17. Simulation results for a large load current change.
Output voltage
20Ps 14Ps
Fig. 18. Simulation results for a step change of reference voltage.
Input voltage
Output voltage
'Vo= 15mV 'Vo= 15mV
V. CONCLUSION
This paper has presented the design of a monolithic current-mode DC/DC converter by using feedforward nonlinear carrier PWM modulation scheme with passive adaptive control to accommodate large load current disturbances as well as input voltage variations. The nonlinear carrier generated by the integration of input voltage can reduce the input-to-output voltage disturbance effect compared with the conventional PWM technique. The passive adaptive controller provided a simple self-adjust of gain based on the averaged inductor current to stabilize the control loop to accommodate different loading conditions. Simulation results show the designed adaptive monolithic dc-dc switching regulator can maintain fast and well damped dynamic response for large changes of input voltage and load current. This research reveals feasibility of implementation of adaptive switching dc-dc regulators for wide applications without loop compensator design by using analog technology.
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