[10] M. Goossens, J. Ritskes, C. Verhoeven, and A. van Roermund, “Learning single electron tunneling neural nets,” in Proc. ProRISC Workshop Circuits, Syst. Signal Process., 1997, pp. 179–186.
Fast Transient Low-Dropout Voltage Regulator With Hybrid Dynamic Biasing Technique for SoC Application
Chia-Min Chen, Student Member, IEEE, Tung-Wei Tsai, and Chung-Chih Hung, Senior Member, IEEE
Abstract— This brief presents a low-dropout (LDO) voltage regulator without output capacitors that achieves fast transient responses by hybrid dynamic biasing. The hybrid dynamic biasing in the proposed transient improvement circuit is activated through capacitive coupling. The proposed circuit senses the LDO regulator output change so as to increase the bias current instantly. The proposed circuit was applied to an LDO regulator without output capacitors implemented in standard 0.35-µm CMOS technology. The device consumes only 25 µA of quiescent current with a dropout voltage of 180 mV. The proposed circuit reduces the output voltage spike of the LDO regulator to 80 mV when the output current is changed from 0 to 100 mA. The output voltage spike is reduced to 20 mV when the supply voltage varies between 1.3 and 2.3 V with a load current of 100 mA.
Index Terms— Capacitive coupling, hybrid dynamic biasing, low-dropout regulator, transient response, voltage spike.
I. INTRODUCTION
Nowadays, on-chip power management units have been exten-sively developed, implying there are multiple power domains in the system-on-chip (SoC) design. The power management system scales down the supply voltage by low-dropout (LDO) to power many circuit blocks. Transient response time is an important dynamic specification in LDO designs because the voltage spike affects the overall performance. For the LDO loop bandwidth, it is necessary to control the locations of the loop’s poles and zeros in small-signal analysis [1]–[3]. Increasing the loop bandwidth can improve small-signal performance at low and moderate frequencies. If the design focuses on the large-signal behavior, typical approaches are to increase the bias current to achieve a high slew rate, or to use large capacitors to reduce the undershoot and overshoot of the output Manuscript received November 22, 2011; revised July 6, 2012; accepted August 31, 2012. Date of publication October 9, 2012; date of current version August 2, 2013. This work was supported in part by the National Science Council and National Chip Implementation Center.
The authors are with the Institute of Communications Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: jeremy. cm97g@g2.nctu.edu.tw; twtsai.cm96g@g2.nctu.edu.tw; cchung@mail.nctu. edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2012.2217766
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Fig. 1. LDO structure without output capacitors.
voltage (VOUT) [4], [5]. In SoC applications [6]–[9], to reduce the undershoot or overshoot of the output voltage, the use of a large output capacitor will require an extra pin, which is therefore not preferred. To effectively increase the slew rate instantly seems to be a better approach to cope with output voltage spikes.
There are many ways to solve the voltage spike problem. One method is to use a constant bias current to increase the slew rate, where the bias current is not dependent on the output current. Besides, a previous design incorporates a 600-pF on-chip capacitor to reduce the output voltage ripple [10]. This method does not meet the power-saving and area-limited requirements of SoC designs.
The other method is the push–pull biasing method [11]. More bias current will be used at the transient instant only if the output current changes. The error amplifier uses a push–pull output stage to increase the current for charging and discharging the gate capaci-tance of the power transistor (CPAR_IN) during the transient instant. A differential-input common-gate amplifier activates the push–pull output stage. However, the fast-changing voltage spike cannot be detected effectively because the differential common-gate amplifier has limited bandwidth. This approach is also not suitable for low output voltages.
Another method is to raise the bias current based on the signifi-cance of the output current [12], [13]. For circuits to react to a change in the output voltage quickly, an adaptive bias current should maintain a minimum value in the steady state.
In this brief, an LDO with hybrid dynamic biasing is proposed to improve the output voltage transient speed under abrupt changes of the output current. Through capacitive coupling, the fast transient circuit senses transient changes in voltage at the LDO output and instantly increases the bias current. The quiescent current is only 25μA.
The rest of this brief is organized as follows. Section II presents the LDO architecture and operation principle of the proposed fast transient circuit through hybrid dynamic biasing. Section III shows experimental results. The final section addresses the conclusion of this brief.
II. LDO ARCHITECTURE A. LDO Architecture Without the Output Capacitor
Fig. 1 shows an LDO structure without the output capacitor [10]. Fig. 2 illustrates the large-signal responses of this structure. In Fig. 2(a), when the output voltage (VOUT) suddenly drops, it instantly decreases the VSG of transistor M1 and turns it off. To provide the same bias current (IBIAS), CPAR_INitself releases the current. In this
Fig. 2. Large-signal responses of the LDO structure without an output capacitor. (a) Undershoot. (b) Overshoot.
Fig. 3. LDO structure with the proposed fast transient circuit through hybrid dynamic biasing.
way, the current flowing through transistor MP increases when the VSGof transistor MP increases. This current pulls VOUTback to the original voltage. Fig. 2(b) shows that, when VOUTrises suddenly, it increases the drain voltage of transistor M1and the source voltage of transistor M2. Thus, a decrease in the VGSof transistor M2turns off transistor M2. As a result, all current flowing through transistor M4is charged to CPAR_IN. This phenomenon increases the gate voltage of transistor MP and decreases the VSGof transistor MP. This effectively reduces the current through the transistor MP. To maintain the same IBIAS, VOUTis pulled down to keep the same IBIAScurrent, thereby returning to the original voltage. The power transistor has a large size and generates a large parasitic gate capacitance. Owing to the large parasitic capacitance and the high impedance at this node, the gate of the power transistor forms a dominant pole. The other nodes are all of low impedance. Therefore, in the negative feedback loop, there only appears one pole within loop bandwidth, so the LDO does not require an output capacitor, which is therefore suitable for SoC applications. B. Structure and Operation Principles of the Proposed Fast Transient Circuit
Fig. 3 illustrates the proposed architecture. The most critical feature of the structure is the dynamic enhancement of the slew rate. When the output voltage changes dramatically, the bias current immediately changes to improve the slew rate and reduce the LDO undershoot and overshoot. Figs. 4 and 5 analyze the large-signal performance
Fig. 4. Operation of the proposed circuit (undershoot).
Fig. 5. Operation of the proposed circuit (overshoot).
of undershoot and overshoot, respectively. The voltage gain of the two op amps is Av = −gm1(ro1//ro3). The gain of the proposed circuit is larger than that of the circuit in [8], enabling it to amplify the detected transient signals more efficiently to enhance the transient driving capabilities and slew rates of transistors M4 and M3. Thus, the gate charge of power transistor MP can be promptly sourced or sunk, i.e., the power transistor can respond efficiently. Each op amp consumes only 3.5μA.
In addition to the capacitive coupling circuit, we also propose a dynamic bias circuit. The dynamic bias circuit can speed up the discharge of transistor M2 according to the transient output of the capacitive coupling circuit, thereby reducing the response time of the power transistor. In contrast, the circuit in [8] uses a fixed bias voltage, which limits the response time of the power transistor, resulting in a larger variation of the output voltage unless a larger bias current has been used. The inclusion of the dynamic bias circuit enables the power transistor to respond quickly to an abrupt increase in load, thereby reducing the variation of the output voltage and expediting the recovery of output voltage. The detailed operation of the dynamic bias circuit is given in Section II-D.
Fig. 4 shows that, when VOUT suddenly drops, the capacitive coupling of VOUT causes the gate voltage of transistors MB1 and MT 1 to drop. This, in turn, increases the output voltage of two differential amplifiers, decreasing the VSG of transistor M4 and
Fig. 7. Linking voltage generation circuit.
increasing the VGS of transistor M3. The current flowing through transistor M3becomes higher. As the VSGof transistor M4decreases, the current flowing through transistor M4 decreases. This instantly removes current from CPAR_IN, causing the gate voltage of transistor MP to drop quickly. When the VSG of transistor MP increases, it increases the current flowing through transistor MP. This, in turn, charges the output parasitic capacitance (CPAR_OUT) and pulls VOUT back to the original steady state. In Fig. 5, when VOUT suddenly rises, the capacitive coupling of VOUT causes the gate voltage of transistors MB1 and MT 1 to rise. This decreases the output voltage of two differential amplifiers, increasing the VSG of transistor M4 and decreasing the VGS of transistor M3. In this case, the current flowing through transistor M3 decreases, and the current flowing through transistor M4increases. Thus, some current flowing through transistor M4 charges CPAR_IN, which increases the gate voltage of transistor MP. In this way, the VSGof transistor MP decreases, which decreases the current flowing through transistor MP. Thus, CPAR_OUT discharges, making VOUT to pull down and return to the original steady voltage. In order to reduce the overshoot, increasing the gate voltage of the power transistor MPis more effective than discharging LDO output by transistor M1.
The bias generation circuit for VIP and VIN of Figs. 4 and 5 is shown in Fig. 6. The op amps in the proposed LDO regulator require additional bias voltages (VIP and VIN), while the circuit of [8] also requires two additional bias voltages.
C. Proposed Linking Voltage Generation Circuit (LVGC)
Fig. 7 shows that VREF locking V1 makes V1 = VREF by connecting op amp in the unity-gain feedback configuration. The op amp provides one stage of high gain and one stage of low gain. The closed-loop gain is Af ≈ gmL1(roL4//roL2) (2gmL5/gmL6) = 46 dB. The gain, which is larger than that of [8], is sufficient to force V1 to nearly equal VREF. The LVGC is designed to make the currents flowing through transistor ML6 and M1 to be the same. The size of transistor ML6 equals the size of transistor M1,
Fig. 8. Dynamic bias circuit.
ensuring that VSG(ML6) = VSG(M1). Therefore, the output voltage VOUT = V1 = VREF. Meanwhile, the bias current is designed as IML7 = IML6 = IM1 by selecting the size of transistor M3 to be twice that of ML7.
D. Proposed Dynamic Bias Circuit
The design principle of the dynamic bias circuit is to make VDYN change with VOP, as shown in Fig. 8. The primary purpose of the dynamic bias circuit is to momentarily change the bias current of the feedback loop of the main circuit when voltage spikes appear at the LDO output in order to quickly charge or discharge gate parasitic capacitance (CPAR_IN) of the power transistor. A sudden drop in VOUT increases VOP, which decreases the drain voltage of transistor MD4. A decrease in the drain and gate voltage of transistor MD3decreases the gate voltage of transistor MD2. Because the VSG of transistor MD2 is larger, the current flowing through it becomes larger as well, which causes VDYN to increase instantly. A drop in VOUT causes an increase in VDYN. A sudden drop at the gate of power transistor (MP) increases the VSG of the power transistor as well as the current flowing through it. This enables a more rapid pull-up of VOUT, returning it to a steady voltage. The addition of the dynamic bias circuit makes the whole circuit respond even faster with better performance.
E. Enhancement of Transient Responses
In Fig. 3, the high-pass network comprises resistor RT (RB) and capacitor CT (CB). The values of both CT and CB are 2 pF and the values of both RT and RBare 400 k. Thus, the corner frequency of the high-pass network is 199 kHz. When the load current of the LDO regulator is 100 mA, the crossover frequency of the main feedback loop is 500 kHz. The corner frequency of the high-pass network must be designed to be less than the crossover frequency of the LDO feedback loop. VOUTneeds to vary at least 5 mV within 5μs, so the fast transient circuit and the dynamic bias circuit can be efficiently triggered to respond to and reduce the output spikes.
Fig. 9 shows the measurement results of the load transient responses when VDD = 1.3 V, VOUT = 1.1 V, and IOUT = 1−100 mA. There are three parts in Fig. 9. The top one is the load transient response of the LDO with the proposed circuit, and the middle one is that of the LDO without the proposed circuit. The bottom one shows that IOUT changes between 1 and 100 mA. Both the rise and fall time of the load current range from 1 to 100 mA is 200 ns. The proposed dynamic hybrid biasing improves the undershoot of the output voltage from 480 to 117 mV, while the recovery time is improved from 6 to 1.4 μs. The overshoot is improved from 173 to 28 mV. The proposed approach effectively extends the bandwidth of the feedback loop, and ensures high-speed transient response to signal change.
Fig. 9. Comparison of two LDO structures with and without the proposed fast transient circuit, at VDD = 1.3 V, VOUT = 1.1 V, IOUT(MAX) = 100 mA, IOUT(MIN)= 1 mA.
Fig. 10. Die photograph of the proposed LDO voltage regulator.
III. EXPERIMENTALRESULTS
The proposed LDO regulator was fabricated using the 0.35-μm mixed-signal CMOS 2P4M process. The design of our regulator uses only 3.3 V MOS transistors; therefore, the maximum operation voltage is 3.3 V. Fig. 10 shows the die photograph of the prototype voltage regulator. Fig. 11 shows the input–output voltage characteristics of LDO regulator at IOUT = 100 mA, the dropout region, and line regulation performance. The size of the power transistor is 26 000 μm/0.35 μm to provide high output current. The dropout voltage is 180 mV. Fig. 12 shows the measured line transient response. The supply voltage switches between 1.3 and 2.3 V with 100 mA output current, and voltage spike is 20 mV. Fig. 13 shows the measured load transient response without an off-chip output capacitor. The output current varies from 0 to
Fig. 11. Input–output characteristics of the regulated voltage.
Fig. 12. Line transient measurement result of the proposed LDO voltage regulator without an off-chip output capacitor.
Fig. 13. Load transient measurement result of the proposed LDO voltage regulator without an off-chip output capacitor.
100 mA at 1.3 V supply voltage, while the rise time and fall time of the load current are 5 ns/mA. These measurement results show that the load transient voltage spike is only 80 mV.
The quiescent current of 25μA was measured with a load current IOUT = 100 mA. All bias current flows into the ground; therefore, we simply measure the current flowing into the ground pin to obtain the quiescent current. The current efficiency was obtained from (1). Fig. 14 shows the current efficiency as a function of load current
ηI=
IOUT IGND+ IOUT =
100 mA
25μA + 100 mA = 99.97%. (1) Performance comparison between some previously reported LDOs and the proposed LDO is summarized in Table I. The figure of merit
TR(measure)(μ s) 2.5 15.4 3 0.00054 0.75
FOM2 (ns) 1.125 1.54 1.29 0.032 0.187
Active area 0.263 mm2 0.264 mm2 0.155 mm2 0.098 mm2 0.126 mm2
Fig. 14. Current efficiency as a function of load current.
(FOM), given in (2) [10], is adopted in Table I FOM1= TR Iq IOUT,MAX = COUT· VOUT IOUT,MAX Iq IOUT,MAX. (2) To show an FOM directly obtained from the measurement data, a measured response time (TR(measure)) from load transient responses is taken into account. Another FOM is defined as
F O M2= TR(measure) Iq IOUT,MAX.
(3) Although our FOM2is larger than that of [10], the latter actually has an on-chip output capacitance of 600 pF, which has effectively reduced the measured response time. Therefore, to compare the performance with [10], FOM1seems to be a fair index. In addition, our measurement condition for the load transient response ranges from 0 to 100 mA, while the measurement condition in [8] ranges from 1 to 100 mA. The output impedance changes abruptly for load currents ranging from 0 to 100 mA; however, the output impedance does not change a great deal for load currents ranging from 1 to 100 mA. In other words, the measurement conditions for load transient response are far stricter in this case than in [8]. Therefore, the proposed LDO regulator is superior both in static and transient characteristics to the LDO regulator in [8]. By using 0.35-μm CMOS technology, the chip area of the proposed design is smaller than that in both [4] and [8].
IV. CONCLUSION
This brief presented an LDO voltage regulator without the output capacitor that achieves fast transient responses by hybrid dynamic
biasing. The dynamic biasing in the proposed fast transient circuit is activated through capacitive coupling. The fast transient through hybrid dynamic biasing circuit senses the LDO output change so as to increase the bias current instantly. The output voltage spike of the LDO with the proposed circuit decreases to 80 mV when the output current changes from 0 to 100 mA and 20 mV when a supply voltage of 1 V input step is applied to the circuit.
The proposed LDO regulator is stable for output current in the complete range of 0–100 mA and does not require any off-chip output capacitor. The proposed circuit improves both the overshoot and the undershoot of the LDO regulator. The FOM of this LDO compares favorably with that of other published designs.
REFERENCES
[1] G. A. Rincon-Mora, “Active capacitor multiplier in Miller-compensated circuits,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 26–32, Jan. 2000.
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[3] Y.-H. Lin, K.-L. Zheng, and K.-H. Chen, “Smooth pole tracking tech-nique by power MOSFET array in low-dropout regulators,” IEEE Trans. Power Electron., vol. 23, no. 5, pp. 2421–2427, Sep. 2008.
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[5] C. K. Chava and J. Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 6, pp. 1041–1050, Jun. 2004.
[6] Y.-H. Lee and K.-H. Chen, “A 65 nm sub-1 V multi-stage low-dropout (LDO) regulator design for SoC systems,” in Proc. IEEE Int. Midwest Symp. Circuits Syst. Conf., Aug. 2010, pp. 584–587.
[7] R. J. Milliken, J. Silva-Martinez, and E. Sanchez-Sinencio, “Full on-chip CMOS low-dropout voltage regulator,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 9, pp. 1879–1890, Sep. 2007.
[8] P. Y. Or and K. N. Leung, “An output-capacitorless low-dropout regulator with direct voltage-spike detection,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 458–466, Feb. 2010.
[9] C.-M. Chen and C.-C. Hung, “A capacitor-free CMOS low-dropout voltage regulator,” in Proc. IEEE Int. Symp. Circuits Syst. Conf., May 2009, pp. 2525–2528.
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output amplifier for low-quiescent current low-dropout regulators with transient-response improvement,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 9, pp. 755–759, Sep. 2007.
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Digital Error Corrector for Phase Lead-Compensated Buck Converter in DVS Applications
Shaowei Zhen, Xiaohui Zhu, Ping Luo, Yajuan He, and Bo Zhang
Abstract— Modern low-power system on a chip needs direct current converter with dynamic voltage scaling (DVS) ability for core power supply. The converter output should be accurate voltage across the full load current and voltage scaling range. An integrated buck converter for DVS application is proposed in this brief. Voltage mode phase lead compensation is implemented in the converter, with much smaller passive components than conventional type-III compensation. To improve accuracy, the output voltage error accompanied with load current and reference voltage caused by finite loop gain in analog control loop is corrected by the digital error corrector. The output voltage is compared by two comparators whose threshold voltage is about 10 mV above and below the reference voltage, respectively. The duty cycle is slightly adjusted by finite state machine according to outputs of the two comparators. Experimental results show that the converter is well regulated over an output range of 0.7–1.8 V, with step voltage of 25 mV. When load current suddenly changes between 170 and 500 mA, the overshoot and undershoot voltage are 32 and 50 mV, respectively. Load regulation is maintained about 1% throughout the full load range. The voltage error is within±10 mV in the voltage scaling range.
Index Terms— Buck converter, digital error corrector, phase lead compensation, voltage mode control.
I. INTRODUCTION
Low-power design techniques have become increasingly important for modern system on chips (SoCs). The dynamic voltage and frequency scaling (DVFS) technique controls the supply voltage and operation frequency of each module in SoC in response to workload demands, leading to substantial power saving while maintaining system performance. Direct current (dc–dc) converter with dynamic voltage scaling (DVS) ability acts as a hardware platform in a typical DVFS system. It is one of the hot topics in current research [1]–[4]. Compared to traditional dc-dc converters, the converter in the DVFS system should have several extra characteristics [1], [2]. Efforts have been made to achieve fast voltage scaling response, by Manuscript received January 24, 2012; revised August 7, 2012; accepted August 31, 2012. Date of publication October 9, 2012; date of current version August 2, 2013. This work was supported in part by the National S&T Special Project of China under Grant 2009ZX01031-003-003, the Fundamen-tal Research Funds for the Central Universities under Grant ZYGX2009J026, and the NLAIC Project under Grant 9140C0903091004.
S. Zhen and P. Luo are with the State Key Laboratory of Electronic Thin Films and Integrated Devices, Chengdu 610054, China (e-mail: swzhen@uestc.edu.cn; pingl@uestc.edu.cn).
X. Zhu was with the University of Electronic Science and Technology of China, Chengdu 610054, China. He is now with Texas Instruments Semiconductor Technologies Company, Ltd., Shanghai 200030, China (e-mail: 326465632@qq.com).
Y. He and B. Zhang are with the University of Electronic Science and Technology of China, Chengdu 610054, China (e-mail: yjhe@uestc.edu.cn; zhangbo@uestc.edu.cn).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2012.2217513
1063-8210/$31.00 © 2012 IEEE
maximum current charging or hysteretic control [2]–[4]. Moreover, voltage accuracy over full load current and voltage scaling range is an important specification, because smaller design margin is allowed, leading to further power saving while eliminating any slack periods caused by egregious low power supply. Accurate output needs high gain error amplifier (EA) and power devices with low resistance. The type-III compensator is often implemented in buck converter for high loop gain, but large off-chip capacitors and resistors limit its implementation in integrated power converters. Though recent advances in research are successful for monolithically integrate type-III compensator by pseudotype-III compensation [5] or extend-ing loop bandwidth [6], the passive components still occupy large area to generate low-frequency pole, or the loop bandwidth is limited [6]. In contrast, the phase lead compensator (PLC) stabilizes buck con-verter by only one high-frequency zero, so the area is tremendously reduced with comparable bandwidth with type-III compensation [7]. However, the primary drawback of the PLC is that the loop gain is severely curtailed. Thus, its application in DVFS systems is limited. This brief details the design of a novel error correction method presented in [8]. The digital error corrector (DEC) is implemented in a phase lead-compensated buck converter. Extra digitally controlled offset voltage is introduced to cancel output error because of low loop gain and parasitical resistors. This brief is organized as follows. In Section II, the error correction scheme is proposed and the detailed circuit implementation is introduced. Section III shows and discusses experimental performance, and Section IV summarizes this brief.
II. IMPLEMENTATION OFBUCKCONVERTERWITHDEC The simplified block diagram of the proposed buck converter with the proposed DEC is illustrated in Fig. 1. Output voltage VOUT is fed back to the PLC, and the operational transconductance amplifier (OTA) GM converts voltage error between VREF and VC into differential current in R1 and R2,respectively. The differential current is compared with sawtooth current ISAW by comparator Comp to generate pulse-width modulation (PWM) signal. ISAW and global clock signal CLK are provided by OSC. Power devices MP and MN are controlled and driven by RS latch and driver. There are two comparators designed accompanied with GM whose outputs are Comp_H and Comp_L, respectively. The threshold voltages to trigger Comp_H and Comp_L are defined as VOUT, MAX and VOUT, MIN, respectively. The proposed DEC introduces digitally controlled cur-rent source at node V1 to adjust duty cycle slightly according to Comp_H and Comp_L, until VOUT is between VOUT, MAX and VOUT, MIN. Then there is digitally controlled input offset voltage of EA introduced by DEC. The original output voltage error due to low loop gain is compensated by the offset voltage. Thus the regulation and output accuracy are enhanced.
A. Analog Control Loop
The schematic of control blocks in Fig. 1, such as PLC, GM comparators, and ISAWgeneration, is shown in Fig. 2. PLC is realized by operational amplifier OP, resistors RC 1, RC 2, and capacitor CC. GM is designed on the basis of symmetrical OTA. Voltage error between VC and VREFis converted into current error in R1and R2. ISAW generated by ISAW generation block flows out from node V2 and output current of DEC flows from node V1. The two comparators are current comparators, and IB1 and IB2 are designed to make VOUT, MAX about 10 mV higher than VREF and VOUT, MIN about 10 mV lower.
