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Room temperature two-terminal characteristics in silicon nanowires

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Room temperature two-terminal characteristics in

silicon nanowires

S.F. Hu

a,

*, W.Z. Wong

a

, S.S. Liu

a

, Y.C. Wu

a

, C.L. Sung

a

, T.Y. Huang

b

a

National Nano Device Laboratories, 1001-1 Ta Hsueh Road, Hsinchu 300, Taiwan, ROC

bInstitute of Electronics, National Chiao Tung University, 1001-1 Ta Hsueh Road, Hsinchu 300, Taiwan, ROC

Received 16 September 2002; accepted 16 October 2002 by C.N.R. Rao

Abstract

Quantum effects in silicon nanowires due to one-dimensional carrier confinement were observed at room temperature. Electrical transport properties were measured on narrow thin-silicon-on-insulator wires that were defined by e-beam lithography and further narrowed and thinned down by oxidation to a final thickness of around 3 nm, and a width of 29 nm. The room temperature current – voltage characteristics of the resulting silicon nanowires are shown to exhibit a zero current state may be due to the occurrence of Coulomb blockade.

q2003 Elsevier Science Ltd. All rights reserved.

PACS: 73.21.Hb

Keywords: A. Nanostructures; B. Nanofabrications; D. Tunnelling

1. Introduction

When the dimensions of a semiconductor sample are reduced to the nanometer regime, small-dimensional effects involving quantization come into play. These effects, which manifest themselves in the form of conductance oscillations

[1], appear at nanometer-scale dimensions at room tem-perature. To understand the size-quantization effects in semiconducting materials, semiconductor nanostructures have been studied extensively in the past two decades. Single electron and Coulomb blockade effects[1]have been revealed in mesoscopic low-dimensional structures. Yano et al. demonstrated Coulomb blockade effects in polycrys-talline silicon structures[2]. In their work, the film thickness was sufficiently thin and nonuniform so a natural potential difference occurs between the individual Si grains. Ng et al. reported the observation of Coulomb blockade effects at no

higher than 70 K in hydrogenated amorphous silicon recrystallized by electron beam annealing [3]. In their work, Coulomb blockade effect was modeled as a combination of hopping conduction between a limited number of trapping sites in amorphous regions or at grain boundaries with additional Coulomb blockade effects, as well as confinement due to potential fluctuations arising from dopant distribution. Concurrently, because silicon-on-insulator (SOI) structure is an efficient method for obtaining thin device thickness and can effectively remove the undesirable bulk effect of Si wafer, many works on devices based on SOI wafers made from separation by implanted oxygen (SIMOX) method have recently been reported

[4 – 7]. In this paper, we present our experimental work using electron-beam direct writing combined with oxidation to fabricate narrow thin wires on SIMOX wafer. The final width and thickness of the wires are 29 and 3 nm, respectively. Two-terminal characteristics were demon-strated at room temperature in the conducting silicon quantum wires.

0038-1098/03/$ - see front matter q 2003 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 0 9 8 ( 0 2 ) 0 0 8 0 7 - 4

Solid State Communications 125 (2003) 351–354

www.elsevier.com/locate/ssc

* Corresponding author. Tel.: þ 886-3-5726100x7717; fax: þ 886-3-5722715.

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2. Experimental

The silicon nano wires in this study were fabricated using SIMOX wafers fabricated on k100l p-type Si substrates, with a thin 60 nm silicon layer on top of a 400 nm buried SiO2. After depositing a 10 nm capping

oxide, the top silicon layer was doped by phosphorous ion implantation at a dose of 2 £ 1014ions/cm2and with energy of 40 kV. The doping level is sufficiently high so that the layer depicts metallic behavior, as is indicated by a significant drop in silicon sheet resistance to around 965 – 1118 V. The silicon layer was thinned down by a sacrificial oxidation and subsequent oxide strip. E-beam direct writing by a Leica Weprint 200 system with NEB22A electron-beam resist was then employed to define 80 nm-wide lines, with various lengths of 0.5, 1, and 3 mm, respectively. Next, the silicon layer was further thinned and narrowed down again, and a 20 nm gate oxide was then grown at 925 8C for 43 min in oxygen which further reduce the silicon wires’ thickness and width. Aluminum metal film was then deposited and patterned to provide electrical contact to the structure.Fig. 1(a)shows a schematic of the fabricated Si wires. The corresponding scanning electron microscope photograph is shown inFig. 1(b). W, L, and d denote the wire width, length, and thickness, respectively.

To characterize structural aspects of the Si wire, high-resolution transmission electron microscopy (HRTEM) was employed. The HRTEM examination was carried out with a JEOL-4000EX electron microscope operated at 400 kV. A HP4156C precision semiconductor parameter analyzer was used to measure the electrical properties both at 300 and 31 K. The low temperature measurements were performed

in liquid He cryogenic probing system (SCT-66 MDC, NAGASE). The current – voltage characteristics were measured with symmetric dc voltage bias Vds varied

between 2 2 and þ 2 V. Cross-sectional HRTEM image of a narrow silicon wire profile along AA0 (seeFig. 1) after oxidation at 925 8C for 43 min is shown inFig. 2. An abrupt interface between the oxide and the silicon is observed. The HRTEM image shows a dark, orderly region as well as gray regions in the sample. From the observation of the enlarged TEM image (bottom part ofFig. 2), the dark orderly ‘lattice-like’ region is mainly composed of nanocrystalline Si regions, which are separated by the gray regions. The gray counterparts are the SiO2amorphous phase. The separation

between crystalline planes in the images was measured and estimated to be , 5 A˚ , which is in excellent agreement with the Si lattice constant of 5.43 A˚ . The lateral crystallite dimensions d , 3 nm and W , 29 nm are confirmed by the cross-sectional view inFig. 2.

3. Results and discussion

I – V characteristics measured at T ¼ 31 K as a function of source – drain bias for narrow wires with various lengths are shown inFig. 3. All wires have active W , 29 nm and d , 3 nm. It can be seen that all wires, irrespective of their length, depict very low current in a considerable voltage range around zero bias. Moreover, the measurements of source – drain current at T ¼ 300 K, which are plotted in

Fig. 4, also exhibit zero current state around zero bias. This phenomenon observed at 300 K is similar to that at 31 K. Under higher bias conditions the current depict a

Fig. 1. (a) Schematic diagram of Si quantum wire and (b) the corresponding SEM photograph.

Fig. 2. Cross-sectional views of a HRTEM observation of silicon nano wire profile along AA0(as shown inFig. 1). Lateral crystallite dimensions with d , 3 nm and W , 29 nm are confirmed. S.F. Hu et al. / Solid State Communications 125 (2003) 351–354

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linear function of the applied voltage. A clear tendency is observed that, with the same thickness and width, a longer wire gives rise to a higher low current region. In other words, the size of the zero current state is significantly decreased while the overall conductivity increases for wires with smaller length. Specifically, from the distance between the first conductance peak, zero current state of 0.1, 0.3, and 1.5 V were found for wire length of 0.5, 1, and 3 mm, respectively.

The effects of a capacitively coupled gate on the transport properties of nano wires were also found. The gate electrode was formed by a probe tip, which was placed

in direct contact with the oxide on top of the 1 mm-long wire. The drain – source current – voltage characteristics at room temperature of a wire with active width , 29 nm and thickness , 3 nm were measured with different gate voltages VG¼ 0; 25, and 210 V, respectively. The results are shown in Fig. 5. Due to the relatively thick oxide , 500 nm used in this study, the gate coupling was weak. Nevertheless, it can be seen clearly that a more negative gate bias leads to a wider blockade region. It seems that the effect of the gate is a field effect, perturbing or narrowing the conductance channel. The increase in resistance with length, leading to significant current suppression at low bias, can be due to multiple tunneling between the nanocrystallites along the wire, where each may involve a charge effect. In addition, some peaks were observed in the differential conductance that separates the low current range from the tunneling region. When the drain bias is sufficiently high, the low current range of the current through the wire can be lifted due to the additional energy. Therefore, the electrons can occupy states at higher orbital in the confined quantum wire and opening of a large energy window for tunneling.

Fig. 6shows the corresponding tunneling spectra (dI/dV vs. V). The tunneling spectra appear to be asymmetrical with peaks in the positive and negative bias region. The conductance peaks in the positive bias region as shown in

Fig. 6is much higher and better resolved than the peaks in the negative bias region. It should be noted that the conductance, on the other hand, increases more rapidly at negative bias than at positive bias. Electron transport in Si nanocrystallites is complicated due to the coexistence of amorphous and crystalline phases, dopants, traps, etc. Assuming a complete suppression of the potential fluctu-ations, the observed low current regime could only be attributed to quantum confinement and unintentional inhomogeneous effects[8 – 12], as they only depend on the geometry and the exact location of the impurities and are not only affected by the applied gate voltage.

Fig. 3. Current – voltage characteristics measured at 31 K of silicon quantum wires with various lengths of 0.5, 1, and 3 mm. Insert shows the enlarged portion in the region around 0 V for 0.5 mm-long wire, illustrating the value of the offset voltage.

Fig. 4. Current – voltage characteristics measured at room tempera-ture (300 K) of silicon quantum wires with various lengths of 0.5, 1, and 3 mm. Insert shows the enlarged portion in the region around 0 V for 0.5 mm-long wire, illustrating the value of the offset voltage.

Fig. 5. Current – voltage characteristics measured at room tempera-ture (300 K) of silicon wire with various gate voltage of 0, 2 5, and 2 10 V. The wire length is 1 mm.

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4. Conclusions

We have fabricated extremely narrow thin silicon wires on SIMOX wafers. The highly doped Si layer was accomplished using phosphorous ion implantation and annealing. The lateral crystallite dimension, 3 nm £ 29 nm, is confirmed by cross-sectional view of HRTEM image. Two-terminal characteristics were observed in the structure not only at 31 K but also at the room temperature.

Acknowledgements

This work was performed under the contract numbers

NSC90-2721-2317-200 and NSC90-2215-E-317-002 sup-ported by the National Science Council, Republic of China. Technical supports from the members at National Nano Device Laboratories are acknowledged.

References

[1] H. Grabert, M. Devoret, Single Electron Tunneling, Plenum Press, New York, 1992.

[2] K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai, K. Seki, Tech. Dig. IEEE Int. Electron Devices Meet. (1993) 541. [3] V. Ng, H. Ahmed, T. Shimada, J. Appl. Phys. 86 (1999) 6931. [4] D. Ali, H. Ahmed, Appl. Phys. Lett. 64 (1994) 2119. [5] A. Nakajima, T. Futatsugi, K. Kosemura, T. Fukano, N.

Yokoyama, Appl. Phys. Lett. 70 (1997) 1742.

[6] T. Koester, F. Goldschmidtboeing, B. Hadam, J. Stein, S. Altmeyer, B. Spangenberg, H. Kurz, R. Neumann, K. Brunner, G. Abstreiter, Jpn. J. Appl. Phys. 38 (1999) 465.

[7] K. Kurihara, H. Namatsu, M. Nagase, T. Makino, Elsevier Microelectron. Engng 35 (1997) 261.

[8] D.K. Ferry, S.M. Goodnick, Transport in Nanostructures, Cambridge University Press, Cambridge, 1999.

[9] A. Tike, R.H. Blick, H. Lorenz, J.P. Kotthaus, D.A. Wharam, Appl. Phys. Lett. 75 (1999) 3704.

[10] C. Single, A.F. Zhou, H. Heidemeyer, F.E. Prins, D.P. Kern, E. Plies, J. Vac. Sci. Technol. B 16 (1998) 3938.

[11] F. Iacona, V. Raineri, F. La Via, A. Terrasi, E. Rimini, Phys. Rev. B 58 (1998) 10990F.

[12] A.T. Tiike, F.C. Simmel, R.H. Blick, H. Lorenz, J.P. Kotthaus, Prog. Quant. Electron. 25 (2001) 97.

Fig. 6. Conductance ðdID=dVDÞ oscillations plotted as a function of

VDSfor 1 mm-long wire measured at room temperature. VGis fixed

at 2 10 V.

S.F. Hu et al. / Solid State Communications 125 (2003) 351–354 354

數據

Fig. 1. (a) Schematic diagram of Si quantum wire and (b) the corresponding SEM photograph.
Fig. 6 shows the corresponding tunneling spectra (dI/dV vs. V). The tunneling spectra appear to be asymmetrical with peaks in the positive and negative bias region
Fig. 6. Conductance ðdI D =dV D Þ oscillations plotted as a function of

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