IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 7, JULY 2009 1629
A Phase-Locked Loop With Injection-Locked
Frequency Multiplier in 0.18-
m
CMOS for
V -Band Applications
Chung-Yu Wu, Fellow, IEEE, Min-Chiao Chen, and Yi-Kai Lo
Abstract—In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the -band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18- m CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are 85.2 and 90.9 dBc Hz, respectively. The reference spur level of 40.16 dBc is measured. The dc power dissi-pation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suit-able for low-power and high-performance -band applications.
Index Terms—Injection-locked frequency multiplier (ILFM), millimeter-wave circuits, phase-locked loop (PLL), RF CMOS.
I. INTRODUCTION
T
HE FREQUENCY synthesizer (FS) is a key building block of the RF integrated circuit (RFIC), which gener-ates the carrier signal to convert transmission data up to the desired frequency band. The transmission and reception qual-ities in the wireless communication system are determined by the performance of the local oscillator (LO) that is generated by the FS. In the conventional FS [1]–[3], the voltage-controlled oscillator (VCO) is always operated at the highest frequency to generate the LO signal. Owing to the limited performance of the active and passive devices, the performance of the VCO is mainly determined by the device technology. The implementa-tion of the high-frequency divider is another important design issue in the conventional FS structure. The injection-locked frequency divider (ILFD) [4] or Miller divider [5] are the popular options for the high-frequency divider design. Unfor-tunately, the division ratio of these dividers [4], [5] is not high. If the output frequency of these dividers is still higher than the frequency that a static divider can handle, a multistage of theseManuscript received June 12, 2008; revised March 09, 2009. First published May 19, 2009; current version published July 09, 2009. This work was supported by the National Science Council (NSC), Taiwan, under Grant NSC 96-2221-E-009-179.
C.-Y. Wu and Y.-K. Lo are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: cywu@alab.ee.nctu.edu.tw).
M.-C. Chen was with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan. He is now with the MStar Semiconductor Inc., Hsinchu 302, Taiwan.
Digital Object Identifier 10.1109/TMTT.2009.2021833
Fig. 1. Block diagram of the proposedV -band PLL.
dividers is required [6]. Since these high-frequency dividers are of narrowband characteristic, any frequency shift in each divider could cause the failure of the entire FS.
The other FS structure is composed of a low-frequency FS cascaded with a frequency multiplier to generate the desired output frequency [7], [8]. In this FS structure, the low-frequency FS is operated at the subharmonic of the desired frequency and the target frequency is generated by the frequency multiplier after the low-frequency FS. Obviously, it has the advantages of smaller division ratio and low power dissipation from the frequency divider. A frequency multiplier with a significant amount of power dissipation is, however, the main drawback [7]. Lately, a fully differential subharmonic injection-locked frequency multiplier (ILFM) has been proposed and demon-strated with low dc power consumption and large output power [9]. ILFM is, therefore, the feasible choice for the frequency multiplier in the design of the second FS structure.
In this paper, the design of a CMOS PLL cascaded with the ILFM for -band applications is proposed and designed to verify the above design concept. The proposed CMOS ILFM is designed to generate the fifth-order harmonic frequency of the VCO output. The proposed PLL with ILFM is designed and fabricated using 0.18- m bulk CMOS technology. The measured output frequency range is from 53.04 to 58.0 GHz, which is higher than the transition frequency ( GHz) of the device, but the highest frequency of the frequency divider in the proposed PLL structure is only 11.6 GHz. As a result, the total power dissipation can be reduced significantly as compared with pervious work [1]–[3].
In Section II, the proposed architecture of the -band phase-locked loop (PLL) and the building blocks of the proposed PLL including the VCO, ILFM, frequency divider, phase-frequency
Fig. 2. Circuit diagram of both VCO and ILFM.
detector (PFD), charge pump (CP), and loop filter are described. The experimental results are shown in Section III. Finally, a conclusion is presented in Section IV.
II. PLL BUILDINGBLOCKS
The proposed -band third-order type-II CMOS PLL that is composed of a VCO, an ILFM, a 1/32 frequency divider, a PFD, a CP, and la oop filter is shown in Fig. 1. The reference signal with the input power of 0 dBm and the frequency from 331.5 to 362.5 MHz is fed from the external signal generator. The output frequency ( ) with the frequency range from 53.04 to 58.0 GHz, which is five times the VCO output frequency ( ), is generated by the ILFM.
A. VCO and ILFM
The circuit diagram of both the VCO and ILFM is shown in Fig. 2. The VCO is made of a cross-coupled pair M1/M2 to generate negative resistance for the compensation of the loss from the LC tank. An on-chip spiral inductor L1 with sym-metric structure and accumulation mode MOS varactors C1/C2 are used in the VCO design. C1/C2 has the higher quality factor compared with pn-junction varactors. The poly-resistor R1 is designed for a proper bias condition of the cross-coupled pair. The utilization of resistor instead of PMOS current source is at-tributed to its free-of-flicker-noise property [10].
The schematic of the proposed ILFM can be divided into two stages [9]. The first stage is the frequency pre-generator stage and the second stage is the injection-locked oscillator (ILO) stage. The input signal from VCO is injected into the frequency pre-generator stage. The function of the frequency pre-generator stage that generates the fifth-order harmonic of the input injec-tion signal is implemented by M3/M4. The conversion gain of the frequency pre-generator can be maximized by selection of an appropriate gate bias value of M3/M4 . In addition, the locking range of the ILFM can be increased by an increase of the conversion gain of the frequency pre-generator [9].
The signal generated by the frequency pre-generator is di-rectly transmitted into the ILO stage formed by M5/M6 and a symmetric spiral inductor L2. The value of the inductor L2 is chosen so that it can resonate with the total capacitances at the
drain of M5/M6 at the fifth-order harmonic frequency of the input frequency. M5/M6 is used to generate negative conduc-tance to cancel the loss of the LC tank for higher output power of the ILO stage and to make the output signal differential. Without input signal, the output impedance of M3/M4 degrades the loop gain of the cross-couple pair M5/M6. However, when a large input signal is applied to the gates of M5/M6, M5/M6 are op-erated at the cutoff or linear region most times within a pe-riod of the input signal. Therefore, the effect of M3/M4 output impedance is not serious to degrade the performance of the ILO stage. Even with the loop gain degradation from M3/M4, the free-running output of ILFM can be designed in [9].
If the ILFM is designed with the loop gain larger than unity, free-running output signal of the ILFM occurs while there is no input injection. Hence, this type of ILFM is called an ILFM with free-running output. On the other hand, if the ILFM is de-signed with the loop gain less than unity, the ILFM does not pro-duce any output signal, while there is no input injection because the oscillation condition of free-running output is not satisfied. Thus, this type of ILFM is called an ILFM without free-running output. In the latter case, the ILFM is similar to a conventional frequency multiplier, but with a positive-feedback load to in-crease the output amplitude.
The resistor R2 is designed for the improvement of the monic rejection ratio (HRR) at every undesired even-order har-monic [9]. Since the output frequency is higher than the transi-tion frequency of the device, the open-drain output buffer is not suitable in this design owing to the poor property of the de-vice. A source follower is chosen as the output buffer for testing purposes. The simulated voltage loss from the output buffer is, however, still higher than 10 dB. Finally, the length of the inter-connection metal line from the ILFM output to the testing pad is around 70 m. To avoid the frequency shift, the characteristic of this metal line is simulated by the 3-D electromagnetic (EM) computer-aided design (CAD) tool High Frequency Structure Simulator (HFSS).
Based upon the model developed in [9], the extension model for the proposed ILFM is shown in Fig. 3(a). The frequency pre-generator is modeled as the nonlinear characteristic func-tion , the active devices of the ILO stage are modeled as
WU et al.: PLL WITH ILFM IN 0.18- m CMOS FOR -BAND APPLICATIONS 1631
Fig. 3. ILFM model. (a) Simplified signal flow model. (b) Simplified noise source model.
the linear constant transconductance stage , is the transfer function of the bandpass LC-tank filter in the output of the ILO stage, is the incident signal with the input frequency , is the output signal with the frequency , is the output signal of the frequency pre-generator, and is the output current of the transcon-ductance stage .
Firstly, the model for ILFM with free-running output is devel-oped. By use of the same process shown in [9] and extension of the nonlinear characteristic function into the fifth-order polynomial, the normalized locking range of the ILFM with free-running output can be expressed as
(1) where and are the resonant frequency and quality factor of the LC tank in the output of the ILFM, respectively, the coef-ficient is the nonlinear characteristic property of fifth-order term from frequency pre-generator, and and are the inci-dent and output amplitude, respectively.
The simplified noise model of the proposed ILFM is shown in Fig. 3(b) [9] where the conversion gain of the fifth-order har-monic signal in the frequency pre-generator is simplified to be a constant value and is the signal with frequency . The noise contribution from the frequency pre-generator and the ILO are modeled as and , respectively. The linear phase-domain model [11], [12] is adopted to calcu-late the output phase noise. The derived output phase noise can be expressed as
(2)
where the corner frequency of the ILFM noise transfer function can be written as
(3) (4) In the above equations, is the offset frequency from output
frequency and , , , and
are the noise spectral densities of output, input injection signal, frequency pre-generator, and ILO circuit, respectively.
The ILFM with free-running output has been discussed in [9]. The quality factor of the LC tank in this type of ILFM is max-imized for low power consumption and large output power. It can be seen from (1) that the output frequency range of this type ILFM is decreased due to the selection of large quality factor of the LC tank. The output frequency range of the ILFM is only 2% [9]. The output frequency of the ILFM can be in-creased by the degradation of the LC tank quality factor. Extra power consumption is required to keep the oscillation condition. However, due to the limited performance of active devices in 0.18- m CMOS technology, it is difficult to maintain ILFM os-cillation with small quality factor of the LC tank. In addition, the value of in (1) is strongly dependent on the fifth-order har-monic conversion characteristic of the active device. However, the high-order harmonic conversion efficiency of the active de-vice is not good. In other words, the value of in (1) is very small. Therefore, the locking range of the ILFM operated with free-running output is small. When the ILFM is integrated with a low-frequency VCO, the output frequency range is limited by the locking range of the ILFM due to the limited performance of active devices and high-order harmonic conversion efficiency.
Secondly, the ILFM without free-running output is discussed. In this case, the constraint of satisfying the free-running oscilla-tion condioscilla-tion is removed; the output signal is always locked when it is produced. When an ILFM designed without free-running output is integrated with a low-frequency VCO, the output frequency range is determined by the tuning range of the low-frequency VCO multiplied by the harmonic ratio, not by the locking range in (1) of the ILFM designed with free-run-ning output. Thus, the output frequency range is not affected by and can be increased by increasing the tuning range of the low-frequency VCO. The ILFM without free-running output is a better choice for wide output frequency applications. In this design, because the performance of active devices in 0.18- m CMOS technology is limited and wide output frequency is de-sired, the ILFM without free-running output is designed. For the ILFM without free-running output, the phase-noise perfor-mance is the same as in (3) [13].
Fig. 4 shows the HSPICE simulated normalized fifth-order harmonic currents of the frequency pre-generator where is the magnitude of the output drain current at the fifth-order harmonic frequency, is the magnitude of the output total drain current, and conduction angle is the device turn-on angle within one period of the input signal. The simulation condition involves a 12-GHz input signal with 4-dBm input power and a MOSFET device with dimensions of m m. Due to the parasitic capacitances of
Fig. 4. HSPICE simulated coefficient of output harmonic current as a function of conduction angle.
Fig. 5. Simulated output phase of VCO and ILFM.
the MOSFET device from gate–drain and drain–source, those undesired ac currents through gate–drain and drain–source are included in the output drain current and . It can be seen from Fig. 4 that the normalized harmonic current curve is not the same as the ideal switch condition in [14].
In general, the fifth-order harmonic current is mainly deter-mined by the coefficient of . In the case of an ILFM without free running, the output power is proportional to the coefficient because the larger fifth-order harmonic is generated; the larger desired fifth-order harmonic signal is transmitted to the ILO stage for signal amplification. The devices M3/M4 per-formed as the frequency pre-generator functions are, therefore, biased at a conduction angle of 230 in the proposed ILFM for higher output power. Finally, the value of can be calculated by a given input power, the device threshold voltage, and a suitable conduction angle [14].
The simulated phase noises of VCO output and ILFM output are shown in Fig. 5. It can be seen from Fig. 5 that the phase-noise differences between VCO output and ILFM output at 10-kHz and 1-MHz offset are 14.0 and 14.04 dB, respectively. If the noise contribution from the frequency pre-generator is negligible, the output phase noise is 13.98 dB ( ) higher than that from the input signal with a small offset frequency (3). Therefore, the noise contributions from the frequency pre-generator to the output phase noise at
Fig. 6. Simulated ILFM output power at fundamental and fifth-order harmonic frequencies versus input frequency from 11.4 to 12.0 GHz.
10 kHz and 1 MHz are 0.02 and 0.06 dB, respectively. The simulated power consumption of VCO and ILFM are 6.72 and 6.08 mW, respectively.
Since the ILFM without free-running output is selected in this design, the output power is proportional to the impedance of the positive-feedback load. The simulated output signal with the frequency at the fifth-order harmonic of the input signal is a function of input frequency and is shown in Fig. 6. The max-imum output power is 21.68 dBm, as the input frequency is 11.8 GHz. Due to the bandpass load ofthe ILFM, the funda-mental signal is lower than 46 dBm at the ILFM output. The HRR to fundamental signal is larger than 10 dB in the desired frequency range.
B. Frequency Divider
The 1/32 frequency divider is composed of the four-stage cur-rent-mode logic (CML) divide-by-2 dividers and one-stage dig-ital static flip-flop-based divide-by-2 divider. The CML divider [15] is made of a master–slave D-type flip-flop (DFF) with the output terminal (Q) connected to the input terminal (D) in in-verted polarities. The CMOS CML divider has been demon-strated to have high-speed operation with low power dissipa-tion because the full swing for internal operadissipa-tion is not required [16]. The schematic diagram of the master and slave latch is shown in Fig. 7(a). In the latch circuit, the sense stage consists of transistors M1, M3, and M4, whereas the latch stage com-prises the transistors M2, M5, and M6. In order to increase the operational frequency, the output load is chosen as the poly-re-sistors R1/R2 for smaller parasitic capacitance instead of PMOS load [17]. Each CML divider stage is designed to drive the next stage directly at its operational frequency by changing the de-vice ratios of sense stage and latch stage.
Since a full swing input for PFD is required, the last stage of the 1/32 frequency divider is designed as the digital-type fre-quency divider. The divide-by-2 divider comprises two ring-connected D-latches. The circuit diagram of the digital static divider is shown in Fig. 7(b). The simulated total power con-sumption of 1/32 frequency divider is 16.72 mW.
WU et al.: PLL WITH ILFM IN 0.18- m CMOS FOR -BAND APPLICATIONS 1633
Fig. 7. Simplified schematic of frequency divider. (a) CML static divider. (b) Digital static divider.
Fig. 8. Simplified schematic of the PFD.
C. PFD, CP, and Loop Filter
The circuit diagram of PFD [18] is shown in Fig. 8. The true single-phase-clock (TSPC) dynamic DFF is used for 100-MHz
Fig. 9. Circuit diagram of the CP and loop filter.
Fig. 10. Chip microphotograph of the proposed PLL.
Fig. 11. Output spectrum of the proposedV -band PLL.
frequency operation in the PFD circuit implementation. A slow
NORgate is used to generate the reset signal ( ) for re-ducing the dead-zone problem. Additionally, in order to reduce the skew between the complementary output signals, (UP/UPB) and (DN/DNB), complementary pass-transistor gates are used to match the delay of an inverter in the output of PFD.
The circuit diagram of the CP [19] and loop filter is shown in Fig. 9. A simple current-switched CP is used. Switches M3 and M4 are turned on at every phase comparison and may create the ripple on the control voltage ( ). M1 and M2 are used to decrease the charge injection and clock feedthrough from M3
Fig. 12. Measured output phase noise.
Fig. 13. (a) Measurement setup for the reference spur testing. (b) Measured reference spur.
and M4 to the output node ( ) [20]. The small bandwidth of the loop filter is designed to reduce the effect of nonideal property of switches. Since there is no current-matched technique in the CP design, the reference spur is stronger than that with current-matched technique. The simulated charge and discharge current is 50 A in this CP design.
In the loop filter design, all the passive components are im-plemented by the on-chip elements. The vertical metal–insu-lator–metal capacitors (MIMCaps) are used to realize the
ca-pacitors pF and pF with a reasonable
chip area. The resistor k is made of a poly-resistor. Since CP is designed without a current-matched technique, the selective loop bandwidth is only 2 MHz to filter out the nonideal effect of the reference spur.
Fig. 14. Measured: (a) output spectrum and (b) phase noise of the first di-vide-by-2 frequency divider.
III. EXPERIMENTALRESULTS
The proposed -band PLL is designed and fabricated by using 0.18- m Al 1P6M standard CMOS technology with an ultra-thick metal of 2 m. The chip microphotograph of the proposed PLL is shown in Fig. 10 where the chip area including all the test pads and dummy metal is 0.96 mm 0.84 mm. An on-wafer measurement system incorporating a probe station, ground–signal–ground (GSG) coplanar probes, and high-speed cables is used to measure chip performance. Since the VCO output load including the ILFM and frequency divider is large, the output signal from the VCO is not directly connected to the testing pad. In order to check the function of the low-frequency PLL, the output signal from the first divide-by-2 divider is connected to the testing pad.
The power consumption of the fabricated -band PLL is 35.7 mW at a power supply of 1.8 V. The measured output spec-trum of the locked ILFM is shown in Fig. 11 where all the losses from the probe, cable, adaptors, and external harmonic mixer have been deembedded. It can be seen from Fig. 11 that the pro-posed PLL structure provides the output power of 37.85 dBm with the output frequency of 58.0 GHz, which is higher than the transition frequency . The measured total output frequency range of the fabricated PLL is from 53.04 to 58.0 GHz, which is limited by the tuning range of the VCO. The output power
WU et al.: PLL WITH ILFM IN 0.18- m CMOS FOR -BAND APPLICATIONS 1635
TABLE I
COMPARISONWITHRECENTLYPUBLISHEDV -BANDCMOS PLLS.
at 53.04 GHz is about 10 dB lower than that at 58.0 GHz. The output phase noises marked at 1 and 10 MHz are measured as shown in Fig. 12. The measured output phase noises at 1- and 10-MHz offset from the carrier are 85.2 and 90.9 dBc Hz, respectively.
Due to the large conversion loss from the external harmonic mixer and the small output power from the fabricated chip, the high-resolution setup for the spectrum analyzer is required in the reference spur measurement [6]. To reduce the time cost of the high-resolution setup, a -band low-noise amplifier (LNA) is added before the external harmonic mixer. The output power to the spectrum analyzer is, therefore, large enough to reduce the resolution requirement. The measurement setup for output reference spur testing is shown in Fig. 13(a). As can be seen from the measurement results in Fig. 13(b), the measured refer-ence spur level is 40.16 dBc. Since the cross-product between output frequency and reference spurs are generated in the non-linear frequency pre-generator stage, the frequency offset be-tween the carrier and the spur tone is, therefore, the same as the reference frequency.
The performance of the first divide-by-2 frequency divider is also measured. The measured output power of 16.55 dBm at 5.8-GHz output frequency is shown in Fig. 14(a). The measured phase noise of the first divide-by-2 frequency divider output from 100 Hz to 100 MHz is shown in Fig. 14(b). The measured output phase noises at 100-kHz, 1-MHz, and 10-MHz offset from the carrier are 102, 108, and 121 dBc Hz, respec-tively. The phase noise difference between the ILFM output and the first divide-by-2 frequency divider output at 1-MHz offset is 22.8 dB, which is 2.8 dB higher than the theoretical limit 20 dB ( ), as can be seen from Figs. 12 and 14(b).
In Table I, the recently published -band CMOS PLLs worked at the -band are compared with the proposed PLL. It can also be seen that the proposed PLL can operate with a lower dc power consumption and a similar phase noise. Moreover, the output fre-quency range is larger than those in previous works [1]–[3], [6] because the ILFM with a wide operational frequency range is se-lected. Since the CP is not a current-match structure and larger VCO gain in this work, the reference spur is not as good as in pervious work. Finally, this design is the first CMOS PLL inte-grated with the ILFM in the millimeter-wave band.
IV. CONCLUSION
The proposed PLL integrated with a novel CMOS ILFM for -band applications has been designed and fabricated using 0.18- m standard CMOS technology. The proposed ILFM cir-cuit has been introduced to multiply the frequency five times and successfully co-designed with a low-frequency PLL. As can be seen from the measurement results, the ILFM has great potential in the application of LO signal generators for high-frequency PLL design. In addition, the maximum operational frequency of the frequency divider in a PLL can be reduced to only one-fifth by use of the proposed ILFM. Since it is feasible to design a high-performance VCO at low frequency and to save the large power consumption from full-speed frequency dividers, the pro-posed PLL structure provides a solution to the low-power and high-performance PLL for -band applications.
ACKNOWLEDGMENT
The authors would like to thank the Chip Implementation Center (CIC), National Science Council, Taiwan, for the fab-rication of the testing chip. The authors would also would like to thank Ansoft Taiwan for the use of their CAD tool HFSS.
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Chung-Yu Wu (S’76–M’76–SM’96–F’98) was
born in 1950. He received the M.S. and Ph.D. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1976 and 1980, respectively.
Since 1980, he has been a Consultant to high-tech industry and research organizations and has built up strong research collaborations with high-tech indus-tries. From 1980 to 1983, he was an Associate Pro-fessor with National Chiao Tung University. From 1984 to 1986, he was a Visiting Associate Professor
with the Department of Electrical Engineering, Portland State University, Port-land, OR. Since 1987, he has been a Professor with National Chiao Tung Univer-sity. From 1991 to 1995, he was the Director of the Division of Engineering and Applied Science, National Science Council, Taiwan. From 1996 to 1998, he was the Centennial Honorary Chair Professor with National Chiao Tung University. He is currently the President and Chair Professor of National Chiao Tung Uni-versity. In Summer 2002, he conducted post-doctoral research with the Univer-sity of California at Berkeley. He has authored or coauthored over 250 technical papers in international journals and conferences. He holds 19 patents, including nine U.S. patents. His research interests are nanoelectronics, biomedical devices and system, neural vision sensors, RF circuits, and CAD and analysis.
Dr. Wu is a member of Eta Kappa Nu and Phi Tau Phi. He was a recipient of a 1998 IEEE Fellow Award and a 2000 Third Millennium Medal. He sas also the recipient of numerous research awards presented by the Ministry of Education, National Science Council (NSC), and professional foundations in Taiwan.
Min-Chiao Chen was born in Miaoli, Taiwan, in
1980. He received the B.S. degree from the Institute of Electronics, Hsinchu, Taiwan, in 2002, and the Ph.D. degree in communication engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2008.
In 2009, he joined the MStar Semiconductor Inc., Hsinchu, Taiwan, as a Design Engineer responsible for RFIC design. His current research interests are the design of CMOS TV tuners and global system for mobile communications (GSM) transceivers.
Yi-Kai Lo received the B.S. and M.S. degrees in
elec-tronics engineering from National Chiao Tung Uni-versity, Hsinchu, Taiwan, in 2004 and 2006 respec-tively.
From 2006 to 2007, he was a Research Assistant with the Nanoelectronics and Gigascale Systems Laboratory, National Chiao-Tung University. Since April 2007, he attended compulsory military service with the Ministry of National Defense, Taiwan, as a Corporal of political warfare. He is currently with the Biomimetic System Research Center, National Chiao-Tung University, where he designs bioelectronics circuits and systems. His research interests focus on RF and mixed-signal integrated circuit design for high-frequency communication systems and medical telemetry radio band applications.
