• 沒有找到結果。

Novel Methods to Incorporate Deuterium in the MOS Structures

N/A
N/A
Protected

Academic year: 2021

Share "Novel Methods to Incorporate Deuterium in the MOS Structures"

Copied!
3
0
0

加載中.... (立即查看全文)

全文

(1)

IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 11, NOVEMBER 2001 519

Novel Methods to Incorporate Deuterium

in the MOS Structures

M. H. Lee, C.-H. Lin, and C. W. Liu, Senior Member, IEEE

Abstract—The deuterium concentration as high as 2 1020 cm 3 can be incorporated in rapid thermal oxide layers by a process of deuterium prebake and deuterium post oxidation anneal. The deuterium distributed not only at Si/oxide interface but also in the bulk oxide. The deuterium incorporation shows the improvement on soft breakdown characteristics and the interface state density at SiO2/Si after stress. The addition of very high vacuum prebake process yields a deuterium concentration of 9 1020cm 3, but also leads to the formation of rough oxide.

Index Terms—Deuterium incorporation, interface states, MOS, very high vacuum prebake.

I. INTRODUCTION

T

HE ELECTRICAL degradation of metal–oxide–silicon

(MOS) devices due to electrical stress has been exten-sively studied since the early 1980s [1]. Some degradation is related to the hydrogen release from the Si/oxide interface by hot electrons [2] and the incorporation of deuterium at the Si/oxide interface can significantly improve the device reliability [3]. The strong coupling between Si–D bond bending mode (460 cm ) and transverse optical phonons in bulk Si (463 cm ) is responsible for this giant isotope effect [4]–[6]. Recently, we have demonstrated that the deuterium incorporation can improve the soft breakdown in the NMOS tunneling diodes [7] and the reliability of MOS tunneling light emitting diodes [8]. The conventional method to incorporate the deuterium is performed by post metallization anneal after gate electrode deposition. In this letter, we report three kinds of deuterium process performed before the gate electrode deposition, and compare the deuterium concentrations with each process. The improvement of electrical properties is also demonstrated.

II. GROWTH ANDFABRICATION

The 4-in p-type wafer was transferred to the process chamber through the load-lock chamber and the ultrathin gate oxide of the NMOS diode was grown by rapid thermal oxidation (RTO) at 800–1000 C. The gas flows were 500 sccm nitrogen and 500 sccm oxygen at reduced pressure. The wafer temperature was monitor by pyrometry with a close loop control. The gate oxide

Manuscript received June 26, 2001; revised August 6, 2001. This work was supported by the National Science Council of Taiwan, R.O.C., (89-2218-E-002-082, 89-2218-E-002-054) and TSMC (Taiwan Semiconductor Manufacturing Company). The review of this letter was arranged by Editor K. De Meyer.

The authors are with the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. (e-mail: chee@cc.ee.ntu.edu.tw).

Publisher Item Identifier S 0741-3106(01)09413-7.

Fig. 1. SIMS profiles of the rapid thermal oxide with deuterium prebake.

thickness was measured by ellipsometry. NMOS diodes had Al gate electrodes with circular areas defined by photolithography.

III. DEUTERIUMINCORPORATION

In order to incorporate deuterium in the ultrathin oxide, the first kind process is to prebake the wafers in-situ at 1000 C for two min in deuterium gas. Then the gate oxide is grown, followed by a 900 C nitrogen post oxidation anneal for 10 min. The secondary ion mass spectroscopy (SIMS) profiles of this deuterium prebake process shows a deuterium concentration of 2 10 cm in the oxide as shown in Fig. 1.

To further increase the deuterium incorporation, the second kind process is to add a deuterium post oxidation anneal for 10 min at 900 C before the nitrogen anneal in the previous process. This yields a deuterium concentration of 2 10 cm in Fig. 2. The deuterium concentration increases by one order of magnitude, as compared to the first kind process.

Since the Si wafers are cleaned by a HF dip before the transfer to the process chamber, the Si surface is hydrogen-terminated and the hydrogen passivation will prevent the deuterium incor-poration in the oxide [9]. Therefore, the third kind process per-forms a thermal bake of the hydrogen-passivated wafer in the very high vacuum environment before the deuterium prebake. During the very high vacuum prebake ( 3 10 torr, main-tained by a turbo pump), hydrogen can be removed from the Si surface. To estimate the hydrogen coverage after the very high vacuum prebake, the desorption rate was calculated by first order analysis [10] with the assumption of the initial coverage , i.e., every silicon atom on the surface is bonded with hydrogen.

0741–3106/01$10.00 © 2001 IEEE

(2)

520 IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 11, NOVEMBER 2001

Fig. 2. SIMS profiles of the rapid thermal oxide with deuterium prebake and the post oxidation deuterium annealing.

Fig. 3. SIMS profiles of the rapid thermal oxide with very high vacuum prebake, deuterium prebake, and the post oxidation deuterium annealing.

where the activation energy and preexponential factor of hydrogen are 2.17 eV and 2.2 10 s , respectively [10]. The hydrogen is almost completely removed by the very high vacuum prebake for two min at 1000 C, as indicated by the calculation. The deuterium incorporation in the oxide with very high vacuum prebake can reach as high as 9 10 cm from the SIMS data in Fig. 3. However, the very high vacuum prebake also yields rough oxide with roughness up to 1.5 nm [11]. Since the roughness can also enhance the oxide reliability [12], the sole isotope effect on the oxide reliability can not be resolved. Therefore, all the following electrical measurements are based on the oxide prepared by the second kind process.

The grown oxide thickness by the deuterium process is 10–20% smaller, as compared to the hydrogen process. The hydrogen desorption rate is approximately 1.6 times the deu-terium desorption rate [10], and this may be responsible for the low growth thickness of deuterium process. For all three processes, the deuterium atoms not only distribute at Si/oxide interface but also in the entire SiO layers (Figs. 1–3), very similar to the deuterium distribution of D O pyrogenic oxide [13]. The incorporation of deuterium both at interface and bulk oxide plays an important role to suppress the electron trap creation. Note that the D O pyrogenic oxidation [13] yields a much lower deuterium concentration of 1 10 cm , as compared to our process. Besides, to avoid the other

Fig. 4. Gate current versus stress time plot of H -treated and D -treated NMOS diodes with the area of 32 10 cm under constant voltage stress with03 V CVS for 10 000 and 1000 sec, respectively. The insets are the I–V characteristics of the devices before and after stress.

signal with mass-to-charge ratio of 2 such as H , the SIMS profile of a H -treated sample was also measured, and this

signal was 1 10 cm , which was negligible as

com-pared to the deuterium concentration. The H -treated samples were processed using the same procedure except replacing deuterium with hydrogen.

IV. ELECTRICALCHARACTERIZATION

In order to observe the isotope effect, we use the second kind process to fabricate H -treated and D -treated devices to avoid the roughness effect produced by the very high vacuum prebake [11]. Fig. 4 shows the gate current variation as a function of stress time for H -treated and D -treated NMOS diodes with the area of 3 10 cm under constant voltage stress (CVS). There is no apparent fluctuation in gate current during the stress of the D -treated devices ( nm), and the – curves of the devices after 1000 sec CVS at 3 V is almost identical to the fresh one, as shown in the right inset of Fig. 4. For H -treated devices ( nm), the fluctuation in gate current under CVS implies that the degradation of oxide occurs and the in-version tunneling current increases significantly after the 10 000 sec CVS at 3 V (the left inset of Fig. 4). Note that the injection fluence ( ) maintains the same (about 4 10 coul/cm ) for both the H -treated and D -treated devices, and the D -treated devices have higher current densities. The D -treated device still remains intact even after 5000 sec stress (not shown here). We also perform the high–low frequency capacitance–voltage (C-V)

measurement on MOS diodes with thick oxide ( nm)

with the area of 3 10 cm to extract the interface state den-sities ( ) of the fresh devices and the stressed devices (Fig. 5). Note that we have difficulties to obtain reliable – measure-ments on thin oxide ( 3 nm). The extracted increases by 7 in H -treated devices after 15 sec constant voltage stress at 6 V since the Si–H bonds were broken by the injected elec-trons. No apparent increase of for D -treated devices im-plies the isotope effect. Both devices with 4-nm oxide break down during the constant current stress at 1.5 A (the insets of Fig. 5). It is similar to the previous report that there is an isotope effect on , but no isotope effect on stress induced leakage current (SILC) for ultrathin oxide [14]. Note that the

(3)

LEE et al.: NOVEL METHODS TO INCORPORATE DEUTERIUM IN THE MOS STRUCTURES 521

Fig. 5. Interface states density versus energy level of H -devices (upper) and D -devices (lower) with the area of 32 10 cm before and after stress.D increases approximately 72 after stress in H devices. No apparent increase of

D in D -treated devices is observed. The insets are the gate voltage variation

during constant current stress01.5 A.

isotope effect on SILC has been observed on the deuterium py-rogenic oxide, but not on the deuterium annealed thermal oxide [15].

Note that we have investigated the HF-dip only sample without H treatment as a control sample. The value of is 2 10 eV cm for the control sample, and reduces to 4

10 eV cm with H prebake two min at 1000 C. The

can further decrease to be less than 1 10 eV cm with both H prebake and H postoxidation anneal (H POA for 10 min) at 900 C. However, the previous study reported that the degradation of the electrical properties was observed after the H POA at temperature of 400–800 C [16]. This may attribute to different POA temperature, N POA, and oxidation conditions.

V. CONCLUSIONS

The deuterium distribution is not only at interface but also in the bulk oxide by these novel methods. The deuterium concen-tration as high as 2 10 cm can be achieved by a process of deuterium prebake and deuterium post oxidation anneal. The isotope effects on constant voltage stress and are observed for the deuterium-treated MOS device.

REFERENCES

[1] J. Maserijian and N. Zamani, “Behavior of the Si/SiO interface ob-served by Fowler–Nordheim tunneling,” J. Appl. Phys., vol. 53, no. 1, pp. 559–567, 1982.

[2] D. J. DiMaria and E. Cartier, “Mechanism for stress-induced leakage current in thin silicon dioxide films,” J. Appl. Phys., vol. 78, no. 6, pp. 3883–3894, 1995.

[3] J. W. Lyding, K. Hess, and I. C. Kizilyalli, “Reduction of hot electron degradation in metal oxide semiconductor transistors by deuterium pro-cessing,” Appl. Phys. Lett., vol. 68, no. 18, pp. 2526–2528, 1996. [4] K. Hess, I. C. Kizilyalli, and J. W. Lyding, “Giant isotope effect in hot

electron degradation of metal oxide silicon device,” IEEE Trans.

Elec-tron Devices, vol. 45, pp. 406–416, Feb. 1998.

[5] J.-H. Wei, M.-S. Sun, and S.-C. Lee, “A possible mechanism for improved light-induced degradation in deuterium amorphous-silicon alloy,” Appl. Phys. Lett., vol. 71, no. 11, pp. 1498–1500, 1997. [6] C. G. Van de Walle and W. B. Jackson, “Comment on ‘Reduction of hot

electron degradation in metal oxide semiconductor transistors by deu-terium processing’,” Appl. Phys. Lett., vol. 69, no. 16, pp. 2441–2243, 1996.

[7] C.-H. Lin, M. H. Lee, and C. W. Liu, “Correlation between Si–H/D bond desorption and injected electron energy in metal–oxide–silicon tunneling diodes,” Appl. Phys. Lett., vol. 78, no. 5, pp. 637–639, 2001. [8] C. W. Liu, C.-H. Lin, M. H. Lee, S. T. Chang, Y. H. Liu, M.-J. Chen, and C.-F. Lin, “Enhanced reliability of electroluminescence from metal–oxide–silicon tunneling diodes by deuterium incorporation,”

Appl. Phys. Lett., vol. 78, no. 10, pp. 1397–1399, 2001.

[9] K. Arima, K. Endo, T. Kataoka, Y. Oshikane, H. Inoue, and Y. Mori, “Atomically resolved scanning tunneling microscopy of hydrogen-ter-minated Si(001) surface after HF cleaning,” Appl. Phys. Lett., vol. 76, no. 4, pp. 463–465, 2000.

[10] K. Sinniah, M. G. Sherman, L. B. Lewis, W. H. Weinberg, J. T. Yates, Jr., and K. C. Janda, “Hydrogen desorption from the monohydride phase on Si(100),” J. Chem. Phys., vol. 92, no. 9, pp. 5700–5711, 1990. [11] C. W. Liu, M. H. Lee, B.-C. Hsu, Y.-H. Liu, W. C. Chung, and W. W. Pai,

“Correlation between oxide roughness and light emission intensity of metal–oxide–silicon light-emitting diodes,” Appl. Phys. Lett., submitted for publication.

[12] C. W. Liu, C.-H. Lin, M. H. Lee, B. C. Hsu, K.-F. Chen, and C.-R. Shie, “Oxide roughness enhanced reliability of MOS tunneling diodes,” , sub-mitted for publication.

[13] Y. Mitani, H. Satake, H. Itoh, and A. Toriumi, “Highly reliable gate oxide under Fowler–Nordheim electron injection by deuterium pyrogenic ox-idation and deuterated Poly-Si deposition,” in IEDM Tech. Dig., 2000, pp. 343–346.

[14] D. Essenio, J. D. Bude, and L. Seimi, “Deuterium effect on interface state and SILC generation in CHE stress conditions: A comparative study,” in IEDM Tech. Dig., 2000, pp. 339–342.

[15] Y. Mitani, H. Satake, H. Ito, and A. Toriumi, “A study of the effect of deuterium on stress-induced leakage current,” Jpn. J. Appl. 2, vol. 39, no. 6B, pp. L564–L566, 2000.

[16] V. V. Afanas’ev and A. Stesmans, “Hydrogen-induced valence alter-nation state at SiO interfaces,” Phys. Rev. Lett., vol. 80, no. 23, pp. 5176–5179, 1998.

數據

Fig. 1. SIMS profiles of the rapid thermal oxide with deuterium prebake.
Fig. 2. SIMS profiles of the rapid thermal oxide with deuterium prebake and the post oxidation deuterium annealing.
Fig. 5. Interface states density versus energy level of H -devices (upper) and D -devices (lower) with the area of 3 2 10 cm before and after stress

參考文獻

相關文件

2.1.1 The pre-primary educator must have specialised knowledge about the characteristics of child development before they can be responsive to the needs of children, set

Reading Task 6: Genre Structure and Language Features. • Now let’s look at how language features (e.g. sentence patterns) are connected to the structure

 Promote project learning, mathematical modeling, and problem-based learning to strengthen the ability to integrate and apply knowledge and skills, and make. calculated

Robinson Crusoe is an Englishman from the 1) t_______ of York in the seventeenth century, the youngest son of a merchant of German origin. This trip is financially successful,

fostering independent application of reading strategies Strategy 7: Provide opportunities for students to track, reflect on, and share their learning progress (destination). •

Now, nearly all of the current flows through wire S since it has a much lower resistance than the light bulb. The light bulb does not glow because the current flowing through it

During early childhood, developing proficiency in the mother-tongue is of primary importance. Cantonese is most Hong Kong children’s mother-tongue and should also be the medium

The spontaneous breaking of chiral symmetry does not allow the chiral magnetic current to