and High-Frequency Performance in
Nanoscale nMOSFETs
Kuo-Liang Yeh, Member, IEEE, and Jyh-Chyurn Guo, Senior Member, IEEE
Abstract—The impact of channel width scaling on
low-frequency noise (LFN) and high-low-frequency performance in multi-finger MOSFETs is reported in this paper. The compressive stress from shallow trench isolation (STI) cannot explain the lower LFN in extremely narrow devices. STI top corner rounding (TCR)-inducedΔW is identified as an important factor that is responsible for the increase in transconductance Gm and the reduction in LFN with width scaling to nanoscale regime. A semi-empirical model was derived to simulate the effective mo-bility (µeff) degradation from STI stress and the increase in
effective width(Weff) from ΔW due to STI TCR. The proposed
model can accurately predict width scaling effect onGm based on a tradeoff betweenµeff andWeff. The enhanced STI stress
may lead to an increase in interface traps density (Nit), but
the influence is relatively minor and can be compensated by the
Weff effect. Unfortunately, the extremely narrow devices suffer
fT degradation due to an increase in Cgg. The investigation of
impact from width scaling onµeff,Gm, and LFN, as well as the
tradeoff between LFN and high-frequency performance, provides an important layout guideline for analog and RF circuit design.
Index Terms—Effective mobility, effective width, low-frequency
noise (LFN), shallow trench isolation (STI) stress.
I. INTRODUCTION
W
ITH the aggressive scaling of CMOS technology into the nanoscale regime, the stress introduced from shal-low trench isolation (STI) process becomes significant and im-poses a dramatic impact on not only CMOS device performance in dc current and ac gate speed [1]–[6] but also high frequency and analog performance. Among previous work on this subject, most of research effort and publications have been focused on the longitudinal stress (σ//) from STI along the direction of thechannel length [1]–[3]. However, relatively fewer studies were done for looking into the influence from STI transverse stress (σ⊥) along the gate width and transverse to the channel length [4]–[6]. In addition, most of the studies on σ⊥ are limited to dc characteristics, such as threshold voltage (VT) and channel
Manuscript received May 10, 2010; accepted August 9, 2010. Date of publication October 4, 2010; date of current version November 5, 2010. This work was supported in part by the National Science Council under Grant NSC 98-2221-E009-166-MY3. The review of this paper was arranged by Editor Z. Celik-Butler.
The authors are with the Institute of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: jcguo@mail.nctu.edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2072959
current (IDS), and restricted to long-channel devices, assuming
negligible σ// in the channel region [4]. STI edge effect on
flicker noise was investigated, and negative impact was reported for NMOS with narrow widths [7], [8]. A minor layout modifi-cation, i.e., an edge-extended design, was implemented, trying to reduce the stress and traps introduced by STI and fix the problem of non-1/f characteristics in the measured flicker noise [9]. However, the abnormal deviation from 1/f characteristics as reported for narrow devices cannot be reproduced from our experiment, even with a much more aggressively scaled width. A ring-type device was proposed, trying to eliminate σ⊥
and identify the influence on flicker noise [10]. However, the study is limited to single-polygate MOSFETs, which are not suitable for analog and RF circuit design, and the impact on high-frequency performance is unknown [10]. Recent studies reported a turn around of IDSwith decreasing width of the
ac-tive area and proposed an increase in effecac-tive width, i.e., ΔW , from STI top corner rounding (TCR) as the potential factor trad-ing with mobility degradation from STI compressive stress [4], [5]. Again, most of the works were restricted to single-polygate MOSFETs for logic circuits, but the influence on multiple-polygate-finger (i.e., multifinger) MOSFETs required for RF and analog circuits, with special concern of high-frequency performance and flicker noise, remains an open question.
The aforementioned multifinger MOSFETs have been widely used to reduce the parasitic gate resistance (Rg) in RF
circuits for the purpose of improving analog and RF perfor-mance like higher maximum oscillation frequency (fMAX) and
lower RF noise [11]. Note that the multifinger transistor has been recognized as the standard layout for RF circuit design. In this paper, two new layouts derived from the standard one, i.e., narrow-OD and multi-OD, were implemented, trying to enhance the transverse stress (σ⊥) from STI. The primary ob-jective is to investigate STI transverse stress effect on effective mobility (μeff), transconductance (Gm), cutoff frequency (fT),
fMAX, and, most importantly, the low-frequency noise (LFN)
for both RF and analog circuit design.
II. DEVICEFABRICATION ANDCHARACTERIZATION
In this paper, multifinger MOSFETs were fabricated in 90-nm low-leakage CMOS process with nitrided oxide of target physical thickness at 2.2 nm. The gate length drawn on the
(b) Narrow-OD device:WF× NF= 1 μm × 32 (W1N32) and 0.5 μm × 64 (W05N64). (c) Multi-OD devices:WOD× NOD= 2 μm × 1, 0.25 μm × 8,
and 0.125μm × 16.
layout is 90 nm, i.e., Ldrawn= 90 nm, and the total channel
width Wtot is fixed at 32 μm. In order to investigate the stress
and interface traps generated from the STI process, two kinds of new layouts derived from multifinger MOSFET, i.e., multi-OD and narrow-multi-OD, were designed and implemented. Note that OD means oxide diffusion, which is equivalent to active area (generally denoted as AA). Fig. 1(a)–(c) displays the device layouts for standard, narrow-OD, and multi-OD, respectively. The narrow-OD devices illustrated in Fig. 1(b) were designed with simultaneously varied NF and WF under a specified total
width, i.e., Wtot = WF × NF. For this group of structures, WF× NF = 2 μm × 16, 1 μm × 32, and 0.5 μm × 64
cor-responding to finger width Wtot= 32 μm were fabricated in
this work. The multi-OD devices shown in Fig. 1(c) represent multiple-OD fingers with simultaneously varied OD finger width (WOD) and OD finger number (NOD) under a specified
finger width, which is WF = WOD× NOD. For this category
of devices, the polygate finger number NF is fixed at 16, and
WOD× NOD= 2 μm × 1, 0.25 μm × 8, and 0.125 μm × 16,
corresponding to finger width WF = 2 μm. Note that the
polygate-edge/OD-edge distance along the direction of channel length is fixed at 0.5 μm for both narrow-OD and multi-OD devices.
S-parameters were measured by an Agilent network analyzer E8364B for high-frequency characterization and ac parameter extraction. Open de-embedding was performed to remove the parasitic capacitances from the pads and interconnection lines, and short de-embedding was done to eliminate the parasitic resistances and inductances originated from the metal inter-connection. Fig. 2 demonstrates the LFN measurement system, which consists of an Agilent dynamic signal analyzer (DSA 35670) and low-noise amplifier (LNA SR570). The aforemen-tioned system was employed to measure the power spectral density of drain current noise, i.e., SID, which is the so-called
LFN. In this paper, the LFN was measured from multifinger MOSFETs under various gate voltages (VGS) and fixed drain
voltage at VDS= 50 mV. Note that VGS is converted as gate
overdrive, i.e., VGT= VGS− VT to offset VT variation among
different devices. The LFN measurement generally covers a wide frequency range of 4 Hz–10 kHz. The aforementioned measurement for dc and LFN characterization has been carried out on 10–15 dies for a statistical analysis.
The charge-pumping (CP) current system was built up, as shown in Fig. 3(a), for interface trap density (Nit)
measure-ment. The CP method proposed by Elliot [12] with sweeping base and fixed amplitude was applied to extract Nit from the
Fig. 2. LFN measurement system setup consisting of an Agilent dynamic signal analyzer (DSA 35670), low noise amplifier (LNA SR570), and Agilent 4156B for dc power supply. The measurement is automatically controlled by Agilent ICCAP.
Fig. 3. (a) CP measurement system consisting of dc source Agilent 4156B, pulse generator 81110A, and switching matrix Keithley 707A. (b) CP pulse waveform, wheretrandtfare the rising and falling times, andVbaseandVh
are swept from accumulation(Vbase< VFB) to inversion (Vh> VT), under
fixed pulse amplitudeVa= Vh− Vbase.
maximum CP current (ICP,max). Fig. 3(b) illustrates the pulse
waveform employed for the Elliot method, in which the base level (Vbase) is swept from accumulation to inversion while
keeping the pulse amplitude (Va) constant. Note that ICP,max
can occur under the condition of Vbase< VFB and Vbase+ Va = Vh> VT, and the accuracy is justified with a clear plateau for ICP,maxand a precise linear dependence on amplitude (Va)
and frequency (not shown).
III. LOCALSTRAINENGINEERINGEFFECT ON
NMOS PERFORMANCE
The STI stress introduced in MOSFETs with three different layouts as previously mentioned (standard, narrow-OD, and multi-OD) are illustrated in Fig. 4 to assist an analysis and understanding of layout effect on STI stress and, then, the electrical characteristics. Note that STI stress is classified as longitudinal stress, which is denoted as σ// and in parallel
with the channel length, and transverse stress, i.e., σ⊥, which is transverse to the channel length. In this paper, the longitudinal stress σ//is considered to be similar for all of the devices with
various layouts, due to fixed gate length and polygate-edge/OD-edge distance [13]. Regarding the stress favorable for mobility enhancement, it has a critical dependence on the device types and orientations. The experimental results in previous work in-dicate that tensile stress in the longitudinal direction (σ//) can
enhance electron mobility in NMOS, whereas it will degrade hole mobility in PMOS. As for the transverse stress σ⊥of our
Fig. 4. Schematic of STI stresses along the longitudinal and transverse directions, which are defined asσ//andσ⊥in MOSFETs with three different layouts. (a) Standard multifinger device. (b) Narrow-OD device. (c) Multi-OD devices.
major interest in this paper, the compressive stress from STI is expected to degrade the effective mobility μefffor both NMOS
and PMOS [6].
A. STI Transverse Stress Effect on DC Performance of Multi-OD and Narrow-OD NMOS
As previously mentioned, narrow-OD and multi-OD MOSFETs were designed to study OD width scaling effect on transverse stress σ⊥from STI in different layouts. Narrow-OD devices are shown in Fig. 4(b), wherein the Narrow-OD width (WOD= WF) is reduced to be extremely narrow and the
polygate finger number (NF) is simultaneously increased to
keep the total width (Wtot= WF × NF) unchanged.
Multi-OD devices illustrated in Fig. 4(c) features a matrix of multiple ploy fingers, as well as multiple OD fingers (NOD) with narrow
OD width (WOD). Note that WODand NODare simultaneously
varied to keep WOD× NOD the same as the finger width of
standard device, i.e., WOD× NOD= WF = 2 μm.
It has been known that the STI process generally leads to VT
lowering with channel width scaling, and it is the so-called in-verse narrow-width effect (INWE) [14]. As shown in Fig. 5, the
VT versus WODfor narrow-OD and multi-OD NMOS presents
an obvious INWE, following a universal curve for different layouts. Note that INWE is determined by collective effects from STI TCR (ΔW ), STI stress, corner field crowding, doping profile, etc. Considering VTvariations from the aforementioned
effects, VGT= VGS− VTis used for electrical characterization
and analysis.
Fig. 6(a) presents the transconductance (Gm) under varying
VGT’s, which are measured from narrow-OD NMOS with two
splits of WF× NF, such as 1 μm× 32 (W1N32) and 0.5 μm ×
64 (W05N64) and the standard one (W2N16) for compari-son. The result indicates that the smaller WOD(= WF) leads
to lower Gm and the maximum Gm (Gm,max) in W05N64
(WOD= WF = 0.5 μm) is degraded by about 8%, compared
with the standard one, i.e., W2N16 (WOD= WF = 2 μm), as
shown in Fig. 6(b). The monotonic degradation of Gm with
Fig. 5. LinearVTversusWODfor narrow-OD and multi-OD NMOSs under
the biases ofVDS= 50 mV and VBS= 0 V.
Fig. 6. (a) Transconductance Gm versus VGT. (b) Maximum
transcon-ductance Gm_max measured from narrow-OD NMOS W1N32 (WF =
1 μm, NF= 32) and W05N64 (WF = 0.5 μm, NF= 64), and standard multifinger device W2N16(WF = 2 μm, NF = 16). All of the devices have the same total finger widthWF× NF = 32 μm.
Fig. 7. (a) TransconductanceGmversusVGT. (b) Maximum
transconduc-tanceGm_maxmeasured from multi-OD NMOS OD8(NOD= 8, WOD=
0.25μm) and OD16 (NOD= 16, WOD= 0.125 μm), and standard
multifin-ger device OD1(NOD= 1, WOD= 2 μm). All of the devices have the same
polygate finger number(NF = 16) and total OD width along each gate finger ((NOD× WOD= 2 μm).
WOD scaling in narrow-OD devices suggests that the increase
in STI compressive σ⊥ is the dominant factor responsible for
μeff degradation and the resulting Gm degradation. As for
multi-OD NMOS shown in Fig. 7, the Gm,maxof OD8 (NOD=
8, WOD = 0.25 μm) is degraded by about 20%, compared with
the standard one (OD1), but the continuous scaling of WOD
to 0.125 μm in OD16 (NOD= 16, WOD= 0.125 μm) leads
to an increase in Gm, compared with OD8, and the Gm,max
degradation, compared with the standard one, is shrunk to 11%. The result looks very interesting and cannot be explained by STI compressive stress alone. Note that the statistical variations of VT and Gm remain less than 2% from measurement on 10–15 dies, and it ensures the experimental results a high confidence level.
Δμ
μ0 = −(k⊥
σ⊥+ k//σ//) (1)
where
μ0 mobility free from STI-stress-induced degradation;
Δμ mobility variation due to STI stress;
σ⊥ transverse stress perpendicular to the direction of the channel length;
σ// longitudinal stress along with the direction of the channel
length;
k⊥ first order of coefficient expressing mobility variation proportional to σ⊥;
k// first order of coefficient expressing mobility variation
proportional to σ//. Then Δμ μ0 ∼ =−k⊥σ⊥ (2)
where σ⊥is a function of gate width expressed by
σ⊥= −k · log(WOD) + k0 (3)
and can be written as another expression given by
σ⊥= k · log W ref WOD (4) where WOD× NOD= WF. (5)
In the preceding expressions, both longitudinal stress σ// and
transverse stress σ⊥ are considered in the original model. For multifinger MOSFETs, σ// limits its effect to the polygate at
the two ends. Therefore, σ// σ⊥for all of the polygates other
than those at the two ends and it leads to the approximation of (1) to (2).
According to (3) or (4), it is proposed that Gmshould
de-crease with the reduction in WODsince the mobility decreases
as the transverse compressive stress σ⊥ increases with WOD
scaling.
However, in this work, we found that OD width scaling from WOD= 0.25 μm in OD8 to WOD= 0.125 μm in OD16
led to an increase in Gm,max, as shown in Fig. 7, rather than
degradation predicted by the stress model in (1)–(5). This observation suggests that the transverse compressive stress σ⊥
from STI, which is maximized in OD16 due to the minimum
WOD, cannot fully explain the largest Gm,max degradation in
OD8, instead of OD16. The experimental results suggest that the variation of Gm with WOD scaling is determined by not
only STI stress effect on mobility (μeff) but also STI TCR
Leff Gm=∂V∂IDS GS = WeffCoxμeff VDS Leff . (7) Let β = Cox VDS Leff (8) μeff(WOD) = μ0+ Δμ(WOD) = μ0 1− k · log W ref WOD (9) Weff = (WOD+ ΔW ) × NOD× NF. (10) Then Gm= βμ0 1− k · log W ref WOD (WOD+ ΔW )NODNF (11) where ΔW is the increase in OD finger width due to STI TCR, and NF, NOD, and WODare defined in Fig. 1.
In this paper, the standard device with WF = WOD= 2 μm
is adopted as the reference, i.e., Wref= 2 μm to minimize the
transverse stress σ⊥ and its impact on mobility. The derived model given by (9) and (11) can accurately predict μeffand Gm
measured from multifinger devices with various OD layouts, such as standard, narrow-OD, and multi-OD.
Fig. 8(a) and (b) shows that simultaneous best fitting to
μeff and Gm for multi-OD NMOS can be realized under the
condition of ΔW = 43 nm and k = 0.2888. Note that ΔW is dependent on the OD layout and varies between the stan-dard and multi-OD NMOSs. For a stanstan-dard device with more gradient trench profile, ΔW = 24 nm appears to be smaller than that of multi-OD devices. For narrow-OD devices, even with minimum OD width in W05N64, its OD width (WOD= WF = 0.5 μm) is four times larger than that of OD16 (WOD=
0.125 μm), and ΔW effect is not strong enough to overcome
μeff degradation from STI stress. It can be understood that the
ΔW ratio calculated by ΔW _ratio =ΔW × NOD× NF Weff = ΔW WOD+ ΔW (12) WOD= WF NOD (13) is about 10.6% for narrow-OD device W05N64 with WOD= WF = 0.5 μm, whereas that of multi-OD device OD16 with
WOD= 0.125 μm is significantly increased to 32.1%, which
is about three times larger than that of narrow-OD device W05N64.
Fig. 8. (a) Measuredμeffand the fitting by model (9). (b) MeasuredGmand the fitting by model (11). The simultaneous best fitting for multi-OD NMOS was realized under the condition ofΔW = 43 nm and k = 0.2888.
Fig. 9. Interface trap densityNitof W2N16, W1N32, and W05N64 devices
extracted by usingWeff, which is measured atVD= VS= VB= 0 V and
VG= Vamp= 1.2 V.
Fig. 10. Interface trap densityNitof OD1 and OD16 devices extracted by
usingWeffandW , measured at VD= VS= VB= 0 V and VG= Vamp=
1.2 V.Weff = (WOD+ ΔW )NOD∗ NFW = WODNOD∗ NF.
B. Interface Traps of Narrow-OD and Multi-OD NMOS
Strain effect on interface traps and the resulting impact on carrier mobility is one more critical concern for the deployment of strain engineering in the state-of-the-art process. Figs. 9 and 10 present the interface trap density Nit extracted by the CP
current method, according to
Icp_max= qfWeffLNit (14)
for narrow-OD and multi-OD devices, respectively, where
Icp,maxis the maximum of the measured CP current, f is the
frequency of the applied pulse waveform, and L is the gate length of the device under test. Note that the effective width
Weff is used to reflect the ΔW effect.
As shown in Fig. 9, the Nit extracted from narrow-OD
NMOS indicates nearly the same distribution for W2N16 and W1N32, and a minor decrease in W05N64 with minimal
Fig. 11. LFN SID/IDS2 measured from the standard NMOS W2N16
and narrow-OD NMOS W05N64, under the biases of VDS= 50 mV and
VGT= 0.5 V.
WF(= WOD) in this category. The results just disapprove the
conventional consideration that the narrower OD width may lead to higher Nit due to an increase in STI stress σ⊥. As for
multi-OD NMOS in Fig. 10, OD16 with minimal OD width (WOD= 0.125 μm) reveals apparently larger Nit, compared
with the standard one (OD1). The result suggests that extremely narrow OD combined with minimal OD-to-OD space in multi-OD devices may introduce a significant increase in Nitdue to a
substantially steeper trench profile, compared with narrow-OD devices. The extra trap density in the sidewall also contributes to the higher Nitof OD16. Note that ΔW should be considered
to accurately determine the effective active area and Nit in
devices with extremely narrow WOD. The increase in Nit of
OD16, which is normalized to that of OD1 and denoted as ΔNit(OD16,OD1)/Nit(OD1), is as large as 55% when ΔW is
neglected and reduced to near 10% when ΔW is considered and Weffis taken.
C. LFNSID/IDS2 in Narrow-OD and Multi-OD NMOS
Fig. 11 presents LFN in terms of SID/IDS2 measured from
narrow-OD NMOS with minimum OD width, i.e., W05N64 (WOD= 0.5 μm) and the comparison with the standard one,
i.e., W2N16 (WOD= 2 μm). Similarly, Fig. 12 makes a
com-parison of SID/IDS2 between multi-OD NMOS with minimal
OD width, i.e., OD16 (WOD= 0.125 μm) and the standard
one (OD1, WOD= 2 μm). Note that the noise spectra for all
of the devices (standard, narrow-OD, and multi-OD) follow 1/f characteristics over a wide frequency domain from 10 Hz to 10 kHz. The measured LFN manifests itself as a typical flicker noise.
As shown in Fig. 11, the narrow-OD NMOS W05N64 presents lower SID/IDS2 than the standard device W2N16.
The result looks consistent with the lower Nit for narrower
OD width, as shown in Fig. 9. More rigorously, the larger
Weff for narrower OD due to the ΔW effect have to be
considered and will be discussed later. As for multi-OD de-vices shown in Fig. 12, it is interesting to note that OD16 with extremely narrow WOD to 0.125 μm presents lower SID/IDS2 than the standard one (OD1, WOD= 2 μm)), even
though the Nitof OD16 is somewhat higher than that of OD1
Fig. 12. LFN SID/IDS2 measured from the standard NMOS OD1
(NOD= 1, WOD= 2 μm) and multi-OD NMOS OD16 (NOD=
16, WOD= 0.125 μm) under the biases of VDS= 50 mV and VGT= 0.5 V.
Fig. 13. MeasuredSID/IDS2 versus IDS underVGT= 50 mV and
vari-ousVGT (0.1–0.7 V) for standard NMOS W2N16 and narrow-OD NMOS
W05N64.
narrow-OD and multi-OD NMOS is in contradiction with the general expectation and suggests that ΔW from STI and its effect on Weff appears to be an important factor in explaining
the extraordinary results.
To further explore the mechanism responsible for LFN, the
SID/I2
DS measured at 50 Hz and under various VGT’s are
plotted versus IDS for narrow-OD and multi-OD NMOS, as
shown in Figs. 13 and 14, respectively. Note that LFN data have been collected from ten devices for each layout to perform a statistical analysis. Herein, the measured SID/IDS2 follows
a function proportional to 1/I2
DS over the whole range of
bias conditions (VGT= 0.1−0.7 V), which indicates that the
number fluctuation model given by
SID I2 DS = q2kBT λNit WeffLCox2 1 f G2 m I2 DS (15) is the dominant mechanism governing NMOS devices’ LFN, where Nit is the density of interface traps at quasi-Fermi
level [16].
The proposed number fluctuation model suggests that the
SID/IDS2 of NMOS is proportional to Nit/Weff and predicts
the decrease in LFN with increasing effective width Weff. It
was expected that the increase in compressive transverse stress
σ⊥ as well as interface traps Nit suffered by OD16 device
might aggravate interface scattering effect and increase the flicker noise [17]. However, the larger Weff may compensate or
even overcome these effects. The aforementioned mechanism
Fig. 14. MeasuredSID/IDS2 versusIDSunderVGT= 50 mV and various
VGT(0.1–0.7 V) for standard NMOS OD1(NOD= 1, WOD= 2 μm) and
multi-OD NMOS OD16(NOD= 16, WOD= 0.125 μm).
Fig. 15. Statistical distribution of LFNSID/IDS2 measured from ten dies for
multi-OD and narrow-OD NMOSs.
can explain why the multi-OD devices with extremely narrow
WOD, such as OD16, can have lower LFN, compared with OD1. Fig. 15 indicates the statistical distribution of SID/IDS2
measured from ten dies for narrow-OD and multi-OD NMOS devices to further investigate OD width scaling effect on LFN. The ratio of OD16:OD1 is in the range of 40%–87%. According to (15), the ΔW effect can lead to 32% increase in Weff for
OD16 and then 24% lower LFN, i.e., OD16 : OD1 = 76% from ΔW effect alone. Considering the statistical distribution of Nit
shown in Fig. 10, the increase in Weff of OD16 leads to a
decrease in Nit, and the ratio of OD16:OD1 is about 1.2 for the
mean value and 1.13 for the maximum in the distribution. The combined effect from ΔW and Nitindeed leads to 10%–15%
lower LFN in OD16 than OD1. The statistical data suggest that the ΔW effect may not be the only factor but is the primary factor contributing to lower LFN.
For narrow-OD devices, the Nit is similar between W2N16
and W05N64 (Fig. 8), and the larger Weff in W05N64 can
significantly overwhelm Nit and the stress effects. As a
re-sult, the smaller OD width in W05N64 leads to lower LFN (SID/IDS2 ), compared with W2N16. The investigation of layout
effects on LFN in multifinger MOSFETs discloses an interest-ing and important phenomenon that STI stress collaboratinterest-ing with STI TCR-induced ΔW constitutes the primary mechanism responsible for the OD width scaling effect on Gmand LFN.
D. High-Frequency Performance in Narrow-OD and Multi-OD NMOSs
The potential impact from the aforementioned STI stress and TCR-induced ΔW on high-frequency performance is of one
Fig. 16. Cutoff frequencyfTversusVGTmeasured from narrow-OD NMOS underVDS= 1.2 V and varying VGT.fT is extracted from the unit current
gain|H21| = 1.
Fig. 17. Cutoff frequencyfTversusVGTmeasured from multi-OD NMOS
underVDS= 1.2 V and varying VGT.fT is extracted from unit current gain
|H21| = 1.
more special concern for multifinger MOSFETs in RF circuit design. Fig. 16 illustrates the cutoff frequency fT measured
from standard (W2N16) and narrow-OD (W1N32, W05N64) NMOS under varying VGT. Note that H-parameters were
con-verted from S-parameters after two-step de-embedding (open and short), and then, fT was extracted from the extrapolation
of|H21| to unity current gain. The experimental results reveal
that narrow-OD devices suffer significant degradation of fT and
the peak fT drops from 116 GHz for W2N16 to 78 GHz for
W05N64. Referring to fT = Gm 2π C2 gg− Cgd2 (16)
which is an analytical model for calculating fT [18], it is
pre-dicted that fT degradation may be originated from degradation
of Gmor increase in Cgg. For narrow-OD devices, the smallest Gmappearing in W05N64 (Fig. 6) suggests one of the factors
responsible for the worst fT. Furthermore, Cggmeasured from
narrow-OD NMOS indicates the largest one for W05N64 (not shown). The collective effect from Gm and Cgg can explain fT degradation in narrow-OD devices. Regarding OD width
scaling effect on fT in multi-OD NMOS, Fig. 17 demonstrates
that OD16 with the smallest OD width (WOD= 0.125 μm)
reveals the worst fT. The peak fTdrops from 101 GHz for OD1 to 75 GHz for OD16. Cgg measured from multi-OD NMOS
indicates that OD16 suffers about 20% larger Cgg than that
of OD1 (not shown). The collective effect from smaller Gm
(Fig. 7) and larger Cggis responsible for fT degradation.
Fig. 18. fMAXversusVGTmeasured from narrow-OD NMOS underVDS=
1.2 V and varyingVGT.fMAXis determined by the unilateral gain method.
Fig. 19. fMAXversusVGTmeasured from multi-OD NMOS underVDS=
1.2 V and varyingVGT.fMAXis determined by the unilateral gain method.
The maximum oscillation frequency fMAX is another
im-portant performance parameter for RF circuit design, particu-larly for power amplifiers. The impact of layout variation on
fMAX in multifinger MOSFET is investigated as follows: In
this paper, fMAX was determined by the conventionally used
unilateral gain method. Fig. 18 presents fMAXextracted from
standard and narrow-OD NMOS. It reveals a very interest-ing result that W1N32 attains about 10 GHz higher fMAX
than the standard (W2N16), even though W1N32 suffers the lower fT than W2N16 (Fig. 16). However, W05N64 with the lowest fT remains the worst in terms of fMAX. Through an
equivalent circuit analysis on unilateral gain (U), fMAXcan be
approximated by
fMAX =
fT
2Rg(gDS+ 2πfTCgd) + gDS(Ri+ Rs)
(17) in which Rgand fT appear as two key parameters controlling
fMAX [11]. This expression predicts that the higher fT and
lower Rg can increase fMAX. For narrow-OD devices, the
smaller WF(= WOD) and larger NFplay a multiplied effect to
reduce Rg(not shown). The higher fMAXachieved by W1N32,
compared with W2N16, suggests that the significant reduction in Rg can compensate or even overcome the impact from fT
degradation. However, the advantage of Rgsuppression cannot
be obtained by multi-OD devices due to the feature of fixed
NF [Fig. 1(c)]. The fMAX measured from multi-OD NMOS,
as shown in Fig. 19, proves the expectation that the trend of
fMAXsimply follows that of fT (Fig. 17), i.e., the smaller WOD
leads to the lower fMAX and OD16 suffers worse degradation
an abnormal Gmincrease for extremely narrow OD width to
WOD= 0.125 μm. The observed results suggest that STI stress
is not the only mechanism governing the electrical property in miniaturized devices. STI TCR-induced ΔW is identified as another key factor, which may overcome STI stress effect in determining channel current and Gm. Semi-empirical formulas
have been derived to successfully predict WOD scaling effect
on μeff and Gm. Taking this method, ΔW can be precisely
extracted based on a simultaneous best fitting to μeff and Gm,
and the resulting increase in effective width (Weff) is
dramati-cally large to about 34% for OD16 with WOD= 0.125 μm. The
larger Weff becomes, the more it contributes to reducing LFN
and overcoming Niteffect in narrow-OD and multi-OD devices
with sufficiently small WOD. The reduction in LFN with OD
width scaling is the other evidence reflecting STI TCR-induced ΔW effect.
Unfortunately, the OD width scaling leads to a negative impact on high-frequency performance like fT and fMAX, due
to Gmdegradation and undesired increase in Cgg. An improved
open de-embedding method can reduce the parasitic capac-itances from intermetal coupling but cannot eliminate gate-related fringing capacitances. The multifinger MOSFETs with miniaturized OD width cannot prevent from fT degradation.
The tradeoff between LFN and high-frequency performance identified from this work provides an important layout guide-line for analog and RF circuit design.
ACKNOWLEDGMENT
The authors would like to thank the National Device Labo-ratory (NDL) for their support during noise measurement and the Chip Implementation Center (CiC) for test key tape-out and device fabrication.
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Kuo-Liang Yeh (M’09) received the B.S.E.E.
de-gree from National Chiao-Tung University (NCTU), Hsinchu, Taiwan, in 1995 and the M.S.E.E. degree from National Taiwan University, Taipei, Taiwan, in 1997. He is currently working toward the Ph.D. degree in electronics engineering in the Institute of Electronics Engineering, NCTU.
In 1999, he joined Taiwan Semiconductor Man-ufactory Company Inc., Hsinchu, where he has worked on process integration and yield improve-ment. From 2004 to 2007, he has been a Senior Engineer with MediaTek Inc., Hsinchu. He is currently a Senior Manager with the Silicon Motion Technology Corporation, Hsinchu. He has authored more than ten technical publications in international journals and conference proceedings. His research interests include the characterization and parameter extraction of CMOS devices for modeling and circuit simulation, as well as the protection of intellectual property rights.
device design and VLSI technology development. In 1984, she joined the ERSO/ITRI, where she had been engaged in semiconductor integrated circuit technologies with a broad scope that covers high-voltage, high-power, submi-crometer project, and high-speed SRAM technologies. From 1994 to 1998, she was with Macronix International Corporation and engaged in high-density and
since 2008. She has authored or coauthored more than 60 technical papers. She is the holder of 19 U.S. patents in her professional field. Her current research interests include RF/MS CMOS device design and modeling for low-power and low-noise nanoscale CMOS noise modeling and strain engineering effects, broadband and scalable inductors modeling, novel nonvolatile memory technologies, and device integration technologies for system-on-chip.
