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A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-/spl mu/m CMOS technology

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Academic year: 2021

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Fig.  2.  Proposed topology  of  two-stage low-voltage  CMOS  LNA.
Fig.  3.  The  top  three  metal  layers  are  shunted  to  reduce  the  parasitic resistance of the inductor
Fig.  7.  I-dB compression point  and  third order  intercepts point  measurement

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