UNIVERSITY OF CALIFORNIA, SAN DIEGO Enabling Techniques for Low Power, High Performance Fractional-

UNIVERSITY OF CALIFORNIA, SAN DIEGO

Enabling Techniques for Low Power, High Performance Fractional-N Frequency Synthesizers

A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy

in

Electrical Engineering (Electronic Circuits and Systems)

by

Ashok Swaminathan

Committee in charge:

Professor Ian Galton, Chair Professor Peter Asbeck

Professor William Griswold Professor Tom T. Liu Professor James Zeidler

2006

3222048 2006

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ii Copyright

Ashok Swaminathan, 2006 All rights reserved.

iv

To Mom, Dad, and Deeps.

v

TABLE OF CONTENTS

Signature Page ... iii

Dedication... iv

Table of Contents ...v

List of Figures... vii

List of Tables... ix

Acknowledgements...x

Vita... xi

Abstract... xii

Chapter1 : A Calibration Technique for Phase Noise Canceling Fractional-N Phase- Locked Loops 1 Abstract...1

I. Introduction ...1

II. Calibration in Phase noise Canceling Fractional-N PLL...3

A. The Problem...3

B. Calibration Signal Generation ...8

III. Continuous-time Gain Calibration Technique...10

IV. Signal Processing Details ...14

A. Signal Processing Model ...14

B. Calibration Loop Performance...16

V. Simulations and Limitations ...18

VI. Conclusions ...21

Acknowledgements ...21

Appendix A...22

Appendix B...23

References ...30

Chapter 2 : A Digital Quantizer with Shaped Quantization Noise that Remains Well Behaved after Non-linear Distortion 32 Abstract...32

I. Introduction ...32

II. Segmented Quantization...34

A. Spectral Properties of Interest...34

B. Signal Processing Model of the Segmented Quantizer...35

C. Example Segmented Quantizer and Appearance of Spurious Tones 38 III. Theory for Tone-Free Quantization Sequences ...41

vi

IV. A Segmented Quantizer that Satisfies Theorems 1 and 2 ...55

A. Verification of Example Matrices ...55

B. Simulation Results and Comparison to a ∆Σ Modulator ...60

Acknowledgements ...62

References ...63

Chapter 3 : A Wideband 2.4GHz Delta-Sigma Fractional-N PLL with Calibrated Phase Noise Cancellation...65

Abstract...65

I. Introduction ...65

II. Calibrated Phase Noise Canceling Technique ...68

A. The Problem with Phase-Noise Canceling PLLs...68

B. Calibration for Phase-Noise Canceling PLLs ...71

III. Circuit Issues ...75

A. Overview...75

B. Power Consumption Issues...77

C. Dynamic Bias Technique ...78

D. Phase/Frequency Detector and CP...79

E. VCO and Divider ...82

F. Digital ...83

G. Loop Filter and DAC ...84

H. Calibration Circuitry...86

IV. Measurement Results...87

V. Conclusions...91

Acknowledgements ...92

References ...92

vii

LIST OF FIGURES

Figure 1: Phase Noise Canceling PLL; a) Block Diagram; b) Timing diagram, ideal matching; c) Timing diagram, DAC Gain mismatch...5 Figure 2: Previously Published Calibration Method for Phase Noise Canceling PLL...6 Figure 3: Sign of Integrated Quantization Error for a 2^nd order ∆Σ Modulator...7 Figure 4: Correlation signals based on equant[n]...9 Figure 5: High-level Functional Diagram of Calibrated Fractional-N PLL ...11 Figure 6: PLL Loop Modification for Calibration; a) Modified LF and VCO; b)

Equivalent circuit for PLL ...12 Figure 7: Loop Filter Voltages and Calibration Control Voltage ...13 Figure 8: a) Calibration Loop Circuit; b) Continuous-time Model; c) Equivalent

Discrete-time Signal Processing Model...14 Figure 9: Settling Time for Calibration Technique ...19 Figure 10: PLL Phase Noise; a) Without Calibration; b) Calibration enabled for

β=0.9...20 Figure 11: Calibration enabled for random mismatches in PLL loop...20 Figure 12: a) High-level block diagram of the segmented quantizer; b) quantization

block details; c) signal processing model ...36 Figure 13: Estimated power spectra of the quantization noise and its running sum

for the SQ presented in Section II...39 Figure 14: Estimated power spectra of the square of the running sum of the

quantization noise for the SQ presented in Section II. ...40 Figure 15: A first-order ∆Σ modulator. ...60 Figure 16: Estimated power spectra of a) the quantization noise sequences, and b)

the running sums of the quantization noise sequences of the first-order ∆Σ modulator and the segmented quantizer presented in Section IV before and after application of non-linear distortion. ...61 Figure 17: High-level functional diagram of the implemented PLL ...67 Figure 18: Phase Noise Canceling PLL; a) Block Diagram; b) Timing Diagram ...69

viii

Figure 19: PLL Loop Modification for Calibration; a) Modified LF and VCO; b) Equivalent circuit for PLL; c) Equivalent single-ended half circuit for

Calibration system ...73

Figure 20: Effect of PLL Bandwidth on component noise requirements; a) 100kHz bandwidth; b) 500kHz bandwidth...76

Figure 21: CP dynamic bias technique ...79

Figure 22: PFD and Buffer schematic ...80

Figure 23: CP schematic ...81

Figure 24: VCO schematic...82

Figure 25: Details of the mismatch-shaping digital encoder ...83

Figure 26: DAC schematic ...85

Figure 27: Calibration circuit...86

Figure 28: Phase Noise Performance...89

Figure 29: Calibration Loop Settling Performance...89

Figure 30: PLL Output Spectrum ...90

Figure 31: Die Photograph...91

ix

LIST OF TABLES

Table 1: Parameters for Fractional-N PLL from Figure 2 ...18 Table 2: Performance Parameters ...88

x

ACKNOWLEDGEMENTS

Chapter 1, in full, is in preparation for submission for publication to the IEEE Transactions on Circuits and Systems I: Regular Papers. The dissertation author is the primary investigator and author of this paper. Ian Galton supervised the research which forms the basis for this paper.

Chapter 2, in full, has been submitted for review to the IEEE Transactions on Signal Processing. The dissertation author was the primary investigator and author.

Ian Galton supervised the research which forms the basis of this paper. Andrea Pani- gada contributed to the theorem statements, and Elias Masry contributed to the struc- ture of the proofs.

Chapter 3, in full, is in preparation for submission to the IEEE Journal of Solid-State Circuits. The dissertation author was the primary investigator and author.

Ian Galton supervised the research, which forms the basis for this paper. Kevin J.

Wang contributed to the design and implementation of the charge pump power reduc- tion technique.

xi VITA

1994 B. A. Sc., University of Waterloo

1994 – 1997 Research Assistant, Department of Electronics, Carleton University

1997 M. Eng., Carleton University

1997 – 2000 Staff Engineer, Skyworks Solutions, Ottawa 2000 – 2006 Graduate Student Researcher,

University of California, San Diego

2006 Ph. D., University of California, San Diego

xii

ABSTRACT OF THE DISSERTATION

Enabling Techniques for Low Power, High Performance Fractional-N Frequency Synthesizers

by

Ashok Swaminathan

Doctor of Philosophy in Electrical Engineering (Electronic Circuits and Systems)

University of California, San Diego, 2006

Professor Ian Galton, Chair

Delta-sigma fractional-N phase-locked loops are used to generate high quality radio-frequency signals for use in wireless applications. To reduce the phase noise inherent to these systems, a digital-to-analog converter is used to cancel the error in- troduced by the fractional division process, however matching between the digital-to- analog converter and the phase-locked loop circuitry place a limit on the amount of phase noise reduction that can be achieved. Furthermore, circuit non-linearity results

xiii

in the appearance of spurious tones in the phase-locked loop output.

This dissertation outlines a calibration technique, and a digital quantization technique that provide solutions to these two problems. The calibration technique re- sults in improved phase noise performance by adjusting the digital-to-analog converter gain, and thus providing better matching between the phase-locked loop circuitry and digital-to-analog converter. The digital quantization technique results in no spurious tones when specified non-linearity is applied to the quantizer output sequence and er- ror. The calibration technique was implemented in an integrated circuit, which achieves state-of-the-art performance when compared to currently published phase- locked loops and allows for all circuitry to be integrated onto a single chip. Chapter 1 presents the calibration technique, as well as a theoretical analysis of the stability.

Chapter 2 presents details on the digital quantization technique, and a mathematical proof of the absence of spurious tones. In chapter 3, results from an implemented cir- cuit are presented, which verify the behaviour of the technique presented in chapter 1.

Chapter 1 : A Calibration Technique for Phase Noise Canceling Fractional-N Phase-Locked Loops

A

Phase-noise canceling phase-locked loops (PLL) are sensitive to the matching between the phase noise canceling and PLL circuitry. Any mismatch places a limit on the quality of the phase noise cancellation, and as a result constrains the design of the PLL to accommodate the mismatch. This paper presents a calibration technique which estimates the mismatch, and adjusts the equivalent gain of the phase noise canceling circuitry to improve the degree of phase noise cancellation, thus allowing for more PLL design choices, such as widening the PLL loop bandwidth. The presented tech- nique offers faster settling time over current solutions, which in turn enables its use in low power wireless systems.

I.

I

Delta-Sigma Fractional-N Phase-Locked Loops (PLL) are widely used in ap- plications requiring the generation of a periodic signal with fine frequency tuning [1], however noise from the delta-sigma modulator degrades the phase noise performance of the PLL. This requires the bandwidth to be sufficiently narrow in order to attenuate the phase noise to acceptable limits dictated by the PLL requirements. A recent en- hancement to delta-sigma fractional-N PLLs is the use of a Digital-to-Analog Con- verter (DAC) to reduce the phase noise induced by the fractional division process [2,3,4]. This technique facilitates the ability to widen the bandwidth of the PLL, the two main advantages of which are making it possible to integrate the passive loop fil-

1

ter on chip, and reducing the sensitivity of the voltage-controlled oscillator (VCO) to pulling [5].

In order to ensure ideal phase-noise cancellation, the DAC gain must be matched to an equivalent gain in the PLL circuitry. Any mismatch results in imperfect cancellation, leading to a limit on the phase noise performance that can be achieved for the PLL [6]. A calibration technique to reduce this gain mismatch has been pre- sented in [7], and has been shown to result in phase noise cancellation of up to 30dB.

However this calibration system has a low loop bandwidth, and therefore a long set- tling time, constraining its use due to the fact that wireless transceivers often power the fractional-N PLL down when not receiving or transmitting in order to reduce power dissipation.

This paper presents a calibration technique suitable for phase noise canceling fractional-N PLLs. The presented technique has three advantages over the scheme in [7]. There is no sampling of the loop filter voltage that can result in an increased spu- rious tone around the carrier at an offset of the reference frequency. Calibration sig- nals are used which result in improved performance of the calibration loop when non- ideal factors are taken into account, such as DC offset. Finally, the architecture of the calibration technique inherently has reduced offsets, and no quantization noise which allows for a much faster settling time than attainable with currently implemented methods. The result is that the calibration technique presented is suitable for back- ground calibration in wireless systems.

Section II outlines the phase noise canceling PLL matching problem, as well as discussing current methods of solving this. Section III presents the new calibration technique. Section IV presents a suitable signal-processing model, used to prove the stability of the calibration loop. Section V presents a design example as well as simu- lations that verify the normal operating behaviour.

II.C

P

C

F

-N PLL

A. The Problem

A phase noise canceling fractional-N PLL is shown in Figure 1a, which con- sists of a typical fractional-N PLL plus a feed-forward current DAC. The operation of a delta-sigma fractional-N PLL is discussed at length in [1], so only the salient points necessary for understanding the calibration technique are discussed. A fractional-N PLL is never locked every reference sample due to the integer nature of the divider, i.e. Vref(t) and Vdiv(t) are never locked in phase. This results in the phase-frequency detector (PFD) and charge pump (CP) supplying an error charge each reference period into the loop filter. If the PLL is locked in frequency, this charge can be well modeled by [6]

1

0

[ ] ⁿ [ ]

CP CP VCO Q

k

Q n I T ⁻ e k

=

=

∑

where ICP is the nominal CP current, TVCO is the period of the PLL output under steady-state conditions, and eQ[n] is the shaped quantization noise from the Delta-

Sigma (∆Σ) modulator¹.

All phase noise canceling fractional-N PLL [2, 3, 4] operate on the principle that every reference period, the DAC supplies charge in the form of a pulse of current that nominally cancels the CP charge given by (1). This is shown in Figure 1b where the charge from the DAC and CP completely cancel every reference period. The DAC charge can be well modeled by [6]

1

0

[ ] ⁿ [ ] [ ]

DAC DAC DAC Q req

k

Q n I T ⁻ e k e n

=

 

= 

∑

where IDAC is the DAC full-scale current, TDAC is the duration of the DAC cur- rent pulse, and ereq[n] is the noise added by the digital requantizer. The requantizer is dithered such that ereq[n] is uncorrelated from the quantization noise of the ∆Σ modulator [8]. For ideal cancellation, ICPTVCO is equal to IDACTDAC, therefore subtracting (2) from (1) results only in charge related to the requantization noise appearing at the input to the VCO. However timing mismatches between TVCO and TDAC and current mismatches between ICP and IDAC result in a portion of the CP charge remains on the loop filter. Neglecting the requantization noise term, this charge is a scaled version of (1). The result is shown in Figure 1c, which imposes a limit on the degree of phase noise cancellation that can be achieved.

1 eQ[n] is the integer valued ∆Σ modulator quantization noise scaled by the quantization step size, and for a 2^nd order ∆Σ modulator is bounded by 2

a)

b)

Ideal Matching DAC Gain Mismatch

ref( ) V t

div( ) V t

CP( ) i t

DAC( ) i t

ctl( ) V t

ref( ) V t

div( ) V t

CP( ) i t

DAC( ) i t

ctl( ) V t

c) 2nd-Order

Digital ∆Σ Modulator N+y[n]

VCO

1

1 1

z z

−

− −

PFD and Charge

Pump

ref( ) V t

div( ) V t

[ ] y n

Q[ ] [ ] e n

e nint

Digital Requantizer DAC

Encoder

ctl( ) ( ) V t

iCPt

DAC( )

i t R

C₂ C₁

Current DAC

Channel Select

Figure 1: Phase Noise Canceling PLL; a) Block Diagram; b) Timing diagram, ideal matching; c) Timing diagram, DAC Gain mismatch

Since eQ[n] is a known quantity, the charge error on the loop filter can be sensed and IDAC adjusted such that ICPTVCO equals IDACTDAC and the charge due to eQ[n]

is completely cancelled. A method of performing this is shown in Figure 2, equivalent

to the system presented in [7]. The loop filter voltage, Vctl(t) is buffered and then mul- tiplied by a binary correlation signal, c[n]. This correlation signal must satisfy the following two requirements:

• The average of c[n] must be zero

• c[n] must be correlated with eQ[n] such that multiplying (1) by c[n] re- sults in a signal which has a non-zero average value

N+y[n]

VCO

1

1 1

z z

−

− −

PFD and Charge

Pump

y[n]

e_Q[n]

c[n]

ctl( ) V t

e_int[n]

Current DAC

DAC Encoder

PLL Output

2nd-Order Digital ∆Σ Modulator

Channel Select A/D

Converter

1

1 1

z z

−

− −

R C₂ C₁

Buffer

Digital Filter

1

1

sgn( [ ])e n_int

Digital Requantizer

CP( ) i t

DAC( ) i t

ref( ) V t

div( ) V t

Figure 2: Previously Published Calibration Method for Phase Noise Canceling PLL

These requirements ensure that the dc component of Vctl(t) does not affect the calibration of IDAC, and that the mismatch between the DAC and CP can be extracted and used in the calibration loop. The correlated signal is converted to a digital result, accumulated and filtered. The DAC bias is adjusted by switching weighted current sources. Since the correlated signal has a non-zero average value proportional to the CP and DAC mismatch, the calibration system adjusts IDAC until the mismatch be- tween ICPTVCO and IDACTDAC is minimized and there is no dc remaining at the input to the accumulator.

10^-3 10^-2 10^-1

-40 -30 -20 -10 0 10 20 30 40

Power Spectral Density

Normalized Frequency

Figure 3: Sign of Integrated Quantization Error for a 2^nd order ∆Σ∆Σ∆Σ∆Σ Modulator

This particular calibration system suffers from restrictive filtering require- ments; the correlation signal multiplied by the dc component of Vctl(t) results in a sig- nal proportional to c[n] modulating IDAC. Moreover in the case where the correlation

signal is the sign of (1), spurious tones appear in c[n]. This is shown in Figure 3 for an input of 0.01 to the 2^nd order ∆Σ modulator. It has been observed, but not proven in [2,9] that these spurs appear at multiples of the constant input times the reference fre- quency. Thus, any offsets present before correlation will result in periodic behaviour in the adjustment of IDAC, which results in unwanted spurious tones at the output of the PLL.

B. Calibration Signal Generation

For the 2^nd order ∆Σ modulator shown in Figure 1, the CP charge given in (1) can be expressed in terms of the quantizer error equant[n]²

( )

[ ] [ 1] [ 2]

CP CP VCO quant quant

Q n =I ⋅T ⋅ e n− −e n− , (3)

Thus a correlation signal can be generated which is related with the individual equant[n]

terms in (3). In particular, with sgn(x) defined as 1 when x≥0 and –1 when x<0, two correlation signals are given by

( )

sgn e_quant[n−1] , and (4)

( ) ( )

sgn [ 1] sgn [ 2]

2 [ ]

quant quant

e n e n

− − − s n

+ , (5)

where s[n] is a zero-mean ergodic, 3-level, 1^st order shaped random sequence uncorre- lated with equant[n−1] and equant[n−2] that quantizes the three-level signal given by the first term in (5) into a binary signal [10]. If the ∆Σ modulator is properly dithered (e.g. according to the conditions in [11]), then equant[n] has an asymptotically uniform

2 The quantizer error is a digital number which has been normalized by the ∆Σ quantizer step size, and for a 2^nd order ∆Σmodulator, eQ[n]=equant[n]-2 equant[n-1]+ equant[n-2]

distribution, and both (4) and (5) will be asymptotically zero-mean signals. Multiply- ing (3) by either correlation signal results in a signal that has a non-zero mean, there- fore (4) and (5) satisfy the necessary requirements for c[n]. Simulations shown in Figure 4 indicate that these choices of correlation signals have no spurious tones, hence the dc portion of Vctl(t) will not result in periodic modulation of IDAC.

10^-3 10^-2 10^-1

-60 -50 -40 -30 -20 -10 0 10 20

Normalized Frequency

Power Spectral Density

Unshaped c[n]

Shaped c[n]

Figure 4: Correlation signals based on equant[n]

With this enhancement, there remain two problems in the calibration system from Figure 2. The analog-to-digital converter (ADC) samples the buffered loop filter voltage, so the buffer must provide sufficient isolation from the sampling process to avoid causing a spurious reference tone at the output of the PLL. Significant filtering is still required to filter the ADC quantization noise, as well as the noise introduced by multiplying the dc part of Vctl(t) with c[n]. This results in an effective reduction of the

bandwidth of the calibration loop, and hence longer settling time for calibration. For the design presented in [7], the settling time is on the order of one second [12].

III.C

-

G

C

T

To overcome these problems, a calibration technique implemented in a phase- noise canceling fractional-N PLL is shown in Figure 5, with the calibration technique identified by the shaded parts in the figure. The VCO input, and loop filter are split into two equal parts, each of which have the same frequency response as in the PLL of Figure 2. The calibration circuitry consists of a continuous-time integrator and a volt- age-to-current converter that controls IDAC. To understand the system, consider the operation of the PLL from the CP and DAC to VCO as seen in Figure 6a. The calibra- tion signal generator produces c[n] given by (4) and (5), which switches the CP and DAC current, iCP(t) and iDAC(t), to either ip(t) or in(t) each reference period.

Due to the equivalence of the VCO inputs, an equivalent change on either Vp(t) or Vn(t) will result in an identical VCO frequency change, and any differential change between Vp(t) and Vn(t) will result in no change. In this manner, the same current pulse in either ip(t) or in(t) will result in the same VCO output change, therefore the correlation signal switching between ip(t) and in(t) is transparent to the VCO. The ef- fective loop filter voltage for controlling the VCO is the average of Vp(t) and Vn(t), given by Vctl(t) in Figure 6b. If the DAC and CP charges were perfectly matched, the net charge delivered to each loop filter would be zero each reference period, therefore Vp(t) and Vn(t)would settle to constant values and Vctl(t) would be at the correct value

required by the PLL. However, there are an unlimited number of possible choices for Vp(t) and Vn(t) that result in the correct value of Vctl(t) so it is impossible to predict the steady-state loop filter voltages by only considering the operation of the PLL.

N+y[n]

2R C₂/2 C₁/2

2R C₂/2 C₁/2

VCO

1

1 1

z z

−

− −

Pseudo- Random Generator

PFD and Charge

Pump

y[n]

e_Q[n]

c[n]

p( ) V t

n( ) V t

e_int[n]

Current DAC

DAC Encoder

PLL Output

p( ) i t

n( ) i t

gm Vcal

C_int C_int

Calibration Signal Generator

8 17 18

2nd-Order Digital ∆Σ Modulator

Channel Select

16 3

9

1

CP( ) i t

DAC( ) i t

ref( ) V t

div( ) V t

Figure 5: High-level Functional Diagram of Calibrated Fractional-N PLL

Next, consider the operation of the calibration loop. As an example, if the cor- relation signal is the sign of the accumulated quantization noise given in (1) [7], the result is the accumulation of positive CP charge on V_p(t) and negative CP charge on Vn(t). For the case where the DAC gain is smaller than the CP gain, Vp(t) increases

and V_n(t) decreases, causing the loop filter voltages to drift away from one another.

The differential voltage change on Vp(t) and Vn(t) also results in a differential voltage between Vcalp(t) and Vcaln(t) which is accumulated through the continuous-time integra- tor, and used to adjust I_DAC. The DAC current is adjusted such that the average differ- ential voltage between Vcalp(t) and Vcaln(t), and hence Vp(t) and Vn(t), is zero. There- fore the DAC and CP gains are matched. So, the calibration loop operating in con- junction with the PLL will cause Vp(t) and Vn(t)to each converge to unique values de- termined by the PLL output frequency and offsets within the PLL and calibration loops.

a)

b)

VCO Output

p( )

V t K_vco/2 K_vco/2

n( ) ( ) V t

iCP t

p( ) i t

n( ) i t

[ ] c n

2R C₂/2

C₁/2

2R

C₂/2 C₁/2

calp( )

V t

caln( )

V t

DAC( ) i t

R C₂ C₁

VCO Output

ctl( ) V t

K_vco

CP( ) i t

DAC( ) i t

Figure 6: PLL Loop Modification for Calibration; a) Modified LF and VCO; b) Equivalent circuit for PLL

The PLL and calibration locking behaviour are shown in Figure 7 for a 10%

mismatch between CP and DAC. Under ideal circuit behaviour, the operation of the loop is such that Vp(t) and Vn(t) converge to the same average voltage as the calibra- tion loop converges. However, non-idealities in the circuit can result in incorrect set- tling or variation of the calibration loop output, as well as cause instability if the loop parameters are not chosen properly. The following section presents a signal process- ing model, and conditions that guarantee the stability of the system.

2 3 4 5 6 7 8

x 10^-5 0

0.05 0.1

2 3 4 5 6 7 8

x 10^-5 0.6

0.62 0.64

Time

Loop Filter Voltages

Calibration Control

VoltageGain Adjust

Figure 7: Loop Filter Voltages and Calibration Control Voltage

IV.S

P

D

a)

c)

[ ] w n

β

CP[ ] Q n

DAC[ ]

Q n c n[ ]

CP( ) i t

[ ] c n

C₁/2

C₁/2

DAC( ) i t

2R

2R C₂/2

C₂/2

g_m

To DAC Bias

C_int C_int

b)

( ) w t [ ]

c n 1 e^sT

s

− −

DAC( ) i t

CP( )

i t m 1

int

g C ⋅s

1

1 1 s RC+ ⋅ Disc./Cont.

Time Converter

1 IDAC

[ ]

x n ^{G u n⋅ [ ] 1}( ^{−enT RC/ 1})

( ) i t

Figure 8: a) Calibration Loop Circuit; b) Continuous-time Model; c) Equivalent Discrete-time Signal Processing Model

The required continuous-time circuitry to implement the calibration technique

is shown in Figure 8a, consisting of a switch and passive filter followed by an ideal differential integrator³ and voltage-to-current converter with a trans-conductance of gm. The correlation signal c[n] is held constant for the duration of iCP(t) and iDAC(t) and steers the currents to either the positive or negative input of the integrator each reference cycle. The equivalent continuous-time signal processing model of the cali- bration loop is shown in Figure 8b, where c[n] is converted to a continuous-time sig- nal, and the switch is replaced by a multiplication of the correlation signal with iCP(t) and iDAC(t), and w(t) is the gain adjustment signal for the DAC.

Using (1) and (2), the CP and DAC current pulses can be well approximated by [6, 13]

0

( ) [ ] ( )

CP CP

n

i t ^∞ Q nδ t nT

=

=

∑

0

( ) ^DAC[ ] ( ) _DAC( )

DAC T

n DAC

Q n

i t t nT p t

T δ

∞

=

 

= − ∗



∑

where T is the reference period, δ(t) is the impulse function, * is the convolution op- erator and ( )

TDAC

p t is a rectangular unit-amplitude pulse of width T_DAC. Taking the feedback signal w(t) into account, the input to the calibration loop, i(t) is

0 0

( ) [ ] ( ) [ ] ( ) ( ) ( )

DAC

CP DAC T

n n DAC

Q n

i t Q n t nT t nT p t w t

δ T δ

∞ ∞

= =

  

=

∑

∑

Since the output of the calibration loop, w(t) varies during the duration of a DAC pulse, it is impossible to maintain a constant w(t) for all DAC pulses which re-

3 A non-ideal integrator results in the addition of extra poles and zeros in the calibration loop, and with proper amplifier design, can be made negligible.

sults in perfect calibration of the DAC gain. However in all applications, a minimum level of gain matching performance, ∆, can be specified such that

(1− ∆)I T_{CP VCO} < I_{DAC DAC}T < + ∆(1 )I T_{CP VCO} (9)

Appendix A outlines the necessary conditions on the calibration loop parameters to ensure that the variation in w(t) is small with respect to ∆, which can be given as

1

1

/ /

1 1

TDAC RC CP VCO m

T RC int DAC

I T g e

C I e

−

−

− < ∆

− , (10)

therefore w(t) can be assumed to be constant for the duration of a DAC pulse.

Sampling w(t) uniformly at intervals of T, the system can be modeled as a dis- crete-time system with charge inputs defined in (1) and (2), and the impulse response of the discrete-time filter is simply the continuous-time impulse response of the filter and integrator in Figure 8b sampled at t = nT. This model is shown in Figure 8c, where the mismatch between CP and DAC paths is explicitly represented by the pa- rameter β, ICPTVCO = IDACTDAC, and the corresponding discrete-time impulse responses are also shown. The parameter G can be readily derived from Figure 8b as

m int DAC

G g

C I

= ⋅ . (11)

B. Calibration Loop Performance

The two equations used to describe the calibration loop are

{ }

[ ] [ ] _CP[ ] ( [ ]) _DAC[ ]

x n =c n ⋅ Q n − β+w n Q n (12)

( )

{

}

[ ] [ ] [ ] 1 ^{nT RC}

w n = ⋅G x n ∗ u n −e⁻ (13)

where u[n] is the unit step function. Since (12) and (13) represent a non-linear feed- back system, a closed-form expression for w[n] can be derived, and then used to evaluate the conditions under which bounded-input, bounded-output (BIBO) stability holds. Define

0 [ ] [ ] [ ], and

[ ] [ ] [ ],

CP CP

R req DAC DAC req

C C n Q n c n

C C n I T e n c n

+ ⋅

+ ⋅ ⋅ ⋅

(14)

where C₀ and C_R are the sample averages of Q_CP[n]⋅c[n] and I_DAC⋅T_DAC⋅e_req[n]⋅c[n] re- spectively. Claim 1 in Appendix B shows that for the choices of c[n] given in (4) and (5), C0 exists, and furthermore is given by

2 2 1 2

N

CP VCO N

I ⋅T ⋅ ⁻ − (15)

To prove the calibration loop is stable, the equations (12) and (13), and the result in (15) can be used in Claim 2 in Appendix B. The stability condition required is that

(

)

G −e⁻ Q n < (16)

for all DAC charge samples. From (11), (16) and the fact that |QDAC[n]| ≤ IDACTDAC

reduces to

(

)

m DAC

int

g e T

C

− − < (17)

The following section outlines a practical example which shows that for typical values

for calibration loop parameters, (17) is satisfied and the loop is stable.

V.S

L

Suppose that a calibration loop is to be designed for a Bluetooth compliant fractional-N PLL with a block diagram shown in Figure 5 and component values given in Table 1. The component requirements for the PLL and phase noise cancellation system are determined independently of the calibration technique, and will not be dis- cussed as they are presented in [6]. The PLL parameters from Table 1 yield a PLL loop bandwidth of approximately 443kHz. In the absence of phase noise cancellation, the phase noise at a 3MHz offset can be calculated from [1] as –84dBc/Hz. To meet the Bluetooth specification of less than –120dBc/Hz at a 3MHz offset, the DAC gain matching must be accurate to 0.01. Furthermore, since transmission packets for Blue- tooth are less than 625µs, the calibration loop must settle within a fraction of that time.

For adequate noise performance, a settling time of 50µs to 0.01 accuracy is required.

Table 1: Parameters for Fractional-N PLL from Figure 2

PLL Parameters

Reference Frequency, T 12 MHz

Output Frequency 2.4 – 2.5 GHz

∆Σ Quantizer step, 2^N 2¹⁶

Charge Pump Current, ICP 2mA

Nominal DAC Current, IDAC 1mA

VCO gain, K_VCO 120MHz/V

Loop Filter Resistor, R 2.5 kΩ

Loop Filter Capacitor, C1 36 pF

Loop Filter Capacitor, C₂ 564 pF

DAC resolution 9 bit

DAC pulse duration, T_DAC 4T_VCO Required gain matching, ∆ 0.01 Required settling performance 50µs

The validity of the discrete-time model, as well as the stability is verified by substituting the parameters in Table 1 into the left sides of (10) and (17), which results in respective bounds on the calibration loop parameters, gm and Cint of

8 9

4.0 10 , and 1.0 10

m m

int int

g g

C < × C < × . (18)

Clearly the most stringent requirement is satisfying the continuous-time to dis- crete-time model approximation. The appropriate choice of parameters to meet the settling time requirements can be found through simulations. Simulation results are shown in Figure 9 for a C_int of 10pF and a g_m of 0.2mS and 66µS. The simulator is similar to Hspice, and all blocks are implemented with ideal behavioral components.

While both choices of parameters meet the bound given in (18), the settling time re- quirement is achieved when gm is 200µS.

5 10 15

x 10^-5 0

0.05 0.1

5 10 15

x 10^-5 0

0.05 0.1

Time

g_m=0.2mS

g_m=66µS

Gain AdjustGain Adjust

Figure 9: Settling Time for Calibration Technique

The phase noise of the calibrated fractional-N PLL is shown in Figure 10 and compared with that of an ideally matched PLL. As shown, the phase noise resulting from calibration is negligible compared to the case where there is no gain mismatch.

The calibration technique results in a phase noise cancellation improvement of more than 20dB over the uncalibrated case with a 10% gain mismatch.

10⁵ 10⁶ 10⁷

-160 -150 -140 -130 -120 -110 -100 -90 -80

10⁵ 10⁶ 10⁷

-160 -150 -140 -130 -120 -110 -100 -90 -80

Frequency

dBc/Hz dBc/Hz

a) b)

10% Gain Mismatch

Ideal Gain Matching

Frequency

Figure 10: PLL Phase Noise; a) Without Calibration; b) Calibration enabled for ββββ=0.9

10⁵ 10⁶ 10⁷

-160 -150 -140 -130 -120 -110 -100 -90 -80

Frequency

dBc/Hz

Figure 11: Calibration enabled for random mismatches in PLL loop

In practice, component mismatches could result in errors in the calibration technique. With mismatches in the component values of approximately 5%, the phase noise at the output of the PLL remains well behaved as shown in Figure 11, demon- strating the robustness of the calibration technique. It can be shown that component mismatches simply result in a replica of the CP and DAC charges appearing at the in- tegrator input. Since these charges have zero dc content due to the PLL loop, this re- sults in noise on the calibration signal, not misalignment. This demonstrates the vi- ability of this calibration technique for phase-noise canceling delta-sigma fractional-N PLL.

VI.C

An analysis of a calibration technique applied to a phase-noise canceling frac- tional-N PLL has been presented. Conditions have been presented to ensure the stabil- ity of the technique, as well as an approximation for the settling time, which is also used to determine the calibration technique parameters. These results enable the cus- tomization of this calibration technique in response to target PLL specifications.

A

This chapter, in full, is in preparation for submission for publication to the IEEE Transactions on Circuits and Systems I: Regular Papers. The dissertation author is the primary investigator and author of this paper. Ian Galton supervised the research which forms the basis for this paper.

A

A

Consider the continuous-time calibration loop model shown in Figure 8b. The impulse response, g(t), from the input of the filter to w(t) can be derived as

{

}

( ) ^m ( ) 1 ^{t RC}

int DAC

g t g u t e

C I

= ⋅ − − . (19)

The worst-case variation of (19) during a DAC pulse event occurs when the DAC gain is zero. Using (6) and (19), the deviation of w(t) over a duration of T_DAC during the n^th DAC and CP event can be expressed as

{

}

0

( ) ( _DAC) ^{m n} _CP[ ] ^{kT TDAC RC kT RC}

int DAC k

w nT w nT T g Q n e e

C I

− + −

=

− + =

∑

Recalling from (3) that |QCP[n]| ≤ ICPTVCO, the right side of (20) can be bounded by

{

}

{

}

1

1

( 1) /

/ / /

/ 0

/ /

1 1 1

1 1

1

DAC DAC

DAC

n T RC

T RC n kT RC T RC

CP VCO m CP VCO m

T RC

int DAC k int DAC

T RC

CP VCO m

T RC int DAC

I T g I T g e

e e e

C I C I e

I T g e

C I e

− − − − +

= −

−

−

− = − −

−

< −

−

∑

In order to ensure that w(t) does not change over the duration of a DAC pulse, it is necessary to keep (21) small. This leads to

1

1

/ /

1 1

TDAC RC CP VCO m

T RC int DAC

I T g e

C I e

−

−

− < ∆

− (22)

where ∆ is the specified level of gain calibration required for w(t).

A

B

This appendix provides the claims necessary to prove the convergence of the calibration loop. Consider the signal-processing model shown in Figure 8c. With c[n]

given by (5), Claim 1 proves that the charge supplied by the CP and DAC are ergodic, i.e. C0 exists, and Claim 2 provides an intermediate claim to prove the stability of the calibration loop.

Definition: E_quant[n] is an integer-valued sequence representing the quantizer noise from the ∆Σ modulator such that

[ ] [ ] 2

quant

quant N

E n

e n
,

where 2^N is the quantizer step size of the ∆Σ modulator. This definition is provided to ensure congruency with the theorems outlined in [14].

Claim 1: Suppose that the correlation signals given by (5) are generated in conjunc- tion with a 2^nd order ∆Σ modulator designed to satisfy the conditions of Theorem 3 in [14] with a quantizer step size of 2^N. Then C₀ is given by

2 0

2 1

2

N

CP VCO N

C =I ⋅T ⋅ ⁻ − .

Proof: Consider the case where c[n]=sgn(e_quant[n−1])= sgn(E_quant[n−1]). Then from (3),

( )

( )

0 [ ] [ ] [ ] [ 1] sgn [ 1] [ 2]

2

CP VCO

CP CP N quant quant quant

C +C n =Q n c n⋅ = I T ⋅ E n− − E n− ⋅E n− .(23)

From (14), C₀ is defined as the sample average of (23). First consider the sam- ple average of |Equant[n]|. Theorem 1 in [14] proves that Equant[n] asymptotically ap- proaches a uniform random distribution as n→∞ given by

1 1

( ) 2 , ^N 2^N 1 2^N

P uU = ⁻ − ⁻ + ≤ ≤u ⁻ . (24)

And therefore,

lim E _quant[ ] 2^N 2

n E n E u ⁻

→∞  =   = . (25)

For any postive number m, define

[ ] 2^N 2

n quant

X = E n m+ − ⁻ , (26)

and Lemma 3 from [14] shows that E[X_n]→0 is sufficient to prove that the sample av- erage of |Equant[n]| converges in probability to 2^N-2, or in other words

1 2

1 2

lim [ ]

2

n m N

quant N

n k m

e k

n

+ − −

→∞ =

∑

Now consider the second term in (23). Theorem 2 in [14] also proves that the joint pmf of any two samples of the quantizer error converges in distribution to a jointly uniform random variable given by

2 1 1

, ( , ) 2 ^N, 2^N 1 , 2^N

PU V u v = ⁻ − ⁻ + ≤u v≤ ⁻ , (28)

and therefore

( ) ^{[ ]}

lim E sgn _quant[ ] _quant[ 1] E sgn( ) 1

n E n E n u v

→∞  ⋅ − = ⋅ = . (29)

For any positive number m, let

( )

sgn [ ] [ 1] 1

n quant quant

X = E n m E+ n m+ − − , (30)

and Lemma 3 from [14] shows that E[Xn]→0 is sufficient to prove that the sample av- erage of sgn(E_quant[n])⋅Equant[n−1] converges in probability to 1. Therefore due to the linearity of the sample mean operator,

( )

{ }

1 1 2 1

lim [ ] sgn [ ] [ 1]

2

n m N

quant quant quant N

n k m

e k e k e k

n

+ − −

→∞ =

− ⋅ − = −

∑

which proves Claim 1 for c[n]=sgn(equant[n]), and the convergence is irrespective of the initial start index, m. Now consider the second correlation signal given by

( ) ( )

sgn [ ] sgn [ 1]

[ ] [ ]

2

quant quant

e n e n

c n − − s n

= + ,

where s[n] is by definition a zero-mean ergodic sequence. For this correlation signal, (23) can be expressed as

( )

{

( ) ( ) }

0

[ ] 1 [ ] [ 1] sgn [ ] [ 1]

2 2

sgn [ 1] [ ] 2 [ ] [ ] [ 1]

CP VCO

CP N quant quant quant quant

quant quant quant quant

I T

C C n E n E n E n E n

E n E n s n E n E n

+ = ⋅ ⋅ + − − ⋅ −

− − ⋅ + ⋅ ⋅ − −

. (32)

The first 4 terms have already been shown to converge to (31), and since s[n] is a zero-mean ergodic sequence uncorrelated from the quantization error, C0 is given by

2 0

2 1

2

N

CP VCO N

C =I ⋅T ⋅ ⁻ −

Therefore Claim 1 is proven for both correlation signals.

For the following stability claim, consider a system of non-linear difference equations defined by

1 2

[ ] [ ] [ ] [ ]

x n =u n −w n u n⋅ (33)

[ ] [ ] [ ]

w n =x n h n∗ (34)

where u₁[n] and u₂[n] are bounded inputs, and h[n] is a filter with the following char- acteristics

( 1)

[ ] 0 for 0, [1] 0, and [ ] [ 1] ⁿ

h n = n≤ h > h n −h n− =Ke^{− − α} (35)

where K and α are positive constants. Without loss of generality, the system is as- sumed to start at n = 0 such that u₁[n] = u₂[n] = 0 for n < 0.

Claim 2: Suppose that

[1] 2[ ] 1

h ⋅u n < (36)

Then the system of equations defined by (33) and (34) are BIBO stable if for any posi- tive integer m,

1 2

lim 1 ^{N m} [ ] 0

N n m

u n U N

+ −

→∞ =

= >

∑

Proof: First, consider the product given by

(

)

1

1 [1] [ ]

n

l k

h u l

= +

∏

It follows from (36) and the fact that |1 − x| ≤ e^−x that