A Case Study of Failure Analysis and Guardband Determination for a 64M-bit DRAM

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中 華 大 學 碩 士 論 文

題目:

A Case Study of Failure Analysis and Guardband Determination for a 64M-bit DRAM

系所組別:電機工程學系碩士班電子電路組 學號姓名:8 7 0 1 5 3 9 高金德

指導教授:陳竹一 博士

中 華 民 國 八十九 年 七 月

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Abstract

The chips with defects, which escape the test, will cause the quality problem and will hurt the goodwill and decline the revenue. It is important to look for the defect root causes and to derive the prevention strategy. In this paper, a case study of a 64M-DRAM is used to demonstrate the approaches of failure analysis in silicon debug stage and, consequently, the determination of the tests for the production. The consideration of test derivation is both to enhance the yield and to improve the product quality with low-test cost. The root causing, electrical modeling of defects, test selection and guardband determination will be introduced. Finally, a quantitative measure is given to show the value of failure analysis for a high volume DRAM product.

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摘要

某些有瑕疵 (Defects) 的產品, 並沒有經由測試而被篩檢出來, 這些瑕疵品不但 影響產品的品質, 對公司的商譽及收益亦有相當程度的衝擊. 因此找出瑕疵產生 的根本原因 (Root Cause) 並且想出預防的對策, 是相當重要的.

在本文中, 我們以一個六千四百萬位元的動態隨機存取記憶體 (64M-bit DRAM) 產品為實例, 闡示其故障分析 (Failure Analysis) 的手法, 並藉由這些分析的資 料來決定產品量產時的測試規格 (Test Spec.) 及樣式 (Test Pattern). 開發這些測 試的方法及條件乃是為了能更進一步的提升產品的良率及品質. 並且降低後段 測試的成本.

我 們 將 會 在 論 文 中 介 紹 此 瑕 疵 發 生 的 根 本 原 因 , 和 其 等 效 上 的 電 性 模 型 (Electrical Model), 以及如何選擇及決定測試的規格及條件. 在論文最後, 我們 將以一些量化的分析資料來顯示故障分析對量產 DRAM 產品的重要性及價值.

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Acknowledgements

I would like to express my sincere gratitude to my adviser Dr. J. E. Chen for his constant encouragement, guidance and helpful suggestions throughout this study.

Specially, I also would like to thank my director T. S. Feng, deputy director John Liu, and managers Henry Chen, Steve Yang, Eme Chou very much for providing the best opportunity.

After this work, I wish to pay the greatest thanks to my leader Sam Wu for his help, instructions, and discussions of process and theory.

Furthermore, special thanks are my colleagues T. C. Lin, Jacky Huang, Sinclair Lu and Joseph Wen for their help and discussions of this thesis. I also thank all of our group’s classmates.

Finally, I wish to give my thanks to my family for their spiritual supports and encouragement.

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Contents

Abstract

Acknowledgement I. Introduction

Cost reduction, quality and yield improvement II. Failure description and defect analysis II_1 Phenomenal observation

II_2 Finding the root cause II_3 Device model

II_4 Circuit level model

III. Actions for defect and electrical analysis Test selection: changing to chip probing from final test Test considerations and schemes

III_1 Analysis from the storage charge in cell capacitor

III_2 Analysis from the storage to bit-line capacitance ratios and signal levels III_3 Analysis from the total charge that is written into cell capacitor

III_4 Analysis from the effect of disturbance and leakage III_5 Summary of the analyses and actions

IV. Experimental Result V. Conclusions

References

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I. Introduction

Cost reduction, quality and yield improvement

The more integration of a system is as the wafer and the chip area are increasing in size and the device dimension of manufacturing process is scaling down. Quality, at that time, is the never-ending competitive force for a product or a company to enter the global market and stay in it [1]. How to quantify the quality factors is a challenge and it is emergent.

In the meantime, due to the increase in circuit complexity, interconnection requirement and large number of failure modes, the large area VLSI chips are prone to defects during manufacture. In addition to improve the testability of a design [2] and to improve the manufacturing yield, testing plays a major role in modern VLSI development and semiconductor industry. The following economic issues should be taken into consideration during the development of the testing process: testing quality [3,4,5,6], testing cost and yield loss caused by the killing (Type I) errors, as which a good die is failed by test, and the missing (Type II) errors, as which a bad die escapes the test [7,8,9].

The test conditions are worse in high temperature environment for most CP (Chip Probing) test items — data retention time, leakage test,ISB… . for examples. Thus most DRAM products are tested in high temperature in CP test. However, some process- induced defects degrade the chip performances in the cold temperature applications only. These kind of defects will escape from a high temperature wafer sort test and then suffer FT yield, so it is necessary to add an extra cold temperature CP test in order to improve FT yield. This will take an extra cold temperature test cost for us to screen out these kind of defects.

Cost reduction is necessary for a high volume DRAM, because the price of DRAM decreased as time goes by. This pushes us to create a better test me thodology to replace the costly cold temperature test in CP, and still maintain the good shipping quality and yield.

A 64M DRAM product is used to validate the test methodology and the yield of this product is improved up to 10% in production line.

It is important to look for the defect root causes and to derive the prevention strategy.

The consideration of test derivation is both to enhance the yield and to improve the product quality with low-test cost. In the following sections, the root causing of the defect for a silicon crack is firstly introduced. Then an electrical model of the defects is given to consider the test selection. Hundreds of defective components are experimented to determine the guardbands and the special test patterns. We will gene rate an optimal testing methodology that can sieve out weak bits introduced from

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the process defects. The tests with cold temperature are omitted and replaced by those with stretching the parameters. The failed bits on a DRAM chip can be repaired by the spare parts. Thus, the FT (final test, package test) yield and product reliability can be improved. Finally, a quantitative measure is given to show the value of failure analysis for a high volume DRAM product.

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II. Failure description and defect analysis

II_1 Phenomenal observation

These failure units passed a wafer sort test, a packaged unit test in high temperature

(85ΟC), but failed at a packaged unit test in cold temperature (-10ΟC). Failure mode of these failure units is single bit failed 1 and it is sensitive to temperature. These rejects contribute 10% yield loss at a cold temperature packaged test, so this failure mode lose profit very much.

II_2 Finding the root cause

Root cause analysis found the defect to be a “Silicon Crack.” This is a crack along the spacer to silicon substrate. Figure 1 shows a partial cross section of the crack in question.

Figure 1. TEM photo of this defect, notice that the crack was from poly spacer to silicon substrate.

II_3 Device model

Using the results of the FA, TEM, and construction analysis, the defect can be modeled and understood. Tunneling effect cause this kind of defect to be sensitive to temperature [10,11]. Figure 2(a) and figure 2(b) show the wave function of a particle with energy E less than a barrier of height V are incident from the left. 0

crack position

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(a)

(b)

Figure 2. (a) The wave function of a particle of energy E < V0 encountering a barrier potential. (b) Tunneling of a particle in one dimension.

The wavelength λ0 is the same on both sides of the barrier, but the amplitude beyond the barrier is much less than the original amplitude. The tunneling probability T can be expressed approximately as

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T = ( A

C ) ≅ EXP [ -2d 2m*(qV0E)/h2 ]

Note that as the barrier height increases or the barrier width increases the tunneling probability decreases. The width of “silicon crack” is very small, we can not detect this kind of defect by SEM, it can only be observed by TEM, that is, the barrier width (d) is ver small and the tunneling probability is getting higher. In high temperature, the conduction carriers have more energy such that the energy difference (qV - E) 0 becomes smaller, and this also increases the tunneling probability. That is the mechanism why this kind of defects can pass a wafer sort test, a packaged unit test in high temperature (85ΟC), but fail at a packaged unit test in cold temperature (-10ΟC).

II_4 Circuit level model

In this case, the crack adds resistance in series with the channel of MOS transistor, thus inducing an R-C delay. Electrically this can be modeled as an R inserted into the channel of MOS transistor. Figure 3 shows the schematic of the circuit with the defect model included.

Figure 3. Electrical model of a silicon-crack defect

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III. Actions for defect and electrical analysis

Test selection: changing to chip probing from final test

This failure mode can be screened out in a high speed sort test, because the silicon crack increase the equivalent resistance in NMOS channel, and it also induce an extra R-C delay. However, high frequency test is not applicable to wafer sort test. We had to find another scheme to solve this issue in wafer sort test with a loose function test.

Since the equivalent resistor reduce the conduction current and it also decrease the charge stored in DRAM capacitor (I*R drop), we try to worsen this situation by reducing the quantity of storage charge, and then make these weak bits fail in wafer sort test. Spare part circuits will replace these weak bits after laser repaired, hence the FT yield and product quality will be improved without extra cost.

Test considerations and schemes

New test constraints are selected and analyzed in the wafer sort test with a loose functional tester. In order to achieve the approaches, several test schemes are adopted on this issue and described them as follows:

III_1 Analysis from the storage charge in cell capacitor

After write cycle has completed, the charge that is written into DRAM cell capacitor is

Q =CSV where

Q total charge write into cell capacitor C cell storage capacitance S

V voltage difference across DRAM cell capacitor.

) (VCC VREF.

V = −

∆ when signal stored in cell capacitor is ‘1’, where V is the CC device applying voltage from external power supply. Since product design and process recipes have no change, the cell capacitanceC is fixed. That is, we can only S decrease the ∆V to reduce the storage charge Q. Because ∆V =(VCCVREF), we may try to decrease VCC and increase VREF to reduce the charge stored in capacitors.

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III_2 Analysis from the storage to bit-line capacitance ratios and signal levels The storage capacitance to bit-line capacitance ratio is one of the important characteristics of the one transistor DRAM since sufficient charge must be stored on the capacitor to provide a readable signal on the bit lines to the sense amplifier.

The parasitic bit- line capacitance (C ), due to the large number of cells on a single B bit- line, is typically larger than the capacitance of the storage cell (C ). When the cell S is selected and the signal stored in the cell capacitor (VNODE) is read out on to the bit- line, it is reduced by the ratio of the storage capacitance to bit-line parasitic capacitance [12]. The differential signal on the DRAM sense amplifier is

(

NODE REF

)

S B

S

BL V V

C C

V C  −

 

= +

where

VBL potential difference between bit-line ( BL ) and bit-line bar ( BL ) C cell storage capacitance S

C bit-line equivalent capacitance B VNODE cell capacitor storage node potential VREF cell capacitor plate potential

Figure 4 shows the equivalent circuit of one access transistor plus one storage capacitor DRAM cell.

Figure 4. The equivalent circuits of one access transistor plus one storage capacitor DRAM cell.

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VNODE=V if the signal stored in the cell capacitor is ‘1’, and the differential signal CC of DRAM sense amplifier becomes

(

CC REF

)

B S

S

BL V V

C C

V C  −



= +

∆ .

Again, since product designs and process recipes have no change, C and S C are B fixed. We may decrease V and increase CC VREF to reduce ∆VBL during read cycle, and then make these weak bits fail.

Figure 5(a) shows the 2D Shmoo of V vs. CC VREF, figure 5(b) and figure 5(c) show the plots of “VCC vs. Failure Bit Count” and “VREF vs. Failure Bit Count”, respectively. These 3 plots show a new test conditions of lower V and higher CC VREF may help us to distinguish bad units from good units. Based on these three plots, we determine to set the new test condition:

V = 2.4V and CC VREF= 1.3V

Although healthy unit can pass a tighter spec V = 2.3V and CC VREF= 1.4V, we set a looser test spec V = 2.4V and CC VREF= 1.3V for preserving test spec guard-band.

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(a)

(b)

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(c) Figure 5. (a) 2D Shmoo of V vs. CC VREF (b) The plot of “VCC vs. Failure Bit Count” and (c) the plot of “VREF vs. Failure Bit Count”. A lower V and higher CC VREF may help us to distinguish bad units from good units.

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III_3 Analysis from the total charge to be written into cell capacitor During write cycle, the total charge that is written into DRAM cell capacitor is Q = i t

where

Q the total charge been written into cell capacitor

i conduction current from bit line to DRAM cell capacitor t∆ time for charge writing into DRAM cell capacitor

For simply modeling, we assume that i IDSAT, where IDSAT is the saturation current of NMOS and IDSAT is

(

GS TH

) (

DS

)

ox n

DSAT V V V

L W

I = µC − 1+λ

2

2

where

µ electron mobility n C oxide capacitance ox W channel width L channel length

V voltage difference between gate and source GS V threshold voltage TH

The parameters µ ,n C , W, L,ox V are fixed since the process recipes are unchanged, TH and if we ignore the channel length modulation effect (1+λVDS), we may try to reduce V for decreasing GS IDSAT.

Figure 6(a), (b) and (c) show the NMOS structural perspective layout, top view and circuit symbol, respectively. We can easily understand the meanings of those parameters above by figure 6(a), (b) and (c).

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Generally speaking, V is at least a GS V higher than TH V for avoiding the “poor CC 1” issue of NMOS. That is, we can reduce V to decrease CC IDSAT again.

Although V is fixed if process recipes remain unchanged. However, we can take TH advantage of “Body Effect” to increase V [13,14,15]. That is, we can utilize the TH body effect to decrease IDSAT. The incremental threshold voltage is

[

SB si si

]

a

TH V

C N

V qKsε φ φ

− +

=

Ο

2 Ο

where

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K dielectric constant of oxide Ο

ε free-space permittivity Ο

Based on this equation, we should increase V to raise SB V . That means we can TH apply a more negative reverse-bias voltage to P-type substrate. We generally call the applying reverse-bias voltage V . Also, more negative BB V increase P-N junction BB leakage current. This will reduce the storage charge in DRAM cell capacitor, too.

t is the time for charge being written into DRAM cell capacitor, we generally call this timing parameter "tW R" or "tDPL". Figure 7 illustrates the physical meaning of tW R [16]. It is the time difference between the last data being written into capacitor to the precharge command. The NMOS of DRAM cell will be turned off when the precharge command is asserted, and charge can not be written into the DRAM cell capacitor.

Figure 7. Illustration of tW R which is the time for charge been written into DRAM

cell capacitor.

According to the mention above, we should apply a lower V , a more negative CC V BB and tighten tW R to reduce the storage charge of DRAM cell capacitor. Figure 8(a) shows the 2D Shmoo of “V vs. BB V ” and “CC V vs. BB VREF”, figure 8(b) and figure 8(c) show the plots of “V vs. Failure Bit Count” and “BB tW R vs. Failure Bit Count”

respectively. These 3 figures prove that weak bits can be sieve out by tightening tW R and applying a more negative V . Based on these three plots, we determine to set a BB new test condition.

V = -2.8V and BB tW R = 11 ns

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Because we still need to preserve test spec guard-band and consider production tester limit, we set a much looser test spec (V = -2.8V and BB tW R = 11 ns) than the analysis result of these two plots. Even though healthy unit can pass a tighter spec (VBB ≤ -3V and tW R = 5 ns).

(a)

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(b)

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(c)

Figure 8. (a) 2D Shmoo of “V vs. BB V ” and “CC V vs. BB VREF” (b) The plot of “V BB vs. Failure Bit Count” and (c) the plot of “tW R vs. Failure Bit Count”. Tightening tW R and applying a more negative V can help us to screen out those weak bits in wafer BB sort test.

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III_4 Analysis from the effect of disturbance and leakage

There exist many leakage paths and coupling capacitance between each cell. Figure 9 shows the leakage paths in stack capacitor cell [17].

Figure 9. The leakage paths in stack capacitor cell. They can be generally separated into 4 groups.

These leakage paths can be generally separated into 4 groups. They are (1) Junction leakage:

n, p concentration crystal defects (□)

dislocation at isolation oxide edge (■) surface states (+)

(2) Parasitic leakage path:

p, n concentration (3) Subthreshold leakage

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(4) Leakage through dielectric

We treat the equivalent coupling capacitor as an ideal parallel-plate capacitor for simplifying this coupling capacitance model. The capacitance of parallel-pla te capacitor is

d C = εA

and the leakage current (displacement current) between each cell can be expressed as ω

ε Vd

iDA = CV ω where

ω angular frequency ε permittivity

d plate separation of parallel-plate capacitor

Device size continues scaling down since process technology keeps up improving.

This makes the MOS channel length and the space between each cell become smaller.

Therefore, most of the leakage currents shown in figure 9 become larger. The operation frequency keeps up improving also make the leakage current larger. We try to worsen these leakage sources to catch those weak bits but do not affect the normal operation for healthy bits. That is, we need to create a test pattern to increase the disturbance of coupling effect and other leakage current in a proper range [18].

At first, we create a “physical checkerboard” pattern. It is simply shown as below.

0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 => 0 0 0 0 0 => 0 1 0 1 0 => 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 Afterward, to keep on writing ‘0’ or do “RAS only refresh” to those bits which surround the bit stored ‘1’. Combining the effect of more negative V (it increase BB junction leakage), total leakage current will be larger, hence the weak bits are easier to be captured by applying such test patterns. Figure 10(a), 10(b) and 10(c) show the analysis result. Based on these figures, we prove that the modified test patterns can really screen out more weak bits. Figure 11 is a benchmark of healthy unit and weak unit. This figure shows that the modified test pattern does not affect the normal operation for healthy unit.

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(a)

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(b)

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(c)

Figure 10. (a), (b) and (c) The analysis results of original and modified test patterns.

The modified test patterns can capture more weak bits.

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Figure 11. Benchmark of healthy unit and weak unit. The modified test patterns do not affect the normal operation of healthy unit.

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III_5 Summary of the analyses and actions

Based on the above analysis results from the engineering run, the optimal test condition is given to production run.

V = 2.4V CC

VREF= 1.3V V = -2.8V BB

tW R = 11ns

Pattern: Checkerboard plus Row disturbing

The new test condition improves FT yield very much. It improves 9.5% FT yield with almost no suffering on CP yield. It also saves the extra cold temperature test cost on CP. We will describe the test result with applying the new test condition in the next chapter in detail.

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IV. Experimental Result

After many times of test condition modification and yield benchmark, we obtained the best test patterns to screen out this failure mode. To apply these test patterns, we got an inspired result. We improved the FT yield about 10% with almost no suffering on CP yield. The experimental result is shown as below:

Test program for wafer sort test

The first version (original)

The second version (modified)

Wafer sort test (at 85ΟC) 65.6% 65.3%

Yield

Package test (at -10ΟC) 90.3% 99.8%

Test Program

The first version The second version Difference

Consumption of redundancy circuit

Row Column Row Column Row Column

Unit 1 5 14 5 16 0 2

Unit 2 7 38 9 39 2 1

Unit 3 9 58 9 58 0 0

Unit 4 4 25 4 25 0 0

Unit 5 6 41 6 41 0 0

Unit 6 2 23 2 29 0 6

Unit 7 1 5 1 6 0 1

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Program

The first version The second version

Diff.

BIN COUNT YIELD

%

COUNT YIELD

%

UNITS TESTED 392 100% 392 100%

UNITS PASSED 257 65.6% 256 65.3% -1 ea

DB 1 NATURAL GOOD 1 0.3% 0 0.0% -1 ea

DB 5 OPEN/SHORT 24 6.1% 24 6.1%

DB 33 Icc Short Test 9 2.3% 9 2.3%

DB 6 I/P LEAKAGE HIGH 3 0.8% 3 0.8%

DB 7 I/P LEAKAGE LOW 0 0.0% 0 0.0%

DB 8 O/P LEAKAGE HIGH 8 2.0% 8 2.0%

DB 9 O/P LEAKAGE LOW 0 0.0% 0 0.0%

DB 10 VBB MEASUREMENT 0 0.0% 0 0.0%

DB 11 CMOS STANDBY CURRENT 6 1.5% 6 1.5%

DB 13 March-X (B4C3) DS RowBar 312 79.6% 312 79.6%

DB 14 March-X (B1C3) NDS #5AA5 Tightened tWR Veq High

317 80.9% 333 84.9% +16 ea DB 15 March-Y (B1C2) DS RowBar 339 86.5% 339 86.5%

DB 16 Solid One Refresh 337 86.0% 338 86.2%

DB 17 4-Row Disturb Hi Deep Vbb 341 87.0% 341 87.0%

DB 18 4-Row Disturb Hi Shallow Vbb 341 87.0% 341 87.0%

DB 19 4-Row Disturb Lo Shallow Vbb 340 86.7% 340 86.7%

DB 20 4-Row Disturb Lo Deep Vbb 340 86.7% 340 86.7%

DB 21 Solid Zero Refresh 274 69.9% 275 70.2%

DB 22 March-Y (B1C2) DS #F0F0F0F0 329 83.9% 329 83.9%

DB 23 March-Y (B1C2) DS #F0F0F0F0 Lower

331 84.4% 331 84.4%

DB 24 LRAS SBR NDS NCKB Hi 339 86.5% 339 86.5%

DB 25 LRAS SBR DS RowBar Hi 340 86.7% 340 86.7%

DB 26 LRAS SBR NDS NCKB Lo 338 86.2% 337 86.0%

DB 27 LRAS SBR DS RowBar Lo 335 85.5% 335 85.5%

DB 28 LRAS BR NDS NCKB Hi 328 83.7% 328 83.7%

DB 29 LRAS BR NDS NCKB Lo 330 84.2% 330 84.2%

DB 51 Accumulated Tests Pass 1 0.3% 0 0.0%

DB 52 Accumulated Tests Rep. 256 65.3% 256 65.3%

DB 54 Accumulated Tests Unrep. 85 21.7% 86 21.9%

DB 81 March-X (B1C3) NDS #5AA5 Veq Higher Pass

0 0.0% 0 0.0%

DB 82 March-X (B1C3) NDS #5AA5 Veq Higher Rep.

257 65.6% 256 65.3%

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The contributions of this new test pattern are

1. Improving 10% FT yield without suffering on CP yield. The profit we gain is shown as follow:

CP Yield

Gross Dice (per wafer)

Wafer Quantity (per month)

Yield Loss (by this

failure mode)

64M DRAM Price

(per unit)

Profit Gain (per month)

85% 400 10000 10% US$ 5 US$ 1.7

million

2. It does not need to add any extra test item on CP test. That is, the CP test time is the same as before. Hence we will not increase any extra test cost.

3. Saving the extra cold temperature test cost on CP. The test cost we save is shown as follow:

Wafer Quantity (per month)

Test Time (per wafer)

Charge for Tester (per hour)

Cost Saving (per month) 10000 Pieces 4 Hours US$ 100 US$ 4 million

4. Reducing the DPM (Defects Per Million) levels in shipping units.

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V. Conclusions

A product with good yield and quality usually result s largely from an excellent design and process, but we still need the aid of testing for further yield improvement sometimes, especially in the time before we find the root causes and solutions of new failure modes. Because the process and design keep up improving, the product manufacture technology has become more complex. This makes some subtle defects more difficult to be caught and it also increases the DPM for shipping units. To create and apply the optimal test methodology will help us to save cost and improve reliability very much. In the future, how to find the best test conditions to screen out the defects and avoid the “overkill” (don’t damage the healthy parts) will play the important role in the profit generation. This paper has presented a successful experience of failure analysis and guardband determination for a 64M DRAM.

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