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# MMux ALU

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## Arithmetic Logic Unit (ALU)

### Introduction to ComputerpYung-Yu Chuang

with slides by Sedgewick & Wayne (introcs.cs.princeton.edu), Nisan & Schocken (www.nand2tetris.org) and Harris & Harris (DDCA)

(2)

### Let's Make an Adder Circuit Goal. x + y = z for 4-bit integers.

We build 4-bit adder: 9 inputs, 4 outputs.p p

Same idea scales to 128-bit adder.

Key computer component.

1 1

1 0

8 4

2 7

7 5

3 9

+

1 1

1 0

6 0

6 6

(3)

Assuming a 4-bit system:

0 0 0 1 1 1 1 1

1 0 0 1

0 1 0 1 + 1 0 1 1 0 1 1 1 +

no overflow overflow

0 1 1 1 0 1 0 0 1 0

no overflow overflow

Algorithm: exactly the same as in decimal addition

Overflow (MSB carry) has to be dealt with.

(4)

Representing negative numbers (4-bit system)

The codes of all positive numbers begin with a “0”

0 0000

1 0001 1111 -1

The codes of all negative numbers begin with a “1“

b

2 0010 1110 -2

3 0011 1101 -3

4 0100 1100 -4 To convert a number:

leave all trailing 0’s and first 1 intact, and flip all the remaining bits

4 0100 1100 -4

5 0101 1011 -5

6 0110 1010 -6

7 0111 1001 -7

1000 -8

Example: 2 - 5 = 2 + (-5) =p 0 0 1 0 + 1 0 1 1

1 1 0 1 = 3

1 1 0 1 = -3

(5)

1 0

0 0

0 1

1 0

1 0

0 0

1 1

0 1

+

0 0

1 1

x1 x2

x33 2 1 x00 y1

y2

y3 y0

+

z1 z2

z3 z0

(6)

x1 x2

x3 x0

cin cout

### Step 2. [first attempt]

Build truth table.

y1 y2

y3 y0

+

z1 z2

z3 z0

4-Bit Adder Truth Table y2

y3 0 0 x0 x1

0 0 x2 x3

0 0

y0 y1

0 0

z2 z3

0 0

z0 z1

0 0 c0

0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 1 0 1 0 0 1 1

0 0 0 0 0 0 0 0

0 1 0 1 0 0 1

1 28+1 = 512 rows!

0 0 0 0

1 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1

0 . 1 0 . 1

1 . 1 0 . 1

0 . 1 0 . 1

2 512 rows!

0 . 1

256+1

56

(7)

x y

c s

x y s c

(8)

x y s

x y

Cout Cin

C t

Cin Cout

s

(9)

(10)

x1 x2

x3 x0

c1 c2

c3 c0 = 0 cout

### Step 2. [do one bit at a time]

Build truth table for carry bit.

y1 y2

y3 y0

+

z1 z2

z3 z0

Build truth table for summand bit.

Carry Bit Summand Bit

Carry Bit

ci ci+1 yi

xi

0 0

0 0

Summand Bit ci zi yi

xi

0 0

0 0

0 0 1 1

0 1 0

1 1 0

0 0

1 1 0 1

0 1 0

1 1 0

0 0 0

1 1 0

1 0 0

0 1 1

1 1

1 0 0 0

1 0 0

0 1 1

1 1 1

1 1

1 1 1 1 1

(11)

### Step 3.

Derive (simplified) Boolean expression.

Carry Bit Summand Bit

MAJ 0

ODD 0 ci ci+1

yi xi

0 0

0 0

ci zi yi

xi

0 0

0 0

Carry Bit Summand Bit

0 0 1

1 1 0 0

0 1 1

0 1 0

1 1 0

0 0

1 1 0 1

0 1 0

1 1 0

0 0 0

1 1

1 0 0 0

1 1 0

1 0 0

0 1 1

1 1

1 0 0 0

1 0 0

0 1 1

1 1

1 1

1 1

1

1 1 1 1 1

(12)

### Step 4.

Transform Boolean expression into circuit.

Chain together 1-bit adders.

(13)

(14)

(15)

(16)

### Subtractor Subtractor circuit: z = x – y.

One approach: design like adder circuitpp g

(17)

### Subtractor Subtractor circuit: z = x – y.

One approach: design like adder circuitpp g

Better idea: reuse adder circuit

2’s complement: to negate an integer, flip bits, then add 1

(18)

### Subtractor Subtractor circuit: z = x – y.

One approach: design like adder circuitpp g

Better idea: reuse adder circuit

2’s complement: to negate an integer, flip bits, then add 1

(19)

### Shifter

s0 s1 s2 s3

Only one of them will be on at a time.

x0

SHIFT x1

SHIFT x2

x3

4 bit Shift

z0 z1 z2 z3

4-bit Shifter

(20)

0

1

2

3

0

1

2

3

0

1

2

3

(21)

0

1

2

3

0

1

2

3

0

0

1

2

3

1

0

1

2

2

0

1

3

0

(22)

(23)

### N-bit Decoder N-bit decoder

N address inputs, 2p N data outputsp

Addresses output bit is 1;

all others are 0

(24)

### N-bit Decoder N-bit decoder

N address inputs, 2p N data outputsp

Addresses output bit is 1;

all others are 0

(25)

0

1

(26)

### Arithmetic logic unit (ALU). Computes all operations in parallel. p p

Xor.

A d

And.

Shift left or right.

(27)

### 1 Hot OR 1 hot OR.

All devices compute their answer;

we pick one. p

Exactly one select line is on.

Implies exactly one output line is xor

Implies exactly one output line is relevant.

shifter

(28)

xor decoder

shift

(29)

### Bus 16-bit bus

Bundle of 16 wiresu f w

Memory transfer Register transfer

### 8-bit bus 8-bit bus

Bundle of 8 wires

### 4 bit b 4-bit bus

Bundle of 4 wires

(30)

### Bitwise AND, XOR, NOT Bitwise logical operations

Inputs x and y: n bits eachp y

Output z: n bits

Apply logical operation to each corresponding pair of bits

of bits

(31)

### TOY ALU TOY ALU

Big combinational logic g g

16-bit bus

Add, subtract, and, xor, shift left, shift right, copy input 2

copy input 2

(32)

### Device Interface Using Buses

16 bit words for TOY memory

### Input bus. Wires on top.

16-bit words for TOY memory

(33)

### ALU Arithmetic logic unit.

Xor.

And.

Shift left or right

Shift left or right.

### Arithmetic logic unit.

Computes all operations in parallel.

Uses 1-hot OR to pick each bit answer

How to convert opcode to 1-hot OR signal?

(34)
(35)
(36)

### Hack ALU

out

x

16

16-bit 16 adder out

y

16

zx nx zy ny f no out(x, y, control bits) =

x

x+y, x-y, y–x, 0, 1, -1,

16 bits ALU

16 bits

x

y 16 bits

out

x, y, -x, -y, x!, y!,

x+1 y+1 x 1 y 1

zr ng

x+1, y+1, x-1, y-1, x&y, x|y

(37)

### Hack ALU

(38)

The ALU in the CPU context (a sneak preview of the Hack platform)

c1,c2,,c6

D

a D register

ALU

M

out

A/M

A register A

Mux A/M

RAM M (selected (selected register)

(39)

Perspective

Combinational logic

Our adder design is very basic: no parallelism

Our adder design is very basic: no parallelism

It pays to optimize adders

Our ALU is also very basic: no multiplication, no division

Wh is th s t f m d n d m th p ti ns?

Where is the seat of more advanced math operations?

a typical hardware/software tradeoff.

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