MMux ALU

(1)

Arithmetic Logic Unit (ALU)

Introduction to Computer p Yung-Yu Chuang

with slides by Sedgewick & Wayne (introcs.cs.princeton.edu), Nisan & Schocken (www.nand2tetris.org) and Harris & Harris (DDCA)

(2)

Let's Make an Adder Circuit Goal. x + y = z for 4-bit integers.

 We build 4-bit adder: 9 inputs, 4 outputs.p p

 Same idea scales to 128-bit adder.

 Key computer component.

1 1

1 0

8 4

2 7

7 5

3 9

+

1 1

1 0

6 0

6 6

(3)

Binary addition

Assuming a 4-bit system:

0 0 0 1 1 1 1 1

1 0 0 1

0 1 0 1 + 1 0 1 1 0 1 1 1 +

no overflow overflow

0 1 1 1 0 1 0 0 1 0

no overflow overflow

 Algorithm: exactly the same as in decimal addition

 Overflow (MSB carry) has to be dealt with.

(4)

Representing negative numbers (4-bit system)

 The codes of all positive numbers begin with a “0”

0 0000

1 0001 1111 -1

 The codes of all negative numbers begin with a “1“

b

2 0010 1110 -2

3 0011 1101 -3

4 0100 1100 -4  To convert a number:

leave all trailing 0’s and first 1 intact, and flip all the remaining bits

4 0100 1100 -4

5 0101 1011 -5

6 0110 1010 -6

7 0111 1001 -7

1000 -8

Example: 2 - 5 = 2 + (-5) =p 0 0 1 0 + 1 0 1 1

1 1 0 1 = 3

1 1 0 1 = -3

(5)

Let's Make an Adder Circuit

Step 1. Represent input and output in binary.

1 0

0 0

0 1

1 0

0 0

1 1

0 1

+

0 0

1 1

x₁ x₂

x₃₃ ₂ ₁ x₀₀ y₁

y₂

y₃ y₀

+

z₁ z₂

z₃ z₀

(6)

Let's Make an Adder Circuit Goal. x + y = z for 4-bit integers.

x₁ x₂

x₃ x₀

c_in c_out

Step 2. [first attempt]

 Build truth table.

y₁ y₂

y₃ y₀

+

z₁ z₂

z₃ z₀

4-Bit Adder Truth Table y₂

y₃ 0 0 x₀ x₁

0 0 x₂ x₃

0 0

y₀ y₁

0 0

z₂ z₃

0 0

z₀ z₁

0 0 c₀

0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 1 0 1 0 0 1 1

0 0 0 0 0 0 0 0

0 1 0 1 0 0 1

1 2⁸⁺¹ = 512 rows!

0 0 0 0

1 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1

0 . 1 0 . 1

1 . 1 0 . 1

0 . 1 0 . 1

2 512 rows!

0 . 1

Q. Why is this a bad idea?

A 128-bit adder: 2

²⁵⁶⁺¹

rows >> # electrons

A. 128-bit adder: 2

⁵⁶

rows >> # electrons

in universe!

(7)

1-bit half adder

We add numbers one bit at a time.

ADD

x y

c s

x y s c

(8)

1-bit full adder

x y s

x y

C_out C_in

ADD

C _t

C_in C_out

s

(9)

8-bit adder

(10)

Let's Make an Adder Circuit Goal. x + y = z for 4-bit integers.

x₁ x₂

x₃ x₀

c₁ c₂

c₃ c₀= 0 c_out

Step 2. [do one bit at a time]

 Build truth table for carry bit.

y₁ y₂

y₃ y₀

+

z₁ z₂

z₃ z₀

 Build truth table for summand bit.

Carry Bit Summand Bit

Carry Bit

c_i c_i+1 y_i

x_i

0 0

Summand Bit c_i z_i y_i

x_i

0 0

0 0 1 1

0 1 0

1 1 0

0 0

1 1 0 1

0 1 0

1 1 0

0 0 0

1 1 0

1 0 0

0 1 1

1 1

1 0 0 0

1 0 0

0 1 1

1 1 1

1 1

1 1 1 1 1

(11)

Let's Make an Adder Circuit Goal. x + y = z for 4-bit integers.

Step 3.

 Derive (simplified) Boolean expression.

MAJ 0

ODD 0 c_i c_i+1

y_i x_i

0 0

c_i z_i y_i

x_i

0 0

0 0 1

1 1 0 0

0 1 1

0 1 0

1 1 0

0 0

1 1 0 1

0 1 0

1 1 0

0 0 0

1 1

1 0 0 0

1 1 0

1 0 0

0 1 1

1 1

1 0 0 0

1 0 0

0 1 1

1 1

1

1 1 1 1 1

(12)

Let's Make an Adder Circuit Goal. x + y = z for 4-bit integers.

Step 4.

 Transform Boolean expression into circuit.

 Chain together 1-bit adders.

(13)

Adder: Interface

(14)

Adder: Component Level View

(15)

Adder: Switch Level View

(16)

Subtractor Subtractor circuit: z = x – y.

 One approach: design like adder circuitpp g

(17)

Subtractor Subtractor circuit: z = x – y.

 Better idea: reuse adder circuit

– 2’s complement: to negate an integer, flip bits, then add 1

(18)

Subtractor Subtractor circuit: z = x – y.

 Better idea: reuse adder circuit

– 2’s complement: to negate an integer, flip bits, then add 1

(19)

Shifter

s₀ s₁ s₂ s₃

Only one of them will be on at a time.

x₀

SHIFT x₁

SHIFT x₂

x₃

4 bit Shift

z₀ z₁ z₂ z₃

4-bit Shifter

(20)

Shifter

z

₂

x

₃

s 0 x x x

s

₁

0 x

₀

x

₁

x

₂

s

₂

0 0 x

₀

x

₁

0 0 0

s

₃

0 0 0 x

₀

z0 = s0‧x0 + s1‧0 + s2‧0 + s3‧0

z1 = s0‧x1 + s1‧x0 + s2‧0 + s3‧0

z2 = s0‧x2 + s1‧x1 + s2‧x0 + s3‧0

z3 = s0‧x3 + s1‧x2 + s2‧x1 + s3‧x0

(22)

Shifter

z0 = s0‧x0 + s1‧0 + s2‧0 + s3‧0

z1 = s0‧x1 + s1‧x0 + s2‧0 + s3‧0

z2 = s0‧x2 + s1‧x1 + s2‧x0 + s3‧0

z3 = s0‧x3 + s1‧x2 + s2‧x1 + s3‧x0

(23)

N-bit Decoder N-bit decoder

 N address inputs, 2p ^N data outputsp

 Addresses output bit is 1;

all others are 0

(24)

N-bit Decoder N-bit decoder

 N address inputs, 2p ^N data outputsp

 Addresses output bit is 1;

all others are 0

(25)

2-Bit Decoder Controlling 4-Bit Shifter

Ex. Put in a binary amount to shift. r

₀

r

₁

(26)

Arithmetic Logic Unit

Arithmetic logic unit (ALU). Computes all operations in parallel. p p

 Add and subtract.

 Xor.

A d

 And.

 Shift left or right.

Q. How to select desired answer?

Q

(27)

1 Hot OR 1 hot OR.

 All devices compute their answer;

adder

we pick one. p

 Exactly one select line is on.

Implies exactly one output line is ^xor

 Implies exactly one output line is relevant.

x．1 = x

0 0

^shifter

x．0 = 0

0 x + 0 = x

(28)

1 Hot OR

1

adder

x．1 = x x．0 = 0 x + 0 = x

xor decoder

shift

(29)

Bus 16-bit bus

 Bundle of 16 wiresu f w

 Memory transfer Register transfer

8-bit bus 8-bit bus

 Bundle of 8 wires

 TOY memory addressy

4 bit b 4-bit bus

 Bundle of 4 wires

TOY register address

 TOY register address

(30)

Bitwise AND, XOR, NOT Bitwise logical operations

 Inputs x and y: n bits eachp y

 Output z: n bits

 Apply logical operation to each corresponding pair of bits

of bits

(31)

TOY ALU TOY ALU

 Big combinational logic g g

 16-bit bus

 Add, subtract, and, xor, shift left, shift right, copy input 2

copy input 2

(32)

Device Interface Using Buses

16 bit words for TOY memory

Device. Processes a word at a time.

Input bus. Wires on top.

16-bit words for TOY memory

p p

Output bus. Wires on bottom.

Control. Individual wires on side.

M

out

A/M

A register A

Mux A/M

RAM M (selected (selected register)

(39)

Perspective

 Combinational logic

 Our adder design is very basic: no parallelism

 It pays to optimize adders

 Our ALU is also very basic: no multiplication, no division

 Wh is th s t f m d n d m th p ti ns?

 Where is the seat of more advanced math operations?

a typical hardware/software tradeoff.

MMux ALU

Full text

Arithmetic Logic Unit (ALU)

Introduction to Computer p Yung-Yu Chuang

Let's Make an Adder Circuit Goal. x + y = z for 4-bit integers.

Let's Make an Adder Circuit

Step 1. Represent input and output in binary.

Let's Make an Adder Circuit Goal. x + y = z for 4-bit integers.

Step 2. [first attempt]

Q. Why is this a bad idea?

A 128-bit adder: 2

rows >> # electrons

A. 128-bit adder: 2

rows >> # electrons

in universe!

1-bit half adder

We add numbers one bit at a time.

1-bit full adder

8-bit adder

Let's Make an Adder Circuit Goal. x + y = z for 4-bit integers.

Step 2. [do one bit at a time]

Let's Make an Adder Circuit Goal. x + y = z for 4-bit integers.

Step 3.

Let's Make an Adder Circuit Goal. x + y = z for 4-bit integers.

Step 4.

Adder: Interface

Adder: Component Level View

Adder: Switch Level View

Subtractor Subtractor circuit: z = x – y.

Subtractor Subtractor circuit: z = x – y.

Subtractor Subtractor circuit: z = x – y.

Shifter

Shifter

z

z

z

z

z

z

z

z

s

ss

s

s

Shifter

z

z

z

z

z

z

z

z

s

x

x

x

x

s 0 x x x

s

0 x

x

x

s

0 0 x

x

0 0 0

s

0 0 0 x

z0 = s0‧x0 + s1‧0 + s2‧0 + s3‧0

z1 = s0‧x1 + s1‧x0 + s2‧0 + s3‧0

z2 = s0‧x2 + s1‧x1 + s2‧x0 + s3‧0

z3 = s0‧x3 + s1‧x2 + s2‧x1 + s3‧x0

Shifter

z0 = s0‧x0 + s1‧0 + s2‧0 + s3‧0

z1 = s0‧x1 + s1‧x0 + s2‧0 + s3‧0

z2 = s0‧x2 + s1‧x1 + s2‧x0 + s3‧0

z3 = s0‧x3 + s1‧x2 + s2‧x1 + s3‧x0

N-bit Decoder N-bit decoder

!"#$%&amp

!"#$%&amp