適用於類比與混合訊號電路系統之時間延遲電路設計與製作
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![Figure 1-5 A coarse-fine TDC structure in all-digital phase-locked loop. [1]](https://thumb-ap.123doks.com/thumbv2/9libinfo/9604121.630357/24.892.191.771.124.700/figure-coarse-fine-tdc-structure-digital-phase-locked.webp)
![Figure 2-3 The delay-line based data converter [10].](https://thumb-ap.123doks.com/thumbv2/9libinfo/9604121.630357/33.892.236.783.118.829/figure-delay-line-based-data-converter.webp)
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![Figure 2-4 A current starved inverter with a degeneration cell and parallel bias devices [12]](https://thumb-ap.123doks.com/thumbv2/9libinfo/9604121.630357/34.892.138.754.674.907/figure-current-starved-inverter-degeneration-cell-parallel-devices.webp)
![Figure 2-5 Time based pipelined ADC [13]. (a) Time based pipelined ADC implementation](https://thumb-ap.123doks.com/thumbv2/9libinfo/9604121.630357/37.892.238.783.119.532/figure-time-based-pipelined-time-based-pipelined-implementation.webp)
![Figure 2-11 Pulse-train based TA [26]](https://thumb-ap.123doks.com/thumbv2/9libinfo/9604121.630357/43.892.166.734.734.984/figure-pulse-train-based-ta.webp)
![Figure 2-12 Basic idea of the proposed TA in [27]. (a) Cross coupled chains](https://thumb-ap.123doks.com/thumbv2/9libinfo/9604121.630357/45.892.183.713.428.761/figure-basic-idea-proposed-ta-cross-coupled-chains.webp)
![Figure 2-13 TA using DLL-like closed-loop control. [27]](https://thumb-ap.123doks.com/thumbv2/9libinfo/9604121.630357/46.892.203.784.118.405/figure-ta-using-dll-like-closed-loop-control.webp)
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