Top PDF A Spread-Spectrum Clock Generator With Triangular Modulation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 4, APRIL 2003 673 A Spread-Spectrum Clock Generator With Triangular Modulation Hsiang-Hui Chang, Student Member, IEEE, I-Hui Hua, and Shen-Iuan Liu, Member, IEEE Abstract—In this paper, a spread-spectrum clock generator (SSCG) with triangular modulation is presented. Only a divider and a programmable charge pump are added into a conventional clock generator to accomplish the spread-spectrum function.

V. C ONCLUSION In this work, a new 400-MHz SSCG which adopts a direct VCO modulation is presented. By using a dual-path loop filter, the capacitance of the low-frequency loop filter is so signifi- cantly reduced such that full integration becomes possible. At the same time, a triangular modulation of spectral spread is easily obtained by the appropriate inclusion of both an extra charge-pump circuit and an isolated buffer in the loop filter. The determination of zero, loop bandwidth, modulation frequency, pole, and comparison clock are carefully studied. The chip is fabricated using a 0.35- m standard CMOS process. The mea- surement results are mostly as predicted.

are the same as the conventional triangular modulation. Table I sum- marizes the jitter and timing comparisons of DTM and RDTM with 16 subsections within one modulation cycle. With two control signals, spreading step (S) and number of subsec- tions (COUNT), the proposed RDTM can provide a flexible spreading ratio for different system requirements. Spreading step is the difference of DCO control code between two consecutive subsections. Number of subsections determines how many subsections in one modulation cycle. COUNT and S decoded from SEC_SEL and STEP by the mod- ulation controller, respectively. Based on the definitions, the frequency- spreading ratio equation can be given as

It is difficult to determine the real peak–peak modulation ratio and the shape of the triangular modulation in the frequency domain. Therefore, the time-domain modulation profile is verified in Fig. 16. The solid line and dashed line represent the profile of the proposed TPDL-SSCG and the profile of conven- tional FN-SSCG, respectively. The measured modulation ratios are 0.55% and 0.507% for the conventional FN-SSCG and the TPDL-SSCG, respectively. The measured modulation ratio of the TPDL-SSCG is very close to the simulation results, 0.506%, listed in Table II. The measured modulation profile for the conventional FN-SSCG looks like a distorted triangular wave- form due to the insufficient PLL bandwidth; therefore, the EMI performance is bad. The measured jitter, using a self-triggered method under different conditions, is shown in Fig. 17. The mea- sured rms jitter is 4.748 and 5.485 ps at SSC- OFF and SSC- ON , respectively. The measured peak-to-peak jitter is 30 and 35 ps at SSC- OFF and SSC- ON , respectively. Only a 0.737-ps rms jitter is increased when the TPDL-SSCG is active, which is very close to the theoretical estimation of 0.556 ps (=0.5%/1500 MHz/6).

11 Measured spectra of 400MHz output frequency a at non-spread spectrum mode, b of the conventional SSCG with 2.5% spread ratio, and c of the TPDL-SSCG with 2.5% spread ratio... 12 Measu[r]

Hsin-Chu, Taiwan 300 yhkao@chu.edu.tw Abstract—A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSG has been fabricated in a 0.35um CMOS process. The clock of 400MHz with center spread ratios of 1.25% and 2.5% are verified. The size of chip area is 0.90×0.89mm 2 .

Fig. 10 presents a chip photograph of this paper and its summary. The technology used is a 0.18-μm complementary metal–oxide–semiconductor (CMOS) with a supply voltage of 1.8 V. The BIST circuit area is 15% of the SSCG, which includes the DFFs and phase-shift detector of the MPD but does not include the accumulator or other digital circuits. The BIST is operated at 20 MHz, which is the same as the reference clock frequency. The SSCG is a fractional-N PLL with a ten-phase 1.2-GHz VCO, a third-order loop filter, and a MASH-111 SDM to meet the SATA-III specification. In total, 10 4 data outputs by the phase-shift detector are recorded by a logic analyzer.

Index Terms— Correlator, delay-locked loop, direct sequence spread spectrum, tracking error variance. I. S YSTEM D ESCRIPTION AND S IGNAL M ODEL I N THIS letter, we present a code tracking receiver with less complexity, by employing a differentially coherent tech- nique originally proposed for pseudonoise (PN) acquisition receiver [3]. The proposed differentially coherent delay-locked loop (DCDLL) scheme is shown in Fig. 1. The received signal is first filtered by front-end band-pass filter (BPF) and the bandwidth of BPF is . is set to be chip rate ( , where is the chip duration). Then this proposed DCDLL scheme processes the received signal using a differential decoder with a delay of -chip duration in the delay path. The decoder output is then correlated with the difference of the advanced (early) and retarded (late) versions of the local PN code to produce an error signal. After the error signal is filtered by a low-pass filter (LPF), then it drives the voltage-controlled clock (VCC) through the loop filter and corrects the code phase error of the local PN code generator. In this proposed system, the bandwidth of LPF, denoted as , is set to be the system data rate ( , where is the data bit duration). The processing gain of this direct-sequence spread-spectrum (DS/SS) system is thus given by or . Usually, if the system is applied in ranging, and

TABLE III B ANDWIDTH C OMPARISON R ESULTS B ETWEEN PSPN C ODES AND PN C ODES Fig. 4. Plot of bandwidth versus toggle rate of the spreading codes. The block of “frequency divider” generates the clock with data rate. PN code generator generates the PN code. Despreader is used for despreading procedure and the decision circuit detects the signal. The transistor netlist of the blocks in Fig. 6 is implemented. The circuit level simulator Hspice simulates the power consumption of the transistor netlist. All the blocks shown in Fig. 6 are included in this power consumption simulation. The circuit schematics described in Fig. 6 could be operated by different spreading codes with different code lengths. That is to say, this is a soft-coded spread spectrum system. The simulation results of the power consumption are listed in Table IV. From Table IV, we find the percentages of reduction for power consumption range from 8% to 14% with PSPN codes compared to PN codes. The concept of low toggle rate means low-power consumption has been verified by the simulation results.

4.7 Spread spectrum clock and skew control The output clocking scheme uses spread spectrum technology to lower RFI in the frequency domain. Moreover, skew control is also used to avoid ringing on supply voltage and then further causing glitches to the other circuits in the ADC. The 5 GHz clock signal is phase modulated with a lower frequency signal by changing the delay of another VCDL. The modulation signal is usually a triangular wave. The spectrum spread clock is then sent to the output buffers. The time window of the data signals that allow the clock to sample or latch is very narrow and may be varied by processes. The maximum extra delay should less than a half clock period, 0.1 ns. However, the initial clock edge position may already be early or late for the perfect position. Thus modulation signal is controlled flexibly from the outside of the ADC.

these subbands at the same time in the same channel, the SS-CDMA multiplexing scheme is particularly well suited to subband coding that divides the image informa[r]

A. System Block Diagram and Loop Parameters Design Fig. 11 shows a system block diagram of the cascaded dy- namic frequency counting loops for wide multiplication range applications. The system consists of two DFC loops in series, called DFC loop 1 and DFC loop 2. The first DFC loop 1 gen- erates low-frequency output, or intermediate frequencies for the DFC loop 2. DFC loops 1 and 2 have different loop parameters and DCO requirements. DFC loop 1 only requires a low-fre- quency DCO 1 and a low-frequency detector. By contrast, the second stage is a high-resolution DCO 2, and also requires a high-resolution frequency detector. Both DFC loops 1 and 2 can be disabled, depending on output requirement, by the mode control. To prevent false locking, the DFC loop 2 is enabled after DFC loop 1 is locked in the acquisition process when two loops are employed. Because the DCO is divided into two DCO ranges, DCO 1 has a smaller control code than the DCO of a single loop, thus shortening the locking time.

Here we consider a spread spectrum cellular radio architec- ture in which the whole service area is divided into cells and each cell is served by a base. A mobile [r]

Kaohsiung, Taiwan 80424 email : ccwang@ee.nsysu.edu.tw Abstract The rapidly improved performance of latest CPUs introduces higher clock rates for peripheral devices. Moreover, DDR(double data rate)has been one of the most important methods to increase the throughput of a system, e.g., SDRAM. The edges of the reference clock, thus, become deadly important to these high-speed and high-clock applications. In this paper, we present a pulse generator circuit to generate pulses corresponding to the rise edge and fall edge of a given clock, respectively, without any phase shift and delay. These pulse trains can be used to synchronize the peripherals. The noise rejection is also proved when the given clock is coupled with a 10\% noise. The proposed circuit can be applied to other clock rates beyond 133 MHz as long as the sizes of the delay elements are properly tuned.

Kaohsiung, Taiwan 80424 email : ccwang@ee.nsysu.edu.tw Abstract The rapidly improved performance of latest CPUs introduces higher clock rates for peripheral devices. Moreover, DDR(double data rate)has been one of the most important methods to increase the throughput of a system, e.g., SDRAM. The edges of the reference clock, thus, become deadly important to these high-speed and high-clock applications. In this paper, we present a pulse generator circuit to generate pulses corresponding to the rise edge and fall edge of a given clock, respectively, without any phase shift and delay. These pulse trains can be used to synchronize the peripherals. The noise rejection is also proved when the given clock is coupled with a 10\% noise. The proposed circuit can be applied to other clock rates beyond 133 MHz as long as the sizes of the delay elements are properly tuned.

For the transmission of images over SS-CDMA AWGN channels, a subband coding scheme that divides the image information into a number of independent data streams using an analysis filter bank, each of which is multiplied by its unique signature PN code, enables the transmission of these data streams via multiple parallel virtual channels created by their correspond- ing PN codes. With a sufficiently large number of streams, the total signal is able to fit within the narrow radio channel bandwidth even though the total bandwidth of all the signals may exceed the channel bandwidth. At receiver, each received signal is separately recovered at the decoder by multiplying its PN code and integrating over the code length in order to obtain the desired subband. All the recovered subbands are then reassembled by a synthesis filter bank into a close reproduction to the original image. Additionally, for color subband image transmission, color images are first transferred to luminance (Y) and two chrominance components (I, Q). Each component is then decomposed independently into several subbands for SS-CDMA transmission. Therefore, a number of additional PN codes are required to support the transmission of the chrominance signals over the CDMA channels whereas the luminance signal was treated in the same manner as monochrome pictures. Moreover, SS-CDMA allows more than one image to be transmitted and be accessed simultaneously at the same limited channel bandwidth.

For those matched filters with long stages, this new architecture saves half the number of M and A in comparison with the conventional filter, while maintaining an identical p[r]

1 Introduction Channel modeling simulation tools that enable researchers and designers to accurately predict the performance of wire- less systems become increasingly important as personal com- munications and wireless data services evolve. A basic under- standing of the channel is important not only for designing modulation and coding schemes for robust communication over such channel, but also for investigating the channel fad- ing impact on existing networking algorithms, such as rout- ing and power adjustment which critically depend on channel attenuation. At present, most network protocol simulations and even power control algorithms are using the free space (distance) channel propagation model which is basically only function of transmitter-receiver distance. Typically, for the indoor environment, the channel characteristics are much too complex to be modeled by simple distance functions. Yet, a realistic channel model is essential for network protocol eval- uation, especially in the presence of mobility. Therefore, a more realistic channel fading model which accounts for chan- nel quality variations with movement is needed for network protocol simulation.

Publisher Item Identifier S 0733-8716(00)00191-8. cars, remote hospitals, military services, homes, and office automation systems is an attractive proposition. It would free the users from cords or optical fibers tying them to particular locations within the building, thus offering true mobility which convenient and sometimes even necessary. The development of multimedia terminals will support the ever-growing demand for mixed data, audio, and video applications and will connect the portable pen pad and lap-top devices to backbone information resources and computational facilities. The possibility of multimedia services will allow services such as dial-up video conference, video-on-demand (VOD) services, and portable PC-based applications incorporating video/audio/data transfer to any location. Moreover, a number of different mobile users can simultaneously request multimedia data from one or more multimedia servers on the network. Each multimedia server is capable of catering to multiple data requests from multiple users, simultaneously. Presentation of preorchestrated multimedia information requires synchronous playback of time-dependent multimedia data according to some prespeci- fied temporal relations. At the time of creation of multimedia information, a user needs a model to specify temporal con- straints among various data objects which must be observed at the time of playback. Usually, the temporal relationships of multimedia information may be characterized by a timeline diagram which is the commonly used tool in commercial multimedia authoring products. Fig. 1 depicts an example of a timeline diagram and its associated multimedia title generated by the most commonly used product called MacroMind Di- rector. Although the timeline diagram is a useful description tool, it has a lot of redundancies in characterizing the temporal relationships and is not suitable for further analysis and system evaluation, however. To tackle this difficulty and to obtain a more compact multimedia representation, a well-known model called object-composition Petri-net (OCPN) [3], [4] is able to describe the temporal relationships of the various components of a multimedia document and represents them in the form of a graph. Since preorchestrated multimedia information has highly time-varying bandwidth, the fixed bandlimited constant bit rate (CBR) wireless channel may not be appropriate for the variable bit rate (VBR) multimedia services. Therefore, it is desirable to design a dynamic mechanism to manage and allocate bandwidth according to the changing levels of concurrencies of multimedia data streams. Woo et al.[5] have introduced a dynamic RF channel capacity allocation to deal with the OCPN-based multimedia data stream. In this paper, an alternative method has been proposed to provide a cost-effective resource allocation scheme for the OCPN-based multimedia services by employing the well-known antimultipath spread

The performance analysis of UWB techniques combining with MC-SS (multi-carrier spread-spectrum) system working in multi-path fading channel is investigated in this paper. The model of the multi-path fading is characterized by Nakagami-m statistical distribution. We establish and derive the model for MC-CDMA (multi-carrier code-division multiple-access) systems working in correlated Nakagami-m fading channel. The average BER（bit error rate）is calculated and compared to the special case of the published results. Basically、some studied results from this paper can be implied to approve the system performance for the UWB system combining with a MC-CDMA system in wireless communication systems. Especially、it is worthwhile noting that the fading parameter of the Nakagami-m distributed significantly dominates the system performance of the UWB system accompany with MC-SS signaling under fading environments. On the other hand、the fact is discovered that the effect of power decay ratio parameter will be ignored after the SNR (signal-to-noise ratio) of the transmitted bit is greater than about 50 dB.