[PDF] Top 20 A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding
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A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding
... Terms—H.264/AVC, motion estimation, video ...flexible and powerful with the development of semiconduc- tors, digital signal processing, and communication ... See full document
6
Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC
... contributed a new VLSI architecture for frac- tional motion estimation of ...analyzed and two decom- posing techniques are proposed to parallelize the algorithm ... See full document
4
Efficient hierarchical motion estimation algorithm and its VLSI architecture
... Terms—Hierarchical, motion estimation, multiresolution, ...popular video compression standards, including MPEG-4, MPEG-2, and MPEG-1, is motion ...of ... See full document
14
Fast multi-frame motion estimation for H.264 and its applications to complexity-aware streaming
... previous video coding standards such as MPEG-4 and ...frame motion compensation, and other advanced coding ...present a fast motion ... See full document
4
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
... online: 4 June 2008 © 2008 Springer Science + Business Media, ...The H.264/AVC Fractional Motion Estima- tion (FME) with rate-distortion constrained mode decision can improve the ... See full document
13
Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
... designed for the previous stan- dards, where VBS and MRF are not supported, the parameter of our design is set as the single-iteration 4SS with one reference ...processes and supply voltages ... See full document
10
An Efficient Mode Preselection Algorithm for Fractional Motion Estimation in H.264/AVC Scalable Video Extension
... Abstract—The video coding standard, H.264/AVC scalable video extension (SVC), adopts various advanced interlayer pre- diction modes to explore the data redundancies between ... See full document
12
PMRME: A parallel multi-resolution motion estimation algorithm and architecture for HDTV sized H.264 video coding
... The simulation results show that for the threshold voltage variation (AVTH), the constant current the proposed circuit can compensate for AVTH and improve the.. source is difficult to de[r] ... See full document
4
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
... Analysis, Fast Algorithm, and VLSI Architecture Design for ...Chen, and Liang-Gee Chen, Fellow, IEEE Abstract—Intra prediction with rate-distortion constrained mode ... See full document
24
An efficient binary motion estimation algorithm and its architecture for MPEG-4 shape encoding
... is a software approach. Thus, our proposed algo- rithm is suitable for software and hardware ...implementation. For hardware design comparison, the proposed algorithm is simple to be ... See full document
10
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
... HARDWARE ARCHITECTURE DESIGN FOR VARIABLE BLOCK SIZE MOTION ESTIMATION IN MPEG-4 AVC/JVT/ITU-T H.264.. Yu- Wen Huang, Tu-Chih Wang, Bing-Yu Hsieh, and Liang-Gee Chen DSPlIC Design L[r] ... See full document
4
Low power and power aware fractional motion estimation of H.264/AVC for mobile applications
... Furthermore, if the PERFORMANCE OF CANDIDATE LEVEL DR FOR THE PROPOSED PARALLEL power is very low, we can even support only half-pel or integer- ARCHITECTURE.. pel resolution with one re[r] ... See full document
4
Analysis and reduction of reference frames for motion estimation in MPEG-4 AVC/JVT/H.264
... we analyze the available information after intra prediction and mo- tion estimation from previous one frame to determine whether it is necessary to search more frames.. The information[r] ... See full document
4
Fast Bi-Directional Prediction Selection in H.264/MPEG-4 AVC Temporal Scalable Video Coding
... BW, and BI) at the SVC temporal enhancement ...the coding information by applying the exhaustive search on uni- and bi-directional predictions before the optimal partition size is ...distributions ... See full document
16
Analysis and architecture design of variable block-size motion estimation for H.264/AVC
... Tree architecture, all distortions of a searching candidate are generated in the same cycle, and by an adder tree, distortions are accumulated to derive the SAD in one ...provide a high ... See full document
16
A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video
... of a low cycle count, which is crucial to HD ...levels for data reuse ...range for the most frequently occurring ...our algorithm is the unequal distribution of MV that most of them are near ... See full document
10
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture
... Fig. 4. While MB4 is in IME stage, MB3 is in FME stage, MB2 is predicted by INTRA, and MB1 is processed by EC and ...of a row is processed in IME stage, it takes more time to reload the ... See full document
4
Platform architecture design for MPEG-4 video coding
... They have highest flexibility but to achieve the real-time performance under the limited resources, the fast algorithms of motion estimation (ME) and discrete cosine tran[r] ... See full document
4
Parallel 4×4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264
... The input bit width of the second I D transform is 12 bits from the transpose register array and the output should be 15 bits.. 4 x 4 inverse transform for residual block[r] ... See full document
4
Global elimination algorithm and architecture design for fast block matching motion estimation
... GEA and its architecture design for fast block matching ...Our algorithm can solve several problems en- countered by ...block, and then to precisely compare the best ... See full document
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