[PDF] Top 20 Converter-free multiple-voltage scaling techniques for low-power CMOS digital design
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Converter-free multiple-voltage scaling techniques for low-power CMOS digital design
... of multiple supply voltages and do not require level ...employing multiple supply voltages need level converters to prevent static currents, which may result in large power ...supply voltage ... See full document
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An Optimization-based Multiple-Voltage Scaling Technique for Low Power CMOS Digital Design
... As illustrated in previous works, most long paths in a complex circuit are actu- ally false. Furthermore, a significant portion of long false paths do not need to be shortened. 14 We may need only to shorten long ... See full document
12
A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique
... SIDO converter with a switchable D/A LDO regulator for improving supply ...dropout voltage to achieve the tradeoff of ripple suppression function and high efficiency ...to digital op- eration ... See full document
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Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end
... rejection. For testing consideration, the three ports are also designed to match with 50 ...If multiple power supplies can be used in the receiver front-end, the simulated power consumption of ... See full document
13
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter
... the power supply SIDO converter module are ...nm CMOS process. The SIDO DC-DC converter generates two high efficiency power outputs for different circuit blocks with only one ... See full document
17
A low power high accuracy CMOS time-to-digital converter
... the mismatch among pulse-shrinking delay elements results in poor delay line linearity.. This sets a serious limit to the TDC resolution.[r] ... See full document
4
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings
... required power for each instruction according to the instruc- tion power table, which is generated by the iDVS CAD design ...the voltage transition command is is- sued before an ... See full document
13
An optimization-based low-power voltage scaling technique using multiple supply voltages
... Based on the critical order, we increase the supply voltages of the gates in order until the delays of all selected long paths are no more than the given timing constraint.. The [r] ... See full document
4
Sensitisable-path-oriented clustered voltage scaling technique for low power
... However, if the circuit is considered to be under V,,, at the beginning, our PCVS technique can take advantage of the path sensitisation criterion and path selection [r] ... See full document
7
Highly accurate cyclic CMOS time-to-digital converter with extremely low power consumption
... The FELC device proved ideal for this application, as the drive signal for the shutter elements were easily derived from the camera and framestore circuits.. This gives a modest drive[r] ... See full document
3
Power-Tracking Embedded Buck-Boost Converter With Fast Dynamic Voltage Scaling for the SoC System
... PTE-BB converter for the SoC system. Particularly, a high voltage supply is needed to provide better driving capability during the data transmission ...PTE-BB converter operates in pure buck ... See full document
12
Back-gate forward bias method for low-voltage CMOS digital circuits
... Since the implementation of the method requires the bulk or substrate forward biased, guidelines must be carefully established in order to avoid malfunction or permane[r] ... See full document
7
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
... high-voltage CMOS ICs becomes worse. Fig. 10(a) and (b) shows the measured voltage wave- forms of a high-voltage FOD device under TLU test with posi- tive and negative charging voltages, ... See full document
9
Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes
... A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only IxVDD devices for 3xVDD-tolerant mixed-voltage [r] ... See full document
2
1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder
... 1.5V CMOS Bootstrapped Dynamic Logic Circuit Techniques (BDLCT) Suitable(for Low-Voltage Deep-Submicron CMOS VLS1)ifor.. Implementing 482MHz Digital Quadrature Modulator and Ad[r] ... See full document
4
Evolution of low-voltage CMOS digital VLSI circuits using bootstrap technique
... As shown in the figure, this driver is composed of two bootstrap capacitors with the DTMOS technique for magnifying the input signals to overcome the shortage of the gate voltage over-dr[r] ... See full document
3
Low-power wordline voltage generator for low-voltage flash memory
... the low standby current, the voltage divider requires large resistors in standby ...of power supply voltage and temperature has great influence on the average standby current ... See full document
4
Design of mixed-voltage crystal oscillator circuit in low-voltage CMOS technology
... a voltage gain and 180- degree phase shift, which is integrated into the chip with the XI and XO ...of power supply voltage, therefore the inverting amplifier is operating in the high-gain linear ... See full document
4
Low-Power Techniques for Network Security Processors
... files for each suite and computed their average en- ergy consumptions of different components from the results of the simulator, as shown in Figure ...without power management and others labeled by P are ... See full document
6
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
... designs for the mixed-voltage I/O circuits without suffering the gate-oxide reliability ...protection design without increasing the process complexity is strongly requested by the mixed-voltage ... See full document
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