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[PDF] Top 20 Enhanced active feedback technique with dynamic compensation for low-dropout voltage regulator

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Enhanced active feedback technique with dynamic compensation for low-dropout voltage regulator

Enhanced active feedback technique with dynamic compensation for low-dropout voltage regulator

... LDO regulator vary according to load conditions, the phase margin must be designed high enough to maintain ...new compensation topology capable of overcoming these ...tion technique, regardless of ... See full document

12

Fast Transient Low-Dropout Voltage Regulator With Hybrid Dynamic Biasing Technique for SoC Application

Fast Transient Low-Dropout Voltage Regulator With Hybrid Dynamic Biasing Technique for SoC Application

... Corrector for Phase Lead-Compensated Buck Converter in DVS Applications Shaowei Zhen, Xiaohui Zhu, Ping Luo, Yajuan He, and Bo Zhang Abstract— Modern low-power system on a chip needs direct current ... See full document

6

A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique

A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique

... micrograph with an active silicon area of 2 mm ...in active mode. For complete analysis, power efficiency, defined as and related to quiescent current and dropout voltage at ... See full document

11

CMOS low dropout linear regulator with single Miller capacitor

CMOS low dropout linear regulator with single Miller capacitor

... Integrated low dropout (LDO) linear regulators [1–4] are widely used in portable battery-operated electronic devices such as mobile phones and ...required regulator has to have low static ... See full document

2

A CMOS low dropout regulator stable with any load capacitor

A CMOS low dropout regulator stable with any load capacitor

... conventional compensation scheme for LDO and its limitation are ...new compensation technique using pole-zero pairs cancellation is proposed to improve the sable range for the load ... See full document

4

A Low-Dropout Regulator With Smooth Peak Current Control Topology for Overcurrent Protection

A Low-Dropout Regulator With Smooth Peak Current Control Topology for Overcurrent Protection

... negative feedback loop from current sensing ...output voltage will be added into the peak current detector and prevent an unregulated ...output voltage is close to the settled voltage and the ... See full document

9

Low-Dropout Regulators With Adaptive Reference Control and Dynamic Push-Pull Techniques for Enhancing Transient Performance

Low-Dropout Regulators With Adaptive Reference Control and Dynamic Push-Pull Techniques for Enhancing Transient Performance

... LDO regulator with ARC technique when load current changes from 1 to 100 mA, or vice ...ARC technique can smoothly adjust reference voltage to stabilize output voltage in case of ... See full document

7

A low-voltage CMOS LNA design utilizing the technique of capacitive feedback matching network

A low-voltage CMOS LNA design utilizing the technique of capacitive feedback matching network

... proposed technique of capacitive feedback matching network and LNA structure, an experimental chip of a LNA operated at 13 GHz was designed and fabricated in ...a low input return loss ... See full document

4

New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process

New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process

... design with threshold-voltage com- pensation for analog circuits on glass substrate is a very impor- tant challenge for SoP ...design technique with switches and capacitors under ... See full document

6

A low power 5Gb/s transimpedance amplifier with dual feedback technique

A low power 5Gb/s transimpedance amplifier with dual feedback technique

... In order to eliminate this effect on core amplifier's bandwidth, a second shunt-shunt feedback network is incorporated in the output of the core amplifier.. The transi[r] ... See full document

4

Low voltage BiCMOS dynamic logic gates

Low voltage BiCMOS dynamic logic gates

... This design offers an effective speed improvement over other existing designs, such as merged BiCMOS (M-BiC- MOS) [2] and quasi-complementary BiCMOS (QC-BiCMOS) 131[r] ... See full document

2

Sensitisable-path-oriented clustered voltage scaling technique for low power

Sensitisable-path-oriented clustered voltage scaling technique for low power

... However, if the circuit is considered to be under V,,, at the beginning, our PCVS technique can take advantage of the path sensitisation criterion and path selection [r] ... See full document

7

Smooth Pole Tracking Technique by Power MOSFET Array in Low-Dropout Regulators

Smooth Pole Tracking Technique by Power MOSFET Array in Low-Dropout Regulators

... The power MOSFET array makes the power stage be turned on/off in a proper sequence to achieve smooth pole tracking. Basically, the turn-on sequence is from the large power MOS transistor to the small power MOS transistor ... See full document

7

An Optimization Technique for RF Buffers with Active Inductors

An Optimization Technique for RF Buffers with Active Inductors

... an active inductor with reasonable Q is suitable for RF buffer ...Proposed Active Inductor Design and Analysis Figure 4 shows the proposed the active inductor ... See full document

4

Ultra-low voltage implicit multiplexed differential flip-flop with enhanced noise immunity

Ultra-low voltage implicit multiplexed differential flip-flop with enhanced noise immunity

... ultra-low voltage 22T implicit multiplexed differential (IMD) flip- flop (FF) is ...IMD-FF with modified differential topology provides a sufficient noise margin under voltage ...save ... See full document

2

An Optimization-based Multiple-Voltage Scaling Technique for Low Power CMOS Digital Design

An Optimization-based Multiple-Voltage Scaling Technique for Low Power CMOS Digital Design

... As illustrated in previous works, most long paths in a complex circuit are actu- ally false. Furthermore, a significant portion of long false paths do not need to be shortened. 14 We may need only to shorten long ... See full document

12

Flywheel Energy Storage System for Voltage Sag Compensation

Flywheel Energy Storage System for Voltage Sag Compensation

... transform, voltage sag, flywheel energy storage system I. I NTRODUCTION Voltage sag is considered to be one serious instantaneous attack to the power grid and important ...facilities. For power ... See full document

6

Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers

Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers

... BiCMOS integrated circuits The Letter presents a low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for VLSI implementation of fuzzy contr[r] ... See full document

2

Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings

Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings

... controller with the timing diagrams as depicted in ...synchronous with the edge-trig- gered clock signal ...power for each instruction according to the instruc- tion power table, which is generated ... See full document

13

Power PHEMT with compact device layout for low voltage CDMA application

Power PHEMT with compact device layout for low voltage CDMA application

... Tlic doiible gale i " c s s wiis pcrfornied to iiicrcasc tlic dcvicc hresktlowii anti rcdiicc ihe ilevicc sourcc resishiiw using it dilute citric acid hiscd solution.. [r] ... See full document

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