Top PDF Low jitter Butterworth delay-locked loops

Low jitter Butterworth delay-locked loops

Low jitter Butterworth delay-locked loops

Modern CMOS techniques can not only integrate many digital circuits into a system, but also raise the operating clock frequency of the digital systems. However, the higher opera[r]

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Performance analysis of noncoherent digital delay locked loops for direct sequence spread spectrum systems with Doppler shift and quantized adaptation

Performance analysis of noncoherent digital delay locked loops for direct sequence spread spectrum systems with Doppler shift and quantized adaptation

Fig. 7 shows the effects of quantized adaptation on MSE and MTLL for case I. As is evident, for a large code Doppler, too small a will result in a significant performance loss; 4 is a necessity in this case. Fig. 8 shows the same effects for Case II. As seen, unlike Case I an optimal exists, depending on SNR; a large not necessarily gives a better performance. This is especially true at low SNRs, where the tail ends of impose a significant adverse effect on the loop performance.

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A wide-range and fast-locking all-digital cycle-controlled delay-locked loop

A wide-range and fast-locking all-digital cycle-controlled delay-locked loop

VI. C ONCLUSION A wide-range and fast-locking all-digital DLL is presented in this paper. The CCDU enlarges the operating frequency range of the proposed DLL by a factor of without decreasing timing resolution. The two-step SAR controller ensures the DLL to lock the input clock within 32 clock cycles regardless of the input frequencies. The DLL operates in open-loop fashion once lock occurs in order to achieve low jitter operation with small area and low power dissipation. Since the DLL will not track temperature or supply variations once it is in lock, it is best suited for burst mode operation. Given a supplied reference input with 50% duty cycle, the DLL generates an output clock with the duty cycle of nearly 50% over the entire operating frequency range and achieves an acceptable jitter performance as compared to a conventional analog DLL [8]. The proposed all-digital DLL is suitable for the advanced deep-submicron technologies. If more advanced technologies were used, the performance of the DLL such as operating frequency range and jitters could be improved with a little design effort. The power consumption and the total die area would be reduced as well.
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A novel phase-noise-suppressed and delay-time-tunable mode-locked erbium-doped fiber laser

A novel phase-noise-suppressed and delay-time-tunable mode-locked erbium-doped fiber laser

Ó 2002 Published by Elsevier Science B.V. Keywords: Erbium-doped; Fiber laser; Mode-locking; Phase noise; Phase-shift; Delay-time; Frequency-discriminated Harmonic mode-locking has been considered as one of the promising techniques to construct high- repetitive optical pulse laser sources with relatively short pulsewidth [1–3]. It has been demonstrated that the mode-locked erbium-doped fiber lasers (EDFLs) based on this technique can provide stable and nearly transform-limited picosecond optical pulses with very low timing jitter [2]. These active harmonic mode-locked EDFLs have found versatile applications in ultra-high bit-rate optical transmission, high-speed optical time division
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BIST for measuring clock jitter of charge-pump phase-locked loops

BIST for measuring clock jitter of charge-pump phase-locked loops

Table I presents more cases. Figs. 23 and 24 compare the p-p jitter and the rms jitter measured using an oscilloscope and a BIST circuit. The measurement errors in most of the cases are under 20%, except in the case with a 1-MHz noise. As mentioned in Section II, the TDC utilizes the VCO and loop filter of the PLL under test as parts of the circuit, but the initial value of the VCO control voltage is not constant due to supply noise and PLL-tracking ability. This is believed to be the main cause of the measurement error in the experimental result.

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On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines

On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines

6. Conclusion A CDF-based RMS jitter testing algorithm for Gaussian or Gaussian-like jitter distribution is proposed in this paper. The features of the proposed algorithm include a low tap- count coarse delay line for CDF sampling and a sophisti- cated post-processing algorithm that achieves high process variation tolerance. Simulation results show that, in the presence of up to 30Q delay line deviations, the success rate of making correct pass/fail decisions is 99%. Current- ly, we are investigating more efficient algorithms to determine the test algorithm parameters. Also, a prototype chip has been fabricated for silicon proof.
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The Jitter Delay Guarantees by Buffer Control in Multimedia Environments

The Jitter Delay Guarantees by Buffer Control in Multimedia Environments

Workshop : Computer Networks Title : The Jitter Delay Guarantees by Buffer Control in Multimedia Environments Abstract: In applications of multimedia networks, Transmissions involving data, audio, graphics, video, images, and animation are provided. The QoS (quality of service) guarantees the above medias are stringent topics. A good QoS has the ability to reserve resources within network and terminal devices to ensure that certain perceptual performance measures are meet. For QoS guarantee, the technique by using buffer compensation is necessary. The decision problem about how large the buffer size for selections is an interesting issue. At this paper we are concentrating on the compensation of jitter delay at the destination by using buffer control. If the buffer size is too large, the system resources are wasting, in another aspect, too short buffer will not guarantee the system performance requirements. In this paper our propose an simple formula on calculating an adequate buffer size for delay jitter control at the destination node by Chernoff bound methods, the jitter is properly controlled without wasting too much unnecessary resources and the performance is guaranteed in the real time multimedia environments.
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Method for designing a temperature measurement system using two phase-locked loops

Method for designing a temperature measurement system using two phase-locked loops

In the past, complex analog conditioning circuits were de- signed to reduce the sensor nonlinearity, manual calibration, and precision resistors were required to achieve the desired accuracy. Today, however, sensor outputs may be digitized directly by high-resolution analog-to-digital 共A/D兲 convert- ers. Linearization and calibration are then performed digi- tally, thereby reducing cost and complexity. Thermocouples can operate over the widest range 共even up to ⫹2300 °C兲 compared with the other temperature sensors. But, their out- put is only millivolts and precision amplification is required for further processing. Resistance temperature devices 共RTDs兲 are accurate and generally used in bridge circuits, but require excitation current. 2,3 Thermistors have the highest sensitivity but nonlinear problems are also the severest among the three temperature sensors discussed. However, they are popular in portable applications such as measure- ment of battery temperature and other critical temperatures. 4 Semiconductor temperature sensors have the characteristics of high accuracy and high linearity over an operating range of about ⫺55 to ⫹150 °C. These semiconductor temperature sensors with internal amplifiers can scale the output to either current or voltage values. For example, AD590/TMP17 is a current output sensor with scale factors of 1 ␮ A/K, and TMP35/TMP36/TMP37 are low voltage output sensors with a 10/20 mV/°C scale factor. 5 However, their outputs require precision amplification for further processing. The digital
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A Time-Based Frequency Band Selection Method for Phase-Locked Loops

A Time-Based Frequency Band Selection Method for Phase-Locked Loops

Time-based frequency band selection method for phase-locked loops T.-H. Lin and Y.-J. Lai High-performance phase-locked loops (PLLs) often require voltage- controlled oscillators (VCOs) employing both discrete and continuous tuning mechanisms to satisfy a wide frequency range and a low VCO tuning gain simultaneously. An auxiliary circuit is required to facilitate the selection among a group of discrete bands. An agile technique to search for an optimum VCO frequency band is proposed.

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Comparison on the noise and jitter characteristics of harmonic injection-locked and mode-locked erbium-doped fiber lasers

Comparison on the noise and jitter characteristics of harmonic injection-locked and mode-locked erbium-doped fiber lasers

No. 1001, Ta Hsueh Rd., Hsinchu 30050, Taiwan, R.O.C. ABSTRACT We compare the noise characteristics of optical pulses generated from an actively mode-locked (AML) erbium-doped fiber laser (EDFL) with a semiconductor optical amplifier and an injection-locked EDFL with a gain-switched Fabry- Perot laser diode (FPLD). The mode-locked EDFL pulse exhibits a phase noise of -110.1 dBc/Hz (at 1 MHz offset frequencies from the carrier), the timing jitter of 1.16 ps, and a supermode noise suppression ratio of 47.5 dB. The injection-locked EDFL pulse exhibits a phase noise of -121.1 dBc/Hz (at 1 MHz offset frequencies from the carrier), a timing jitter of 0.31 ps, and a supermode noise suppression ratio of 51 dB. It is demonstrated that the injection-locked EDFL with a gain-switched FPLD has lower noise characteristics than the AML-EDFL.
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A Low-Cost Jitter Measurement Technique for BIST Applications

A Low-Cost Jitter Measurement Technique for BIST Applications

In this paper, we propose an RMS period jitter measure- ment technique for BIST applications. Assuming that the jitter is a gaussian random variable, RMS jitter is charac- terized by comparing the phase relationships (lead or lag) between the signal under test and two delay versions of it- self. This way, two points on the jitter’s CDF curve are obtained from which the RMS jitter value is derived. The proposed jitter measurement circuitry is quite simple. It consists mainly of a variable delay with two delay values, a sense-amplifier based phase comparator, and an inverter for delay measurement. Currently, SPICE simulation shows promising results: an average error of less than 5% for 40- 50 ps RMS jitter. We will implement a prototype chip to further validate the proposed technique.
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A 2 V clock synchronizer using digital delay-locked loop

A 2 V clock synchronizer using digital delay-locked loop

It consists of an improved bang-bang type phase comparator, a set of control logic, a 6-bit up/down counter, a digital controlled delay line (DCDL).. and on-chip receivers and d[r]

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Design and Simulation of an Efficient Real-Time Traffic Scheduler with Jitter and Delay Guarantees

Design and Simulation of an Efficient Real-Time Traffic Scheduler with Jitter and Delay Guarantees

Many scheduling algorithms, such as weighted fair queueing (WFQ) [2], weighted round-robin (WRR) [3], etc., have been proposed for general data communications. However, these algorithms simply deal with the reduction of implementation complexity and the improvement of packet delay bound and fairness. In other words, they are not designed to meet the requirements of real-time traffic streams. For example, one may not need to reduce the cell delay bound as small as possible when real-time streams are conveyed. Instead, one can choose to increase the statistical multiplexing gain as large as possible and meet the delay/jitter constraints at the packet level at the same time. Currently, nearly all data communication scheduling algorithms adopt work-conserving disciplines. As a result, they can only limit the CDV to trivial bounds. As is known, scheduling algorithms, such as WFQ and its extensions, inherently face the problem of trading off between jitter bound and statistical multiplexing gain. In other words, the duration over which the statistical multiplexing gain is performed must be restricted if a tight jitter bound is desired. Conversely, if the multiplexing gain is to be maximized, then the jitter bound must be relaxed and this may lead to the need for transmission overhead for source clock recovery.
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A Differentially Coherent Delay-Locked Loop for Spread Spectrum Tracking Receivers

A Differentially Coherent Delay-Locked Loop for Spread Spectrum Tracking Receivers

Index Terms— Correlator, delay-locked loop, direct sequence spread spectrum, tracking error variance. I. S YSTEM D ESCRIPTION AND S IGNAL M ODEL I N THIS letter, we present a code tracking receiver with less complexity, by employing a differentially coherent tech- nique originally proposed for pseudonoise (PN) acquisition receiver [3]. The proposed differentially coherent delay-locked loop (DCDLL) scheme is shown in Fig. 1. The received signal is first filtered by front-end band-pass filter (BPF) and the bandwidth of BPF is . is set to be chip rate ( , where is the chip duration). Then this proposed DCDLL scheme processes the received signal using a differential decoder with a delay of -chip duration in the delay path. The decoder output is then correlated with the difference of the advanced (early) and retarded (late) versions of the local PN code to produce an error signal. After the error signal is filtered by a low-pass filter (LPF), then it drives the voltage-controlled clock (VCC) through the loop filter and corrects the code phase error of the local PN code generator. In this proposed system, the bandwidth of LPF, denoted as , is set to be the system data rate ( , where is the data bit duration). The processing gain of this direct-sequence spread-spectrum (DS/SS) system is thus given by or . Usually, if the system is applied in ranging, and
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DC-balance low-jitter transmission code for 4-PAM-signaling

DC-balance low-jitter transmission code for 4-PAM-signaling

DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling Hsiao-Yun Chen, Chih-Hsien Lin, and Shyh-Jye Jou, Senior Member, IEEE Abstract—This investigation proposes a novel dc-balanced low- jitter transmission code, a 4-PAM symmetric code, for a 4-PAM signaling system. The 4-PAM symmetric code preserves all of the useful characteristics of the 8B/10B code such as dc-balanced serial data and guaranteed transitions in the symbol stream for clock re- covery. Moreover, the proposed method decreases the jitter of the timing transition of the data in the receiver and consumes half of the data bandwidth, because it transmits in 4-PAM. The design re- sults using the UMC 0.18- m process demonstrate that the new transmission code can decrease the jitter of the transition point by 25% of the transition region. The operation speed of the en- coder/decoder for the 4-PAM symmetric code is 819 MHz with 16-b inputs (13.1 Gb/s) and 704 MHz with 16-b outputs (11.3 Gb/s).
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A 14 GHz DLL based low-jitter multi-phase clock generator for low-band ultra-wideband application

A 14 GHz DLL based low-jitter multi-phase clock generator for low-band ultra-wideband application

A self-hiased adaptive bandwidth DLL using an auxiliary digital self-correcting loop is proposed to achieve an optimal jitter transfer characteristic and avoid false-lock[r]

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Laser dynamics and relative timing jitter analysis of passively synchronized Er- and Yb-doped mode-locked fiber lasers

Laser dynamics and relative timing jitter analysis of passively synchronized Er- and Yb-doped mode-locked fiber lasers

This serves as a feedback mechanism from the relative-pulse- timing to the center-optical-frequency and then subsequently to the laser repetition rate through the dispersion effect. Passive synchronization of the two lasers is made possible through such a feedback mechanism, and thus there will be a center optical frequency shift when the synchronization is achieved, which is determined by the balance of the XPM- induced frequency shift and the damping effect of gain filter- ing. This explains the lasing wavelength shift that has been observed experimentally. After verifying that the passive synchronization of two-color mode-locked fiber lasers can be achieved, we then employ the variational method and the linearization technique to derive the coupled equations for the center frequency and the relative timing position fluctua- tions from the pulse parameter evolution equations. The relative timing jitter is found to exhibit the dependence on the relative timing position of the two color pulses before the collision. The predicted dependence and the correspond- ing center optical wavelength shift for the Er laser agree rea- sonably with our previous experimental observations. The relative timing jitter between the two lasers can be minimized by appropriately adjusting their cavity length difference. The minimized relative timing jitter can be smaller than the timing jitters of individual passive mode-locked fiber lasers by at least a factor of 15 in the considered example. This revealed dependence can provide one flexible approach to further optimize the passively synchronized fiber laser systems for achieving ultra-low timing performances and for developing new applications.
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A Low-Power DCO Using Interlaced Hysteresis Delay Cells

A Low-Power DCO Using Interlaced Hysteresis Delay Cells

In this brief, a DCO using the interlaced hysteresis delay cells (IHDCs) is proposed to achieve a large delay and low power in a small area. The IHDC interlaces the signal transitions in two series of cascaded transistors. It prevents the short-circuit current and saves the leakage current in the shared current path. All the internal nodes are rail-to-rail driven to avoid high PVT variations. Also, the glitch protection circuit using a control code resampling synchronous cells is applied for better control of the DCO. This DCO is implemented with a simple demonstrative ADPLL, which generates the output clock from 180 to 530 MHz. Consequently, the total power consumption of less than 500 μW and the 0.0086-mm 2 area verify its power and area efficiency. The rest of this brief is organized as follows:
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A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle

A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle

Conventional DLLs may suffer from harmonic locking over wide operating range as shown in Fig.1. If the DLLs would operate at lower frequency without harmonic locking, the number of delay stages must be increased to let the maximum delay of the delay line equal to the period of the lowest frequency. However, the maximum operating frequency of a DLL will be limited by the minimum delay of the delay line.

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Modified TMN8 Rate Control for Low-Delay Video Communications

Modified TMN8 Rate Control for Low-Delay Video Communications

y In low rate video coding standards such as H.263, the change of QPs of two adjacent MBs, DQUANT, is restricted within two levels. Thus, if the complexity of two adjacent MBs is greatly different, the restriction may result in the following two possible drawbacks. First, if the previous MB is low complex and the current MB is high, the previous QP (denoted as QP prev ) will be small, so the current MB will be quantized too finely because its QP is limited to QP prev +2. Consequently, it will generate too much number of bits. This may result in the fact that the remaining bits are run out, and thus the remaining MBs should be quantized too coarsely. An alternative case is that the previous MB is high complex and the current MB is low. In this case, the QP prev
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