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[PDF] Top 20 Low jitter Butterworth delay-locked loops

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Low jitter Butterworth delay-locked loops

Low jitter Butterworth delay-locked loops

... Modern CMOS techniques can not only integrate many digital circuits into a system, but also raise the operating clock frequency of the digital systems. However, the higher opera[r] ... See full document

4

Performance analysis of noncoherent digital delay locked loops for direct sequence spread spectrum systems with Doppler shift and quantized adaptation

Performance analysis of noncoherent digital delay locked loops for direct sequence spread spectrum systems with Doppler shift and quantized adaptation

... Fig. 7 shows the effects of quantized adaptation on MSE and MTLL for case I. As is evident, for a large code Doppler, too small a will result in a significant performance loss; 4 is a necessity in this case. Fig. 8 shows ... See full document

11

A wide-range and fast-locking all-digital cycle-controlled delay-locked loop

A wide-range and fast-locking all-digital cycle-controlled delay-locked loop

... achieve low jitter operation with small area and low power ...acceptable jitter performance as compared to a conventional analog DLL ... See full document

10

A novel phase-noise-suppressed and delay-time-tunable mode-locked erbium-doped fiber laser

A novel phase-noise-suppressed and delay-time-tunable mode-locked erbium-doped fiber laser

... Phase-shift; Delay-time; Frequency-discriminated Harmonic mode-locking has been considered as one of the promising techniques to construct high- repetitive optical pulse laser sources with relatively short ... See full document

7

BIST for measuring clock jitter of charge-pump phase-locked loops

BIST for measuring clock jitter of charge-pump phase-locked loops

... Table I presents more cases. Figs. 23 and 24 compare the p-p jitter and the rms jitter measured using an oscilloscope and a BIST circuit. The measurement errors in most of the cases are under 20%, except in ... See full document

10

On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines

On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines

... RMS jitter testing algorithm for Gaussian or Gaussian-like jitter distribution is proposed in this ...a low tap- count coarse delay line for CDF sampling and a sophisti- cated post-processing ... See full document

12

The Jitter Delay Guarantees by Buffer Control in Multimedia Environments

The Jitter Delay Guarantees by Buffer Control in Multimedia Environments

... The Jitter Delay Guarantees by Buffer Control in Multimedia Environments Abstract: In applications of multimedia networks, Transmissions involving data, audio, graphics, video, images, and animation are ... See full document

8

Method for designing a temperature measurement system using two phase-locked loops

Method for designing a temperature measurement system using two phase-locked loops

... In the past, complex analog conditioning circuits were de- signed to reduce the sensor nonlinearity, manual calibration, and precision resistors were required to achieve the desired accuracy. Today, however, sensor ... See full document

6

A Time-Based Frequency Band Selection Method for Phase-Locked Loops

A Time-Based Frequency Band Selection Method for Phase-Locked Loops

... phase-locked loops T.-H. Lin and Y.-J. Lai High-performance phase-locked loops (PLLs) often require voltage- controlled oscillators (VCOs) employing both discrete and continuous tuning ... See full document

2

Comparison on the noise and jitter characteristics of harmonic injection-locked and mode-locked erbium-doped fiber lasers

Comparison on the noise and jitter characteristics of harmonic injection-locked and mode-locked erbium-doped fiber lasers

... No. 1001, Ta Hsueh Rd., Hsinchu 30050, Taiwan, R.O.C. ABSTRACT We compare the noise characteristics of optical pulses generated from an actively mode-locked (AML) erbium-doped fiber laser (EDFL) with a ... See full document

9

A Low-Cost Jitter Measurement Technique for BIST Applications

A Low-Cost Jitter Measurement Technique for BIST Applications

... period jitter measure- ment technique for BIST ...the jitter is a gaussian random variable, RMS jitter is charac- terized by comparing the phase relationships (lead or lag) between the signal under ... See full document

4

A 2 V clock synchronizer using digital delay-locked loop

A 2 V clock synchronizer using digital delay-locked loop

... It consists of an improved bang-bang type phase comparator, a set of control logic, a 6-bit up/down counter, a digital controlled delay line (DCDL).. and on-chip receivers and d[r] ... See full document

4

Design and Simulation of an Efficient Real-Time Traffic Scheduler with Jitter and Delay Guarantees

Design and Simulation of an Efficient Real-Time Traffic Scheduler with Jitter and Delay Guarantees

... packet delay bound and ...cell delay bound as small as possible when real-time streams are ...the delay/jitter constraints at the packet level at the same ...between jitter bound and ... See full document

12

A Differentially Coherent Delay-Locked Loop for Spread Spectrum Tracking Receivers

A Differentially Coherent Delay-Locked Loop for Spread Spectrum Tracking Receivers

... Correlator, delay-locked loop, direct sequence spread spectrum, tracking error ...coherent delay-locked loop (DCDLL) scheme is shown in ...a delay of -chip duration in the delay ... See full document

3

DC-balance low-jitter transmission code for 4-PAM-signaling

DC-balance low-jitter transmission code for 4-PAM-signaling

... DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling Hsiao-Yun Chen, Chih-Hsien Lin, and Shyh-Jye Jou, Senior Member, IEEE Abstract—This investigation proposes a novel dc-balanced low- ... See full document

5

A 14 GHz DLL based low-jitter multi-phase clock generator for low-band ultra-wideband application

A 14 GHz DLL based low-jitter multi-phase clock generator for low-band ultra-wideband application

... A self-hiased adaptive bandwidth DLL using an auxiliary digital self-correcting loop is proposed to achieve an optimal jitter transfer characteristic and avoid false-lock[r] ... See full document

4

Laser dynamics and relative timing jitter analysis of passively synchronized Er- and Yb-doped mode-locked fiber lasers

Laser dynamics and relative timing jitter analysis of passively synchronized Er- and Yb-doped mode-locked fiber lasers

... timing jitter is found to exhibit the dependence on the relative timing position of the two color pulses before the ...timing jitter between the two lasers can be minimized by appropriately adjusting their ... See full document

8

A Low-Power DCO Using Interlaced Hysteresis Delay Cells

A Low-Power DCO Using Interlaced Hysteresis Delay Cells

... In this brief, a DCO using the interlaced hysteresis delay cells (IHDCs) is proposed to achieve a large delay and low power in a small area. The IHDC interlaces the signal transitions in two series ... See full document

5

A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle

A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle

... of delay stages must be increased to let the maximum delay of the delay line equal to the period of the lowest ...minimum delay of the delay ... See full document

3

Modified TMN8 Rate Control for Low-Delay Video Communications

Modified TMN8 Rate Control for Low-Delay Video Communications

... In low rate video coding standards such as ...is low complex and the current MB is high, the previous QP (denoted as QP prev ) will be small, so the current MB will be quantized too finely because its QP is ... See full document

9

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