[PDF] Top 20 Low power 2D DCT chip design for wireless multimedia terminals
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Low power 2D DCT chip design for wireless multimedia terminals
... !jince these standards recently apply to battery-operated systems like portable computers (Notebook), personal digital assistants (PDA) and wireless communication equipmen[r] ... See full document
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Design and implementation of low-power DCT chip for portable multimedia terminals
... The chip architecture based on direct 2-D approach reduces computational complexity and the power dissipation can be reduced accordingly.. In the implementation of the[r] ... See full document
9
A symbol-rate timing synchronization method for low power wireless OFDM systems
... test chip in ...reduce power consumption by preventing high-rate circuit opera- ...has low design complexity with the low power feature, making it very suitable for ... See full document
5
A single-chip low-power tunable CMOS low-IF single-conversion ISM receiver
... principal design trade-off in heterodyne receiver ...systems for many ...need for a large number of external components ...single design to different wireless standards and ...optimized ... See full document
4
A low power 2D DCT chip design using direct 2D algorithm
... In addition to the considerations in algorithm and ar- chitecture level, low power design methdologies in logic- style and circuit level are applied t o the real circuit im[r] ... See full document
6
Low power design for MPEG-2 video decoder
... A bus arbitration and scheduling scheme is then proposed to allow larger burst of I/O transfer with less buffer size penalty than the fixed-priority approach Both the Gray[r] ... See full document
9
Task scheduling method for low power dissipation in a system chip
... The processing element (PE3) processes tasks (T7~T8) The poWer state of the processing element (PE3) changes from sleep to loW and then back to sleep. In sum, in a complicated system c[r] ... See full document
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A new design and implementation of 8×8 2-D DCT/IDCT
... The plots of overall mean square error versus internal wordlength with different coefficient wordlengths are shown in Fig.. The horizontal dashed line is the upper bound[r] ... See full document
10
A 2.4 to 5.4 GHz low power CMOS reconfigurable LNA for multistandard wireless receiver
... externally for test ...reconfigurable for variable gain and output ...and low gain (LG) modes. For larger gain stepping the switching transistor configuration is used for M 2 ... See full document
4
A low-power CMOS LNA for ultra-wideband wireless receivers
... Department of Communication Engineering, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu 300, Taiwan a) yiching.cm94g@nctu.edu.tw Abstract: In this paper, a low-power ultra- wideband (UWB) ... See full document
6
Power-efficient FIR filter architecture design for wireless embedded system
... disadvantage is that the structural symmetry in the linear-phase frequency response can not be applied to transposed form filters designs. In this paper, we provide a solution to the problems de- scribed above by ... See full document
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A low-power design for Reed-Solomon decoders
... large power consump- tion, leading to difficulty in system-level ...a low-power design for RS decoders using a novel two-stage syndrome calculator, which is addressed in ...Sec. 2, ... See full document
12
General splitting and merging of 2-D DCT in the DCT domain
... The algorithmic-level computational complexity of the proposed algorithm is lower than the direct approach and the programming-level analysis tells us that the proposed approach[r] ... See full document
4
New CMOS 2V low-power IF fully differential Rm-C bandpass amplifier for RF wireless receivers
... In this design, the Rm amplifier is realised by a simple inverter with tunable shunt-shunt feedback MOS resistor and tunable negative resistance realised by crosscoupled MOS [r] ... See full document
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Design of a power-spectrum-based ATM connection admission controller for multimedia communications
... a power-spectrum-indexed table for managing multimedia call requests, where traffic characteristics of call re- quests are described by the power ...The power spectrum can be obtained ... See full document
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The design of an efficient traffic scheduler with fair bandwidth-sharing for wireless multimedia services
... NRT traffic; 3) shared utilization of the residual bandwidth for both RT and NRT traffic streams, but also provides flexiblc de- lay/jit,ter controls for RT Traffic str[r] ... See full document
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Low power full-search block-matching motion estimation chip for H.263+
... By the properly design for the PE cell, this architecture can fit variable block size and searching range requirement in a signal chip and still consumes less power. This [r] ... See full document
4
Design and Simulation of a Low Power Rake Receiver for Indoor Communication
... • [2] NSC_BIST 子計畫六 • [3]Ahmed M. Eltawil and Babak Daneshrad, “A Low-Power DS-CDMA RAKE Receiver Utilizing Resource Allocation Techniques”, IEEE JSSC, vol. 39, Aug. 2004. • [4]Chi-Min Li and ... See full document
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Low Power Consumption Design of Micro-machined Thermal Sensor for Portable Spirometer
... model for a micromachined thermal sensor was presented for the calculation of temperature distribu- tion and ...geometry for each membrane size of the manufac- tured sensors is chosen around the ... See full document
6
Design of Analog Pixel Memory for Low Power Application in TFT-LCDs
... quality design for microelectronic circuits and ...quality design for integrated circuits by hundreds of design houses and semiconductor companies in the worldwide IC ...quality ... See full document
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