[PDF] Top 20 A low power scheduling method using dual V/sub dd/ and dual V/sub th/
Has 10000 "A low power scheduling method using dual V/sub dd/ and dual V/sub th/" found on our website. Below are the top 20 most common "A low power scheduling method using dual V/sub dd/ and dual V/sub th/".
A low power scheduling method using dual V/sub dd/ and dual V/sub th/
... Individual and Chromosome Representation A suitable chromosome representation is needed to repre- sent the individual in the GASA scheduling algorithm, since it affects the running time of the ... See full document
4
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices
... dynamic power is larger than the nominal MOSFET-based circuits, hence would have larger EDP (energy-delay ...EDP and Standby power in NAND, inverter chains and Clocked-CMOS Latch com- pared ... See full document
9
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture
... VLSI A RCHITECTURE OF P ROPOSED H ETEROGENEOUS D UAL -PE DF-ECC P ROCESSOR ...with a standard AMBA AHB bus interface. Because of the RL binary method implementation of ECSM, the key value is saved in ... See full document
13
Low-Power Sub-Harmonic Direct-Conversion Receiver With Tunable RF LNA and Wideband LO Generator at U-NII Bands
... with a modified - attenuation method of both load and emitter attenuators while V-NPN BJTs are employed at the transconductance ...Amplifier V-NPN BJTs are also used at the input stage ... See full document
12
1.2V sub-nanoampere A/D converter
... 1.2 V sub-nanoampere A=D converter ...at sub-nanoampere (nA) levels, which present a challenge for digital data ...is a MOS current-mode analogue-to-digital converter with ... See full document
2
Sub-I V CMOS large capacitive-load driver circuit using direct bootstrap technique for ' low-voltage CMOS VLSI
... For a supply voltage of 1 V, the CMOS large capacitive-load driver circuit using the direct bootstrap technique shows a 3.3 times improve- ment in switching speed in dri[r] ... See full document
2
Low Power Mapping and Pipelined Scheduling Using Tabu Search
... Multimedia and wireless devices typically have intensive computations and an endless stream of input data with throughput ...for low-power and high- performance is greatly ...between ... See full document
6
A low-power dual-mode video decoder for mobile applications
... is power reduc- ...complexity and com- puting power become the key design challenges for real-time and battery-operated ...consider a newly standardized ...the power dissipa- ... See full document
8
Task scheduling method for low power dissipation in a system chip
... The processing element (PE3) processes tasks (T7~T8) The poWer state of the processing element (PE3) changes from sleep to loW and then back to sleep. In sum, in a complicated system c[r] ... See full document
10
A dual CP slot antenna using a modified Wilkinson power divider configuration
... Abstract—A dual circularly polarized (CP) slot antenna based on a proposed equal-split Wilkinson power divider is ...analyzed using the method of moments together with a ... See full document
3
A low power 5Gb/s transimpedance amplifier with dual feedback technique
... In order to eliminate this effect on core amplifier's bandwidth, a second shunt-shunt feedback network is incorporated in the output of the core amplifier.. The transi[r] ... See full document
4
A new dual-type method used in solving optimal power flow problems
... These results show that the Jacobi-type method associated with the proposed dual-type method are still very efficient in solving OP F problems with system losses crit[r] ... See full document
9
5 mm high-power-density dual-delta-doped power HEMT's for 3 V L-band applications
... The high output power was achieved by small gate periphery at low operation voltage.. The developed HEMT eliminates the problems of large periphery while having t[r] ... See full document
3
V-Plasty technique using dual synthetic vascular grafts to reconstruct outflow channel in living donor liver transplantation
... infection and thrombosis are the concerns that have precluded many transplant surgeons from using ePTFE ...resistance and patency compared with ePTFE grafts because a large percentage of ... See full document
14
A genetic algorithm for scheduling dual flow shops
... ratios and three transportation time ratio options mentioned ...proposed dual-flow shop algorithm (GA-EDD-C) outperforms the three other algo- rithms (GA-EDD-S, GA-FIFO-C and GA-FIFO-S) in most ... See full document
9
Sub-1 V Input Single-Inductor Dual-Output (SIDO) DC-DC Converter With Adaptive Load-Tracking Control (ALTC) for Single-Cell-Powered Systems
... Circuit and the Current Sensor As shown in ...circuit and current ...11, and the sensing resistor R SEN is set to ...reduce power consumption. A large resistor R S , which is N times ... See full document
12
A Design of 2.6 GHz Auto-Biasing Cascode Class-E PA with V(dd)/AM and V(dd)/PM Compensations in EER System
... Circuit and Cascode Class-E PA ...voltage V co , so that this voltage can equal the envelope voltage V dd plus a half of the voltage V c ...as V dd variations, the ... See full document
4
New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation
... base, and collector of the parasitic vertical n-p-n BJT are real- ized by the n diffusion, p-well, and deep n-well layers, respec- ...currents, and , which are formed by two bandgap voltage ...from ... See full document
5
Fabrication of trench-gate power MOSFETs by using a dual doped body region
... trench-gate power MOSFETs by using a dual doped body region has been proposed to further improve the device ...employs a uniform doped body region, a device with a ... See full document
7
Model based Sub-Resolution Assist Features Using an Inverse Lithography Method
... maintain a segment-based OPC while achieving some of the optimized corrections produced by ILT, we propose a model-based pre-OPC flow where the sizing of drawn patterns and placement of surrounding ... See full document
11
相關主題