Top PDF Modified Hysteretic Current Control (MHCC) for Improving Transient Response of Boost Converter

Fig. 18. Waveforms in conventional boost converter with HCC technique (a) when load current changes from 70 mA to 270 mA within 2 s and (b) when load current changes from 270 to 70 mA within 2 s. The fast transient performance can be easily noted because the MHCC technique can speed up the transient response over a wide load current range, as shown in Fig. 20. The load cur- rent step decreases to approximately 100 and 50 mA, as shown in Figs. 20(a) and (b), respectively. The transient response time has only a slight improvement compared with that of the large load current step because the ACC technique has only a min- imal effect on the whole system. Fortunately, the ACC technique consumes little power because it works only when the output voltage varies significantly. The power conversion efficiency is illustrated in Fig. 21. The power conversion efficiency is hardly influenced with or without the ACC technique. The power con- sumption overhead is merely 1%. The maximum power conver- sion efficiency is approximately 90%. A summary of the com- pared performances between the conventional and the proposed MHCC techniques is listed in Table IV.

To show the effective current balance contributed by the TMCB technique, the two inductors, L 1 and L 2 , were set to 0.47 and 1.2 μH, respectively. The mismatch between the two inductors was about 153%. The TMCB technique was switched ON to start the current balance between the two phases, as shown in Fig. 21. Finally, the two phases can drive the same current to the output even there was a large mismatch between the two inductors. Table IV shows the specifications of the pro- posed converter, and Table V shows the comparison between the proposed and the conventional boost converters. The proposed boost converter has a better transient response than the conven- tional converter due to a higher frequency RHP zero. Moreover, the compensator can be modified to have a larger bandwidth.

With the development of integrated circuit technology, switching power supplies have been widely used in many applications because of smaller size, lighter weight and higher efficiency. Among various kinds of electronic equipment, the power supplies for digital IC’s, such as microprocessors, must have a good dynamic performance for input voltage and the large load current change with high slew rate [1]-[3]. For the digital IC’s that have a current rating of under 15A, a hysteretic PWM controlled buck converter is widely used such as a POL converter since it has the advantage of fast transient response for large load transient [4],[5] and the capability of higher switching frequency. However, for higher current rating than 15A, it is necessary to employ multi-phase converter, and it is necessary to adopt a new control method synchronized with a clock signal.

Abstract— This paper proposes a current-mode synthetic con- trol (CSC) technique for the design of boost converters to over- come the difficulty in designing a current-ripple hysteresis boost converter and to maintain high conversion efficiency over a wide load range. The CSC technique has a high accuracy because of the additional voltage path through the error amplifier. A smooth load transient response is maintained when the operation transits from continuous conduction mode with a nearly constant switch- ing frequency to discontinuous conduction mode with a load- dependent switching frequency. Generally, ripple performance, light-load efficiency, and switching frequency are traded off in the design of hysteresis control regulator. In this paper, a balance among the load-dependent switching frequencies at light loads results in high power conversion efficiency compared with conventional pulsewidth modulation converter and attains compact ripple performance. The experimental results show that the output voltage ripple can be kept < 50 mV over a wide load current range from 10 to 400 mA, where as power conversion efficiency is maintained at 78% at a load current of 10 mA when the switching frequency is decreased from 5 to 2 MHz.

II. O PERATION P RINCIPLE The structure of the buck converter with proposed fast transient hysteresis control is shown in Fig. 2. The V ref and V fb are fed to the error amplifier which generates an error voltage V LB to reflect the output voltage V out variation immediately. The ripple signal V ripple , is generated by the synthetic ripple modulator with a hysteretic band confined by V LB and V HB . The lower limit of the hysteretic band V LB is stacked with a variable positive voltage V hys which is generated from hysteretic band modulator to define the higher band limit V HB . V ripple , V LB and V HB are then sent into a hysteresis comparator. The hysteresis comparator output signal is sent to the fixed dead-time buffer to generate a pair of non-overlapping gated signals, the signal is strengthened by digital driver block to increase the driving ability for power MOSFETs. A soft-start circuit is added to prevent the large inrush current damage during the start-up transient response.

Yean-Kuo Luo, Chao-Chang Chiou, Chun-Hsien Wu, Ke-Horng Chen, Senior Member, IEEE, and Wei-Chou Hsu Abstract—In this paper, a current mode boost converter using window transient enhancement (WTE) and overshoot suppression (OSS) technique is presented for digital still camera (DSC) appli- cations. The peak-to-peak transient overshoot voltage demand of a DSC motor driver is generally within 4%–5% of the regulated value. However, conventional boost converters usually fail to pass this criterion during large load transient. The OSS technique re- duces the overshoot voltage when load current changes from heavy to very light. Experimental results show that compared with the use of a conventional current mode boost converter, the use of the technique reduces drop voltage about 62% and overshoot voltage about 51% when the load current has a load step of 400 mA. More- over, the settling time improves to 43%, which is better than in the conventional case of a 400 mA load current step. The overhead of the silicon area is about 4.5% to achieve the overshoot reduction.

V. C ONCLUSION A buck–boost converter with a new control scheme was intro- duced in this paper. Several advantages include reduced switch- ing losses through the use of only half the number of switches during each cycle and decreased conduction losses of power switches due to the RAIC technique. The efficiency is effec- tively improved. A new mode detector can select proper oper- ating mode to get a regulated output and thus enhanced control accuracy are guaranteed during mode transition. Besides, the HBBFF technique is integrated in this converter to minimize the voltage variation at the output of error amplifier. As a result, a fast line transient response can be achieved with small dropout voltage at the output. Experimental results show that the output voltage is regulated during the whole battery life, and the out- put transition is very smooth during the mode transition by the proposed control scheme. The peak efficiency is 97% and the transient dropout voltage can be improved substantially.

Fabricated in a 0.18μm CMOS process with an active area of 1.8mm 2 , this chip has the smallest undershoot/overshoot voltage with 2.2× faster settling speed and achieves 6× faster cali[r]

A. Sinusoidal Input Voltage The sinusoidal input voltage is provided by the instrument of ac power source. Fig. 5 shows the experimental results for various output power where the average duty ratio ¯ d, the con- trol signals v cont0 , and Δv cont for 400 W are also plotted for comparison. When the input voltage is near zero, the average duty ratio is 100% in order to keep the switch conducting within several switching period. As the input voltage increases, the average duty ratio decreases. After the input voltage turns to decrease from its peak value, the average duty ratio increases from its minimum value.

Single-Loop Current Sensorless Control for Single-Phase Boost-Type SMR Hung-Chi Chen, Member, IEEE Abstract—In this paper, the first single-loop current sensorless control (SLCSC) in continuous current mode (CCM) for single- phase boost-type switching-mode rectifiers (SMRs) is developed and digitally implemented in a DSP-based system. Compared to the conventional multiloop control with one inner current loop and one outer voltage loop, there is only one voltage loop in the proposed SLCSC, where the voltage loop’s output is used to shift the nominal duty ratio pattern generated from the sensed input and output voltages. Because of no current loop, the efforts of sampling and tracking inductor current can be saved. It implies that the proposed SLCSC is simple and very adaptable to the implementation with mixed-signal ICs. First, the effects of shifting nominal duty ratio pattern on the input current waveform are analyzed and modeled by considering the inductor resistance and conduction voltages.

Fig. 4. Timing diagram of the proposed converter encounter cross regulation due to load change in V O1 . B. Cross Regulation The outputs of the SIMO DC-DC converter control by time- multiplexing power-distributive approaches will cross regulate among themselves, no matter in DCM or in CCM, because they are coupled together and influenced the duty cycles mutually. Our proposed converter can maintain desirable low cross-regulation which is explained in Fig. 4. Suppose that the load current suddenly increases in V O1 , which makes V O1 drop below the predetermined voltage. While detecting that, the comparator loop increases the duration, △D 1 T, to deliver more energy of inductor current to V O1 until V O1 is larger than its required voltage. Then, due to increasing external energy abruptly in V O1 , remainder energy of inductor current delivered to V O2 is decreased so that V O2 drops. In other words, the output error of the comparator-controlled V O1 is transferred and accumulated to V O2 . Receiving the voltage error of V O2 , PWM generator of the compensation loop extends the duty DT to get more energy from the inductor. At the same time, D 1 T is reduced by the comparator to maintain V O1 . Finally, V O1 and V O2 return their required voltages levels, and the proposed converter achieved low cross-regulation by

Index Terms— H-bridge, Synchronous Buck-Boost Converter, Feedforward Control I. I NTRODUCTION With recent progress of large-scale integrated circuits, various kinds of portable devices powered by batteries have widely spread in consumer electronics. In order to enable longer operation of such portable devices, it is preferable to use the battery at the lowest possible supply voltage. The terminal voltage of the battery varies considerably depending on the state of its charging condition. For example, a single Li-ion battery is fully charged to 4.2 V but it drops to 2.4 V before fully discharged. Therefore electronic circuits in the portable devices require a power converter both step-down and step-up functions. A conventional inverting buck-boost converter has such a capability with single switch and diode, but the polarity of the output voltage is opposite to the input.

B. Adaptive Voltage Loop Compensator In the design of a loop compensator for a high bandwidth switching regulator we need take careful considerations in determination of gain crossover frequency and compensation of the resonant peak inherent in the output LC filter. The resonant peak of a switching regulator becomes more spiky at light load and more flat as load becomes heavy. Conventional approach is employing current-mode control to ensure robust response under large lard load disturbances. However, this approach needs complicated control circuit and still requires proper phase compensation to ensure a guaranteed phase margin for large load variations. Voltage-mode control with matched load compensation emerges as a competitive solution for dedicated applications due to its simplicity and fast dynamic response. However, this approach still requires a careful design of the voltage loop compensator. Fig. 4 shows the block diagram of voltage-mode control loop of a switching regulator. In order to ease the applications of switching regulators for more versatile applications without the need of loop compensator design, we need to develop an adaptive controller to accommodate various loading conditions and to eliminate the compensation circuit to simplify the circuit implementation. This papers proposes a simple analog circuit oriented adaptive control scheme by tuning the control loop gain with a nonlinear function of the measured average inductor current.

An application of the zero-ripple technique to converter struc- ture is described in [8]. In this paper, the zero-ripple technique is applied to the proposed push–pull converter. For basic consider- ation, it seems to be perfect that only by extending a basic con- verter structure by a defined magnetic coupling of the input and filter inductors can a complete elimination of the input current ripple be obtained. It is shown that the ripple suppression can be achieved only on the input side or on the output side. A cir- cuit consisting of passive elements cannot have an infinite high effective input inductance for all frequencies. The impossibility of a complete suppression of the input current ripple of the con- verter becomes clearly understandable. Therefore, the system should be labeled better low-ripple boost converter and not zero- ripple boost converter. In addition, coupled inductor techniques supply a method to reduce the converter size and weight and to achieve ripple-free current. In order to improve efficiency and reduce size, this paper proposes an improved push–pull boost converter with integrated magnetics. In this structure, all the magnetic components including input inductor, input filter in- ductor, and step-down transformer are integrated into a single EI core. The proposed integrated magnetic structure has a simple core structure, a small leakage inductance and low core losses.

The gain of the PWM comparator K =0.25 In general, the nominal output voltage of the designed DC/DC converter and output voltage regulation specification is 12.2V and ± 3% tolerance, respectively. Let droop voltage V droop be 5V at full load current operation condition. Therefore, the design margin is set as 1% of the nominal voltage. In according to the steady state droop voltage design procedures, let V refi and k be 2.5V and 1, respectively, and then from (1) to (3), one can find the parameters of the feedback weighted voltage network R 1 , R 2 and R 3 are 2.563k Ω , 9.94k Ω and 101.844k Ω , respectively. But, it is very hard to find the designed resistance in the commercial part list. Therefore, the parameters of the resistors R 1 , R 2 and R 3 are chosen as 2.56k Ω , 10k Ω and 100k Ω with 5% tolerance as an alternative selection. Fig. 6 shows the steady state droop voltage characteristics of the output voltage with respect to different load currents. It shows the output voltage of the designed DC/DC converters can follow the designed droop voltage characteristics with a smaller error. The results were demonstrated the effectiveness of the proposed designed proced ures. Once the stead y state dro op vo ltage characteristics have been determined, the control system design and analysis of the paralleled DC/DC converter was carried out subsequently. Accordingly, one can obtain the equivalent secondary voltage V g of the IDSFC is 19V.

Its salient features are as follows: (i) soft switching operation can be eusily maintained for a wide line and load range; (ii) there are low switching stress and commutatio[r]

3. THE MODIFIED H 2 FEEDFORWARD ANC ALGORITHM As presented earlier, the H 2 and H a methods effectively solve the model matching problem, even if the NMP problem of the plant is present. However, this masks somewhat a pitfall of the above methods. More precisely, excessive compensation for the NMP zeros by using the H 2 and H a methods will generally result in unnecessary high gains at high frequencies. The fact that the NMP zeros cluster at high frequencies is common for physical systems with flexibility [7], but other than that, it is more often than not the consequence of discretization of analog plants [8]. Compensation for these artificially generated NMP zeros is sometimes not worth the effort because the uncertainty of the NMP zeros obtained by experimental system identification methods is generally large at the plant zeros, where the plant output is extremely small. The NMP zeros impose inherent design constraints on the controller, wherein high-gains at high frequencies become inevitable. In practical implementation of the ANC controller, the effect of high-gains at high frequencies is very detrimental since they will saturate the actuator and one should avoid them whenever possible.

controller is adopted to control the inductor current in the CCM. The digital current controller is implemented on FPGA. A. Block Diagram and Timing Chart of Controller Fig. 7 shows the block diagram of the current controller and Fig. 8 shows the timing chart. The frequency of the main clock CLK is 25 MHz. The switching frequency of the converter is obtained by counting the CLK to 511 (=2 9 -1) and then the frequency becomes 48.8 kHz. The inductor current AD_DATA is measured as a voltage across a shunt resistor through a 2.5MHz A/D converter. A commanded value of the peak inductor current CMD_DATA is calculated in DSP and the commanded current is send as 12 bit data from DSP to FPGA through a parallel port. To achieve the external ramp in FPGA, a down counter is added to the controller. The down counter counts from the commanded current CMD during one switching term. A comparator compares the output from the down counter CM to the inductor current AD. When AD is more than the output CM, the comparator outputs 1. In the conventional converter, the switch is turned off when the output of the comparator is changed. However, in the proposed ZCT converter, the aux switch must be turned on before the main switch is turned off as explained in section II. A Johnson counter and a SR flip flop are used for the switches to achieve the ZCT.

The arrival stream forms a Poisson process in which the number o f customers in each arriving unit is a random variable X, with probability density Cx.. Service rate is switch[r]

II. N -P HASE B OOST -T YPE SMR Fig. 1 shows the topology of an N -phase boost-type SMR, where integer N is the topology phase number (N > 1). It consists of a diode bridge rectifier, N boost converters with the identical inductors L, and the identical diodes D. It is noted that, in the digital control of the power electronic system, the turn-on time t on is given before the beginning of each switching period T s . Thus, by the GSD, all the gate signals G S1 , G S2 , . . . , G SN corresponding to the controllable switches S 1 , S 2 , . . . , S N are generated from the same turn-on time signal t on .