Top PDF A 0.09 mu W Low Power Front-End Biopotential Amplifier for Biosignal Recording

V. C ONCLUSION A low power front-end biopotential amplifier IC that can be adopted in biosignal recording is implemented. The MOS tran- sistors in the proposed IC are operating in subthreshold region to reduce the system power. Chopping technique is applied to remove the flicker noise in the MOS circuit into the high fre- quency band. A Gm-C filter is utilized to detect and cancel out the differential interference that was generated by imbalance of the electrodes impedance. AC-coupling with capacitive feed- back gives the IA a high CMRR and high input impedance.

In this paper, a new CMOS current-mode front-end amplifier (CMFEA) for neural signal recording is proposed. In the pro- posed CMFEA, both bandwidth and current gain are all tunable for different neural signals. Through an active feedback loop incorporated with the first-stage current-mode preamplifier, the high-pass cutoff frequency can achieve 0.3 Hz and the dc offset current caused by electrode-tissue interface can be bypassed. No reset signal or ultra-high value pseudo resistor is needed in the CMFEA. The measured input referred current noise density is 153 with the bandwidth up to 10 kHz. The power dis- sipation is 13 at 1-V power supply. The proposed CMFEA is also applied to the animal test successfully to measure the epileptic ECoG of rats. The experimental results have demon- strated that the CMFEA is a promising solution for designing low-noise and low-power neural recording amplifiers.

ABSTRACT A high input impedance, high common mode rejection ratio, fixed gain ( 100) amplifier is proposed for recording biopotential signals. This miniature amplifier affords the feature of power saving. It can continuously function for as long as 3 months with a small battery (3.3 V, 2.2 g). A practical application of this amplifier for ECG recording has shown that it has great potential for recording other biomedical signals. Hence, this amplifier can be used as a building block at the front end of most biomedical systems. Detailed design considerations and circuit implementation of this amplifier are described to facilitate its acceptance as a common module for this purpose.

Abstract—This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabri- cated in a low-cost 0.35- m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed opera- tions in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 A rms . The input sensitivity of the receiver front-end is 16 A for 2.5-Gbps operation with bit-error rate less than 10 12 , and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 m 1500 m.

The front-end circuits for UWB are designed using 0.18μm CMOS technology. The receiving blocks have been integrated and simulated using SpectreRF. Fig. 8 shows the post-layout simulation results of the wideband amplifier frequency response. The gain achieves 69dB for the bandwidth from 30MHz to 1.2GHz. Besides, it has linear phase response in the band of interest. Fig. 9 shows the post-layout simulation results of the 1-bit ADC with the input threshold of 100mV. When the input pulse is amplified to above 100mV, the ADC acquires the correct data and outputs the digital signals in 1 bit. Under different process corners and temperature conditions, the 1-bit ADCs can operate correctly to digitize the input pulses. Fig. 10 shows the 8 phases of 250MHz clocks from the designed timing generator. For different process corners from the foundry models, the timing signals provide stable and precise timing information. The total power consumption for the whole chip is 15mW with 1.8V power supply.

degraded, the finished antenna front-end module still works well on the large PCB. IV. C ONCLUSION In this paper, a compact RF front-end module using LTCC multilayer technology has been designed and realized. The module includes a BPF, an LPF, a DPDT bare die switch, and an embedded inverted-F antenna, and has a very small size of 6.2 mm 5.4 mm 0.98 mm. The effect of the bond wire has been taken into account by incorporating into the design of the filters. Both the proposed filters possess transmission zeros at out band for suppressing unwanted signals. The performances of the developed antenna front-end module on two PCBs with different sizes (55 mm 20 mm and 80 mm 46 mm) have been demonstrated. The measured radiation patterns are om- nidirectional. The return-loss bandwidth and antenna gain are enough and suitable for the IEEE 802.11a application. In the future, more circuit components, such as the power amplifier, low-noise amplifier, and RF transceiver can be integrated to the LTCC module. Dual-band components (bandpass filter, antenna, and balun) can also be designed in to achieve a com- plete RF front-end module for the IEEE 802.11 a/b/g WLAN applications.

Abstract—In this study, a low-power and low-voltage 5.5-GHz receiver front-end circuit is designed using a resonator coupling technique. An on-chip transformer combined with the parasitic capacitances from a low-noise amplifier (LNA), a mixer, and the transformer itself comprises two coupled resonators of the resonator coupling network (RCN). The RCN functions as a balun, and couples energy from the LNA to the mixer. Under the critical coupling condition, the RCN gives a maximal current gain at resonance frequencies, equivalent to the same level by an ideal transformer. The analysis shows that the current gain is quite tolerable to the coupling coefficient variation, an advantageous feature for on-chip transformer design. The technique is verified by the receiver front-end in 0.18- m CMOS technology. The RCN possess a current gain as high as 12 dB at 5.5 GHz. The measured input return loss, conversion gain, and third-order intermod- ulation intercept point of the entire circuit are 16 dB, 17.4 dB, and 1.5 dBm, respectively. The noise figure is 7.8 dB at the IF frequency of 1 MHz. The power consumption is only 0.33 mW from a 0.6-V supply. The required local oscillator power is only 9.5 dBm. This receiver front-end successfully demonstrates the resonator coupling technique.

SUMMARY A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output bu ffer, and an SFT. A fully differential SFT is introduced to relax the re- quirements on the design of the frequency synthesizer. Thus, the opera- tional frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input- referred 1-dB compression point of −20 dBm and the input third order inter-modulation intercept point of −8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm × 0.794 mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.

III. T HE C RYOGENIC L OW N OISE A MPLIFIER The NF of HEMTs reduces and the gain of HEMTs increases as the temperature becomes lower. Both are beneficial to low noise amplifier, except higher gain is possible to induce un- wanted oscillation. Because the modern HEMT devices have very good gain, the most important thing in cryogenic LNA design is to avoid the unwanted oscillation. The photo of LNA is shown in Fig. 3. The LNA are self-biased with single power supply. The chocks in LNA comprise a quarter wavelength high impendence transmission line, a bypassing capacitor, and a stability resistor. Two Lange couplers are located at input and output of each LNA stage. The Lange coupler keeps the return loss of LNA good, so that each individual HEMT could be matched close to its optimal NF impedance.

However, it increases the complexity of circuit imple- mentation. Reducing the quality factor of a loaded RLC tank is another means to extend bandwidth. Although a loaded RLC tank may have wide bandwidth and small gain variation, however, the resistive loss can cause reduced voltage gain of the entire circuit, which in turn raises the power consumption to achieve an adequate gain. An alternative solution uses inductor peaking techniques in the output of a traditional cascode topology [6–10], which allow higher speeds. In this paper, an inter-stage resonant network is proposed to incorporate in the cascode amplifier to meet a broadband specification. The resonant cascode amplifier forms an RLC tank at higher operational fre- quencies to boost high frequency gain. Furthermore, the topology exhibits a conventional cascode amplifier at rel- atively low frequencies. Consequently, the combination of high and low frequency responses achieves a wideband amplifier design.

the techcians should prepare the surface of shn,degrease the recording area by cleaning it with alcohol, then apply the conducting paste to Ag/AgCl electrodes with collo[r]

From equation 1, the added zero from the feedback inductor can reduce the parasitic effect between the TIA and limiting amplifier. The value of inductor is chosen such that it provides enough gain peaking and does not create a large phase distortion for the received data. The single ended output is converted to differential ones by a wide band buffer and the DC extracting RC network is implemented by the MOS in deep n-well. The RC network must maintain similar behavior under the system dynamic range. The transimpedance gain is 56 dBȍ under 0.5 pF photodiode capacitor, and bandwidth is about 0.7 times data rate. The overall power dissipation under 1.8 V power supply is 10 mW.

This may become a critical issue, in terms of installation space and potential resonance of the passive filter. This paper proposes a hybrid active front-end converter and its power flow control method. The hybrid converter is composed of a capacitor and a voltage source converter in series connection. Bidirectional real power of the converter can be controlled by the output voltage vector perpendicular to the grid voltage, and reactive power delivery of the converter for grid voltage regulation can be determined by the output voltage vector parallel to the grid voltage. Due to series connection capacitor, the converter can be operated between a low-voltage dc side and high-voltage grid side without any low-frequency transformer, which is the significant advantage of the proposed method. A harmonic resistance is also emulated in the proposed method to assure stable operation of the converter for unintentional voltage spike coming from the power system. Operation principles are explained in detail, and computer simulations and experimental results are provided to validate the effectiveness of the proposed approach.

III. S IMULATION R ESULTS OF R ECEIVER The 60-GHz receiver front-end is designed and simulated using 0.13-um 1P8M Cu CMOS technology with ultra thick 3.3-um metal. The chip is under fabrication and chip layout is depicted in Fig.5, with a total die area of only 0.63 mm 2 including all test pads and dummy metal. In order to avoid any coupling effects, the space between the T-lines are more than three-times that of the metal width. All of the T-lines characteristics are simulated using an EM simulator, Ansoft HFSS. The circuit simulation uses Agilent Advanced Design System (ADS) software. The circuit is biased at a 1.2-V supply voltage with current consumption of 4.7, 0.6, and 6.5 mA for the LNA, mixer, and frequency tripler respectively.

Abstract: A 5.8 GHz transmitter front-end comprising a quadrature modulator, a variable gain amplifier and an on-chip output balun in CMOS 0.18-um technology is presented. The quadrature modulator adopts cross-coupled type micro-mixer, and the measured 3 rd -oder rejection is 32 dB under input voltage swing of 250 mVpp. With four-bit control words, a 16-step linear-in-dB output power is realized to achieve a dynamic range of 27 dB. A single-ended type output is accomplished by an on-chip 3:1 transformer and the output matching network is therefore simplified.

This paper describes the design of a 10-Gb/s optical receiver analog front-end in a generic 0.18- m CMOS technology. The optical AFE provides a conversion gain of 90 dB and a 3 dB bandwidth of about 7.86 GHz, which is limited by the transimpedance amplifier. A regulated cascode input stage is utilized to decouple the loading effect at the input node, and wide bandwidth is achieved by means of shunt feedback and inductive peaking. The PA is composed of a preamplification stage followed by a slicing stage. In contrast to a conventional limiting amplifier which consists of identical gain cells, the GBW requirements in the proposed topology are much relaxed, thus, both peaking inductors and power consumption can be saved. Moreover, an AGC is built in to alleviate overload induced data jitter. Instead of using bulky planar inductors or two asymmertric 3-D inductors, a novel fully symmetric 3-D transformer for inductive peaking is utilized in this design to save chip area. A distributed capacitance model of the 3-D transformer is also proposed. The superiority of the proposed transformer over conventional planar counterpart is demonstrated.

power analysis, critical blocks are identified and redesigned so as to further reduce the power consumption. The final design shows that the power is reduced by 51% from the original design of 133.6 mW to 65.49 mW, and its core area is also reduced by 31.9% from 3 4 3 4 mm 2 to 2 8 2 8 mm 2 . The design is implemented and verified in a 3.3-V 0.35- m CMOS technology with clock rate 15.36 MHz.

The simulated and measured radiation patterns at 4, 6, and 8 GHz for the structure for which Vivaldi 1 is the active element are given in Figures 3–5, respectively. The E-plane of this antenna is x–y plane and the H-plane is x–z plane. The measured results in azimuth plane agree well with the simulation and show good radiation pattern with half-power beamwidth (HPBW) as broad as 90° over the entire band. That is, the antenna composed of four direction parts can cover all the 360° of the horizontal plane. The directivity of the antenna is about 6 dB. The front to back ratio reaches more than 10 dB. The radiation pattern is isotropic in the azimuth plane for the symmetrical structure of the antenna, thus high front to back ratio sector beam can be obtained in the other three directions through changing the status of the switches.

A two-stage high-linearity low-voltage low-noise amplifier topology using low-cost 0.35-pm CMOS process has been demonstrated. The measurement results prove that the proposed [r]

Low-power VCO with phase-noise improvement in 0.18 mm CMOS technology C.-P. Liang, T.-J. Huang, P.-Z. Rao and S.-J. Chung A low-power 5.25 GHz voltage-controlled oscillator (VCO) with phase-noise improvement is designed in a 0.18 mm CMOS 1P6M process. Owing to the use of a larger value of parallel capacitor, an additional harmonic-suppressed capacitor, and an appropriate bulk bias voltage of transistor, a good figure of merit of 2190 dBc/Hz can be achieved without extra chip area and CMOS process steps.