第七章、 附錄
7.2 各別元件比較
使用於電壓源 DC1.8V 與+-AC1.8V
INV1 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA OUT
GND VDD
INA OUT
GND
總功率消耗=1.001uW 總功率消耗= 0.920uW
改良後 INV 之 layout 圖
AND2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA
INA
INB
GND
GND INB
OUT
VDD VDD
INA
INA
INB
GND
GND INB
OUT
VDD VDD
總功率消耗=1.374uW 總功率消耗= 1.158 uW
改良後 AND2 之 layout 圖
AND3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA
INA
INB GND
GND INB
OUT
VDD VDD
INC INC
INA INA
INB GND
GND INB
OUT
VDD VDD
INC INC
總功率消耗=1.123uW 總功率消耗=0.801 uW
改良後 AND3 之 layout 圖
OR2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA
INB
INA INB VDD
VDD
GND
GND
OUT INA
INB
INA INB
GND
GND OUT VDD
VDD
總功率消耗= 1.829uW 總功率消耗= 1.431uW
改良後 OR2 之 layout 圖
OR3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA
INB
INA INB
GND
GND OUT VDD
VDD INC
INC
INA
INB
INA INB
GND
GND OUT VDD
VDD INC
INC
總功率消耗= 1.343uW 總功率消耗= 1.148 uW
改良後 OR3 之 layout 圖
NAND2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA INB
INA
INB
OUT VDD
INA INB
INA
INB
OUT VDD
總功率消耗=1.262uW 總功率消耗= 1.048 uW
改良後 NAND2 之 layout 圖
NAND3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA INB
INA
INB
OUT VDD
INC
INC
INA INB INC
INA
INB INC
OUT VDD
總功率消耗= 0.939uW 總功率消耗= 0.785 uW
改良後 NAND3 之 layout 圖
NOR2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA
INB
INA INB
GND VDD
OUT
INA
INB
INA INB GND VDD
OUT
總功率消耗=
1.388uW總功率消耗=1.098 uW
改良後 NOR2 之 layout 圖
NOR3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA
INB
INA INB
GND VDD
INC
INC OUT
INA
INB
INA INB
GND VDD
INC
INC OUT
總功率消耗= 0.969uW 總功率消耗= 0.821 uW
改良後 NOR3 之 layout 圖
D-FF w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
Q
Q’
D
Clk
總功率消耗=16.58uW 總功率消耗=9.722 uW
改良後 D-FF 之 layout 圖
XOR2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
B’ B
A A’
VDD
GND
B B’
A A’
OUT
B’ B
A A’
VDD
GND
B B’
A A’
OUT
總功率消耗=6.702uW 總功率消耗=2.20 uW
改良後 XOR 之 layout 圖
AO12 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA
INB INC
OUT
VDD VDD
INA
INB
INA INB VDD
INB INC
OUT
VDD VDD
INA
INB
INA INB
GND
改良後 AO12 之 layout 圖
AOI12 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA
INB INC
OUT
INA
INB INC
OUT
總功率消耗=1.156uW 總功率消耗=0.7376uW
INA OUT
GND VDD
INA
INB
INA INB VDD
VDD VDD
INA
VDD VDD
INA
INB
INA INB GND
GND OUT VDD
VDD
INA OUT
GND
改良後 AOI12 layout 圖
OA12 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA
INB INC OUT
INA
INB
INA INB VDD
VDD VDD
INA
INB INC OUT
INA
INB
INA INB GND
VDD VDD
總功率消耗=1.521uW 總功率消耗=0.6966uW
改良後 OA12 之 layout 圖
OAI12 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 1.8V 改良後 AC 1.8V
INA
INB INC OUT
INA
INB
INA INB VDD
VDD VDD
INA OUT
GND VDD
INA
INB INC OUT
INA
INB
INA INB GND
VDD VDD
INA OUT
GND
總功率消耗=1.328uW 總功率消耗=0.7426uW
改良後 OAI 之 layout 圖 使用於電壓源 DC2.2V 與 AC（-2.2V～+2.2V）
INV1 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
INA OUT
GND VDD
INA OUT
GND
總功率消耗=1.562uW 總功率消耗= 1.41uW
改良後 INV 之 layout 圖
AND2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
INA
INA
INB GND
GND INB
OUT
VDD VDD
INA
INA
INB GND
GND INB
OUT
VDD VDD
總功率消耗= 2.100uW 總功率消耗= 1.811 uW
改良後 AND2 之 layout 圖
AND3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
INA
INA
INB
GND
GND INB
OUT
VDD VDD
INC INC
INA INA
INB GND
GND INB
OUT
VDD VDD
INC INC
總功率消耗= 1.695uW 總功率消耗= 1.253 uW
改良後 AND3 之 layout 圖
OR2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
INA
INB
INA INB VDD
VDD
GND
GND OUT
INA
INB
INA INB
GND
GND OUT VDD
VDD
總功率消耗= 2.818uW 總功率消耗= 2.203 uW
改良後 OR2 之 layout 圖
OR3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
INA
INB
INA INB GND
GND OUT VDD
VDD INC
INC
INA
INB
INA INB GND
GND OUT VDD
VDD INC
INC
總功率消耗= 2.046uW 總功率消耗= 1.772 uW
改良後 OR3 之 layout 圖
NAND2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
INA INB
INA
INB
OUT VDD
INA INB
INA
INB
OUT VDD
總功率消耗=1.994uW 總功率消耗= 1.603 uW
改良後 NAND2 之 layout 圖
NAND3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
INA INB
INA
INB
OUT VDD
INC
INC
INA INB INC
INA
INB INC
OUT VDD
總功率消耗=1.434uW 總功率消耗= 1.192 uW
改良後 NAND3 之 layout 圖
NOR2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
INA
INB
INA INB
GND VDD
OUT
INA
INB
INA INB
GND VDD
OUT
總功率消耗=2.233uW 總功率消耗= 1.666 uW
改良後 NOR2 之 layout 圖
NOR3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
INA
INB
INA INB
GND VDD
INC
INC OUT
INA
INB
INA INB GND VDD
INC
INC
OUT
總功率消耗= 1.507uW 總功率消耗= 1.329 uW
改良後 NOR3 之 layout 圖
D-FF w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
Q
Q’
D
Clk
總功率消耗=
2.69uW
總功率消耗=15.85 uW改良後 D-FF 之 layout 圖
XOR2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
B’ B
A A’
VDD
GND
B B’
A A’
OUT
B’ B
A A’
VDD
GND
B B’
A A’
OUT
總功率消耗= 11.11uW 總功率消耗=3.361 uW
改良後 XOR2 之 layout 圖
AO12 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
INA
INB INC OUT
INA
VDD VDD
INA
INB
INA INB VDD
VDD VDD
總功率消耗=1.338 uW 總功率消耗=1.155 uW
改良後 AO12 之 layout 圖
AOI12 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
INA
INB INC OUT
INA
INB
INA INB
GND GND
OUT VDD
VDD
改良前 DC 2.2V 改良後 AC 2.2V
INA
INB INC
OUT
INA
INB INC
OUT
總功率消耗=
2.570 uW
總功率消耗=2.127 uW改良後 AOI12 之 layout 圖
OA12 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
INA OUT
GND
VDD VDD
INA
INB
INA INB VDD
VDD
GND
GND
OUT INA OUT
GND
INA INB
INA INB GND
VDD VDD
改良前 DC 2.2V 改良後 AC 2.2V
INA
INB INC OUT
INA
INB
INA INB VDD
VDD VDD
INA
INB INC OUT
INA
INB
INA INB GND
VDD VDD
總功率消耗=2.754 uW 總功率消耗=2.168 uW
改良後 OA12 之 layout
OAI12 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良前 DC 2.2V 改良後 AC 2.2V
INA
INB INC OUT
INA
INB
INA INB VDD
VDD VDD
INA OUT
GND VDD
INA
INB INC OUT
INA
INB
INA INB GND
VDD VDD
INA OUT
GND
總功率消耗=2.378 uW 總功率消耗=2.034 uW
改良後 OAI12 之 layout 圖
Pulse DC
INV1 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-Pulse 1.8V 改良後 DC-Pulse 2.2V
INA OUT
GND
INA OUT
GND
總功率消耗= 1.058uW 總功率消耗= 1.594uW
改良後 INV 之 layout 圖
AND2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
INA
INA
INB GND
GND INB
OUT
VDD VDD
INA
INA
INB GND
GND INB
OUT
VDD VDD
總功率消耗= 1.389uW 總功率消耗= 2.176uW
改良後 AND2 之 layout 圖
AND3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
INA INA
INB GND
GND INB
OUT
VDD VDD
INC INC
INA INA
INB GND
GND INB
OUT
VDD VDD
INC INC
總功率消耗=0.973uW 總功率消耗=1.504uW
改良後 AND3 之 layout 圖
OR2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
INA
INB
INA INB
GND
GND OUT VDD
VDD
INA
INB
INA INB
GND
GND OUT VDD
VDD
總功率消耗=1.702uW 總功率消耗=2.612uW
改良後 OR2 之 layout 圖
OR3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
INA
INB
INA INB GND
GND OUT VDD
VDD INC
INC
INA
INB
INA INB GND
GND OUT VDD
VDD INC
INC
總功率消耗= 2.046uW 總功率消耗= 1.333uW
改良後 OR3 之 layout 圖
NAND2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
INA INB
INA
INB
OUT VDD
INA INB
INA
INB
OUT VDD
總功率消耗=1.129uW 總功率消耗= 1.740uW
改良後 NAND2 之 layout 圖
NAND3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
INA INB INC
INA
INB INC
OUT VDD
INA INB INC
INA
INB INC
OUT VDD
總功率消耗=0.8263uW 總功率消耗= 1.262uW
改良後 NAND3 之 layout 圖
NOR2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
INA
INB
INA INB
GND VDD
OUT
INA
INB
INA INB
GND VDD
OUT
總功率消耗=1.194uW 總功率消耗=1.866uW
改良後 NOR2 之 layout 圖
NOR3 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
INA
INB
INA INB GND VDD
INC
INC
OUT
INA
INB
INA INB GND VDD
INC
INC
OUT
總功率消耗= 0.8795uW 總功率消耗= 1.416uW
改良後 NOR3 之 layout 圖
XOR2 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
B’ B
A A’
VDD
GND
B B’
A A’
OUT
B’ B
A A’
VDD
GND
B B’
A A’
OUT
總功率消耗= 1.403uW 總功率消耗= 2.188uW
改良後 XOR2 之 layout 圖
D-FF w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
總功率消耗=9.331uW 總功率消耗= 15.14uW
改良後 D-FF layout 圖
VDD VDD
INA
VDD VDD
總功率消耗= 0.8835uW 總功率消耗=1.345uW
INA
INB INC OUT
INA
INB
INA INB
GND GND
OUT VDD
VDD
INA
INB INC OUT
INA INB
INA INB
GND GND
OUT VDD
VDD
改良後 AO12 layout 圖
AOI12 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
INA
INB INC
OUT
INA
INB INC
OUT
總功率消耗= 1.604uW 總功率消耗= 2.496uW
INA OUT
GND
INA INB
INA INB GND
VDD VDD
INA OUT
GND
INA
INB
INA INB GND
VDD VDD
改良後 AOI12 layout 圖
OA12 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
INA
INB INC OUT
INA
INB
INA INB GND
VDD VDD
INA
INB INC OUT
INA
INB
INA INB GND
VDD VDD
總功率消耗=0.8202uW 總功率消耗=1.275uW
改良後 OA12 layout
OAI12 w=0.42u (PMOS ,l=0.25u NMOS ,l=0.3u)
改良後 DC-pulse 1.8V 改良後 DC-pulse 2.2V
INA
INB INC OUT
INA
INB
INA INB GND
VDD VDD
INA OUT
GND
INA
INB INC OUT
INA
INB
INA INB GND
VDD VDD
INA OUT
GND
總功率消耗=1.464uW 總功率消耗= 2.222uW
改良後 OAI12 layout
期末專題工作分配表
[1] M. R.Prasad, D.Kirkpatrick, and R. K.Brayton, “Domino logic synthesis and technology mapping,”
presented at the Workshop Notes. Int. Workshop Logic Synthesis, 1997.
[2] T.Thorp, G.Yee, and C.Sechen, “Domino logic synthesis using complex static gates,” in Proc.
IEEE/ACM Int. Conf. Computer-Aided Design, 1998, pp. 242-247.
[3] Puri, A.Bjorksten, and T. E. Rosser, “Logic optimization by output phase assignment in dynamic logic
synthesis,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1996, pp. 2-8.
[4] D.Harris and M. A.Horowitz, “Skew-tolerant domino circuits,” IEEE J. Solid-State Circuits, vol. 32, pp.
1702-1711, Nov. 1997.
[5] R.Puri, “Design issues in mixed static-domino circuit implementations,” in Proc.
IEEE Int. Conf.
Computer Design, 1998, pp. 270-275.
[6] T.Williams, “Dynamic logic: Clocked and asynchronous,” in Tutorial notes Int.
Solid-State Circuits Conf., 1996.
[7] Clock-delayed domino for dynamic circuit design Gin Yee; Sechen, C.; Very Large Scale Integration
(VLSI) Systems, IEEE Transactions on Volume 8, Issue 4, Aug. 2000 Page(s):425 - 430
[8] Razak Hossain, “High performance ASIC design : using synthesizable domino
logic in an ASIC flow”,
Cambridge, England ; New York, N.Y. : Cambridge University Press, 2008.
[9] Tsung-Ting Yeh, “A High-Performance/Low-Power Mixed Static/Dynamic Circuit Synthesizer”, 大葉大
學碩士論文, Jun 2005.
[10] Hsiang-Hui Huang, “A Fully Synthesizable Design Flow for High-Speed Dual-Phase Dynamic Logic”,
逢甲大學碩士論文, Jun 2008.
[11]
柯門均、蕭安泰Low-Power Mixed Dynamic- Dynamic High-Speed Circuit Design Flow Implementation with Chip Validation
逢甲大學論文，DEC 2011
[12]
紀柏羽 Using Pulse Voltage and Dynamic Circuit to Deign Low-Power Bio-Electronics逢甲大學論文，JULY 2012