子計畫一:
I. 期刊論文
1. Yu-Min Lee and Po-Yi Chiang, “Effective Sleep Transistor Sizing Algorithm for Leakage Power Reduction”, International Journal of Electrical Engineering (IJEE), vol. 16, no. 5, pp. 421-431, October 2009.
2. Pei-Yu Huang, Huai-Chung Chang and Yu-Min Lee, “High Efficiency Statistical
Electro-Thermal Simulation Algorithms”, will be submitted to IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 2010.
II. 會議論文
1. Yu-Min Lee, Tsung-You Wu, and Po-Yi Chiang, “A Hierarchical Bin-Based Legalizer for Standard-Cell Designs with Minimal Disturbance”, Asia South Pacific Design Automation Conference (ASPDAC), pp. 568-573, 2010.
2. Shu-Han Whi, Bing-Shiun Su, Yu-Min Lee and Chi-Wen Pan, “Spatial Correlation Extraction with a Limited Amount of Measurement Data”, to appear in Asia Symposium on Quality Electronic Design (ASQED) 2010.
3. Huai-Chung Chang, Pei-Yu Huang, Ting-Jung Li and Yu-Min Lee, “Statistical Electro-Thermal Analysis with High Compatibility of Leakage Power Models”, International SOC Conference (SOCC) 2010.
4. Ting-Jung Li, Shu-Han Whi, Chi-Wen Pan and Yu-Min Lee, “Efficiently Adaptive Thermal Simulator for 3D-ICs”, in preparation.
5. Shu-Han Whi and Yu-Min Lee, “Dual Supply Voltage Assignment in 3D ICs Considering
Thermal Effects,” The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), 2010.
6. Shu-Han Whi and Yu-Min Lee, “Supply Voltage Assignment for Power Reduction in 3D ICs Considering Thermal Effect and Level Shifter Budget,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2011.
7. Pei-Yu Huang and Yu-Min Lee, “Statistical Hot-Spot Identification Using On-Chip Thermal Yield Profile,” VLSI Design/CAD Symposium (VLSI/CAD), 2012.
8. Pei-Yu Huang and Yu-Min Lee, “On-Chip Statistical Hot-Spot Estimation Using Mixed-Mesh Statistical Polynomial Expression Generating and Skew-Normal Based Moment Matching Techniques,” Accepted by Asia South Pacific Design Automation Conference (ASPDAC), 2012.
子計畫二:
I. 期刊論文
1. Ke-Ren Dai, Wen-Hao Liu and Yih-Lang Li, " NCTU-GR: Efficient Simulated Evolution Based Rerouting and Congestion-Relaxed LayerAssignment on 3-D Global Routing," to appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
2. Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li, “Critical-Trunk-based Obstacle-Avoiding
Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No.
9, pp. 1335 – 1348, Sep. 2011.
3. Yih-Lang Li, Yu-Ning Chang, and Wen-Nai Cheng, “A Gridless Routing System with Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment”, ACM Trans. on Design Automation of Electronic Systems, Vol 16, No. 2, Article 19 (1-25), March 2011.
II. 會議論文
1. Jiang, I.H.-R, “Generic integer linear programming formulation for 3D IC partitioning”, 22nd IEEE International SOC Conference (SOCC-2009), Belfast, UK, Sep. 2009.
2. Wan-Yu Lee and Iris Hui-Ru Jiang, “Variability tolerance on throughput and power for 3D chip-multiprocessor”, 18th International Workshop on Logic & Synthesis (IWLS-2009), Berkeley, CA, Jul. 2009.
3. Wen-Hao Liu, Yih-Lang Li and Kai-Yuan Chao, “High-Quality Global Routing for Multiple Dynamic Supply Voltage Designs,” to appear in International Conference on Computer-Aided Design (ICCAD 2011), San Jose, California, 2011.
4. Yen-Hung Lin, Yong-Chan Ban, David Z. Pan and Yih-Lang Li, “DOPPLER: DPL-aware and OPC-friendly Gridless Detailed Routing with Mask Density Balancing,” to appear in International Conference on Computer-Aided Design (ICCAD 2011), San Jose, California, 2011.
5. Wen-Hao Liu and Yih-Lang Li, " Negotiation-Based Layer Assignment for Via Count and Via Overflow Minimization," in The 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Jan. 2011.
6. Ke-Ren Dai, Yi-Chun Lin, Yih-Lang Li, “A Novel Zone-Based ILP Track Routing,” in The 15th Workshop on Synthesis And System Integration of Mixed Information technologies
(SASIMI2010), Taipei, Oct 2010.
7. Guan-Hung Chen, Ke-Ren Dai, Yih-Lang Li, “Minimizing Wirelength and Overflow of 3D-IC Global Routing by Signal-TSV Planning,” in The 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2010), Taipei, Oct 2010.
8. Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li, “Efficient Random-Defect Aware Layer Assignment and Gridless Track Routing,” in The 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2010), Taipei, Oct 2010.
9. Yen-Hung Lin and Yih-Lang Li, “Double Patterning Lithography Aware Gridless Detailed Routing with Innovative Conflict Graph”, in Proceedings of ACM/IEEE Design Automation Conference (DAC-2010), Anaheim, CA, June 2010.
10. Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, and Kai-Yuan Chao, “Multi-Threaded
Collision-Aware Global Routing with Bounded-Length Maze Routing”, in Proceedings of ACM/IEEE Design Automation Conference (DAC-2010), Anaheim, CA, June 2010.
11. Chih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li, “Dead Via Minimization by
Simultaneous Routing and Redundant Via Insertion”, in The 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010), Taipei, Jan. 2010.
12. Wen-Hao Liu, Yih-Lang Li, Hui-chi Chen, “Minimizing Clock Latency Range in Robust Clock Tree Synthesis”, in The 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010), Taipei, Jan. 2010.
子計畫三:
I. 期刊論文
1. Juinn-Dar Huang, Ya-Shih Huang, Liya Wang, and Geeng-Wei Lee, “Throughput-Aware
Floorplanning via Dynamic Optimization on Performance-Critical Loops,” International Journal of Electrical Engineering, vol. 17, no.1, pp. 33-42, Feb. 2010.
II. 會議論文
1. Wan-Hsien Lin, Juinn-Dar Huang and Ya-Shih Huang, “Performance-Driven Behavioral Synthesis with Degenerable Compound Functional Units”, Proc. of the 20th VLSI Design/CAD Symposium, Aug. 2009.
2. Ya-Shih Huang and Juinn-Dar Huang, “Hierarchical Placement in 2D Regular Architecture for Throughput Optimization,” Proc. of the 20th VLSI Design/CAD Symposium, Aug. 2009.
3. Ya-Shih Huang and Juinn-Dar Huang, “Throughput-Driven Hierarchical Placement for
Two-Dimensional Regular Multicycle Communication Architecture,” Asia Symposium on Quality Electronic Design, pp. 134–139, Aug. 2010.
4. Ya-Shih Huang, Yang-Hsiang Liu, and Juinn-Dar Huang, “Layer-Aware Partitioning for
Through-Silicon Via Minimization in 3D ICs,” Proc. of the 21st VLSI Design/CAD Symposium, Aug. 2010.
5. Chia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang, “Architectural Exploration of 3D FPGAs towards a Better Balance between Area and Delay,” Proc. of Design, Automation & Test in Europe
Conference and Exhibition, pp. 587–590, Mar. 2011.
6. Ya-Shih Huang, Yang-Hsiang Liu, and Juinn-Dar Huang, “Iterative 3D Partitioning for Through-Silicon Via Minimization,” Proc. of the 16th Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 154–159, Oct. 2010.
7. Juinn-Dar Huang, Yi-Hang Chen, and Wan-Hsien Lin, “Performance-Optimal Behavioral Synthesis with Degenerable Compound Functional Units,” Proc. of IEEE International Symposium on VLSI Design, Automation, and Test, pp. 337–340, Apr. 2011. (Best Paper Candidate)
8. Ya-Shih Huang, Yang-Hsiang Liu and Juinn-Dar Huang, “Layer-Aware Design Partitioning for Vertical Interconnect Minimization,” Proc. of IEEE Computer Society Annual Symposium on VLSI, pp. 144–149, Jul. 2011. (Best Paper Award)
子計畫四:
I. 期刊論文
1. C.-Y. Lin, H.-C. Lin and H.-M. Chen, “On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes,” IEEE Transactions on Very Large Scale Integration
Systems(TVLSI) 2010.
2. R.-J. Lee and H.-M. Chen, "Fast Flip-Chip Pin-Out Designation Respin for Package-Board
Codesign," IEEE Transactions on Very Large Scale Integration Systems, v.17, no.8, pp.1087-1098, August 2009 (TVLSI-Aug-09)
3. M.-C. Wu, M.-C. Lu, H.-M. Chen, and J.-Y. Jou, "Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC Floorplanning," , ACM Transactions on Design Automation of
Electronic Systems (TODAES) 2009
4. C.-Y. Lin, L.-C. Hsu, and H.-M. Chen, "On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques," in IEICE Transactions, 2010
II. 會議論文
1. C.-C. Hsiao and H.-M. Chen, "On Distinguishing Process Corners for Yield Enhancement in Memory Compiler Generated SRAM," Proc. of IEEE International Workshop on Memory Technology, Design, and Test (MTDT-09), August 2009
2. F.-Y. Fan, H.-M. Chen, and I-M. Liu, "Technology Mapping with Crosstalk Noise Avoidance,"
ACM/IEEE ASP-DAC-10, January 2010.
3. C.-Y. Lin and H.-M. Chen, "A Novel Two-Dimensional Scan-Control Scheme for Test-Cost Reduction," Proceedings of the 20th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2009.
4. R.-J. Lee and H.-M. Chen, "Row-Based Area-Array I/O Design Planning in Concurrent
Chip-Package Design Flow," Proc. of IEEE Asia and South Pacific Design Automation Conference, January 2011 (ASP-DAC-11)
5. T.-Y. Tsai, R.-J. Lee, C.-Y. Chin, C.-Y. Kuan, H.-M. Chen, and Y. Kajitani, "On Routing Fixed Escaped Boundary Pins for High Speed Boards," Proc. of IEEE Design, Automation and Test in Europe, March 2011 (DATE-11)
6. C.-Y. Lin, H.-M. Chen, and W.-C. Fang, "A Low Noise and Robust 3D System-in-Package Test Scheme for Optical Biosensor," IEEE/NIH Life Science Systems and Applications Workshop, April 2011 (LiSSA-11)
7. Y.-R. Chen, H.-M. Chen, and S.-Y. Liu, "TSV-Based 3D-IC Placement for Timing Optimization,"
Proc. of IEEE International System on Chip Conference, September 2011 (SOCC-11) 8. H.-W. Hsu, R.-J. Lee, and H.-M. Chen, “On Effective Flip-Chip Routing via Pseudo Single
Redistribution Layer,” submit to Proc. of IEEE Design, Automation and Test in Europe, March 2012 (DATE-12)
子計畫五:
I. 期刊論文
1. Huan-Kai (Pumbaa) Peng, Yu-Hsin (Phoebe) Kuo, and Charles H.-P. Wen, "Statistical Soft
Error Rate (SSER) Analysis Considering Uncertainty Due to Process Variation," in submission to IEEE Transactions on Computers (TC) 2009.
2. Chien-Hui Liao, Yu-Ze Lin and H.-P. Wen, “Enhancing Energy-Efficient Task Scheduling on 3D Multi-Core Processors by Dynamic Remapping”, submit to IET Computers & Digital Techniques, 2011.(under review)
3. Chien-Hui Liao, Wei-Ting Chen, Yu-Ze Lin and H.-P. Wen, “Fast Scan-Chain Ordering for 3D-IC Designs under Through-Silicon-Via (TSV) Constraints”submit to IEEE Transaction on Very Large Scale Integration Systems, 2011.(under review)
II. 會議論文
1. Pumbaa H.-K. Peng., Charles H.-P. Wen and Jayanta Bhadra, “On Soft Error Rate Analysis Beyond Deep Submicron - A Statistical Perspective”, Proceedings of the International Conference on Computer-Aided Design, 2009.
2. Yu-Hsin (Phoebe) Kuo, Charles H.-P. Wen and Pumbaa H.-K. Peng, “Accurate Statistical Soft Error Rate (SSER) Analysis Using A Quasi-Monte Carlo Framework With Quality Cell Models”, Proceedings of the ISQED, 2010
3. Chen-Yuan (Ben) Gao, Chien-Hui (Christina) Liao and Charles H.-P. Wen, "An ILP-based Diagnosis Framework For Multiple Open-Segment Defects, " to appear in IEEE Workshop on Microprocessor Test and Verification (MTV'09),December 2009.
4. Lynn C.-L. Chang, Charles H.-P. Wen and Jayanta Bhadra, "Paper 16.1: Speeding up Bounded Sequential Equivalence Checking with Cross-Timeframe State-Pair Constraints from Data Learning, " Proc. Int'l Test Conference, (ITC'09), November 2009.
5. Francisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen, Mrinal Bose and Jayanta Bhadra, "Poster #16: Portable simulation/emulation stimulus on an industrial-strength
SoC," Proc. Int'l Test Conference, (ITC'09), November 2009.
6. Wei-Ting Chen, Chia-Chin Chang and H.-P Wen, “Through-Silicon-Via(TSV)-constrained Scan Chain Reordering for Three-dimensional(3D) Integrated Circuits”, SASIMI Workshop, Oct 2010.
7. Wei-Ting Chen, Chia-Chin Chang and H.-P Wen, “Through-Silicon-Via (TSV)-constrained Scan Chain Reordering for Three-dimensional(3D) Integrated Circuits” VLSI Design / CAD Symposium, April 2010.
8. Christina C.-H. Liao and Charles H.-P. Wen, “Performance Validation of
Dynamic-Remapping-Based Task Scheduling on 3D Multi-Core Processors”, submit to International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2012.
(under review)
4. 專利
control arbiter and themethod thereof Method of 2-Pin Logic Cell
施盈安、陳宏明 US 7913219 美國