1. Journal papers (1)
a、 J. H. Luo, C. N. Wang, and Tihao Chiang, “A novel all binary motion estimation with optimized hardware architectures, “ IEEE Transaction on Circuits and Systems for Video Technology—Special Issue on Multimedia Implementation, Aug. 2002.
2. International conference papers (3)
a、 J. H. Luo, C. N. Wang, and Tihao Chiang, “A Novel All Binary Motion Estimation (ABME), “in Proceeding of ISCAS02, 2002.
b、 Shih-Hao Wang, Wen-Hsiao Peng, Yuwen He, Guan-Yi Lin, Chen-Yi Lin, Shih-Chien Chang, Chung-Neng Wang, and Tihao Chiang, “A Platform-Based MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining”, Accepted by PCM2003.
c、 Chih-Hung Li, Chung-Neng Wang, and Tihao Chiang, “A VBR Rate Control Using MINMAX Criterion for Video Streaming, ” in Proceeding of PCM02 (HsinChu, Taiwan), Dec. 2002, pp.831-838.
3. Domestic conference papers (4)
a、 Yue-Lin Lee, C.-N. Wang, and Tihao Chiang, “An MPEG-4 Error Resilient Decoder, “ in Proceeding of WCE 2001.
b、 S.-H. Wang, C.-N. Wang, and Tihao Chiang, “An optimized MPEG-4 Reference Software,” in Proceeding of Lee Center’s Workshop, 2001.
c、 S.-H. Wang, G.-Y. Lin, C.-N. Wang, X.-Y. Wu, and Tihao Chiang, “A Fast Variable Length Decoder for MPEG-4 Using Hierarchical Table Lookup,” in Proceeding of WCE 2002.
d、 Ming-Yen Huang, Tzu-Liang Su, Shih-Hao Wang, Chung-Neng Wang, and Tihao Chiang, “An Error Resilient System for Streaming MPEG-4 Video over the Internet,” Accepted by WCE2003, Oct. 2003.
4. Patents (3)
ABME (細節請參閱可供推廣之研發成果資料表(一))
a、 C.-H. Luo, G.-M. Lee, C.-N. Wang, and Tihao Chiang, “Method And Apparatus For Estimation With Binary Representation,” Filed in U.S patent (IAM10/301415 ), February 26th, 2003.
b、 C.-H. Luo, G.-M. Lee, C.-N. Wang, and Tihao Chiang, “Method And
Apparatus For Estimation With Binary Representation,” Filed in Japan patent (2003-048958), November 11th, 2002.
c、 C.-H. Luo, G.-M. Lee, C.-N. Wang, and Tihao Chiang, “在視訊影像編碼中作 為動態預測的裝置與方法,” Filed in R.O.C patent(92104361 ), September 27, 2003
5. Master thesis (2)
a、 C.-H. Luo and Tihao Chiang, “On a Fast Motion Estimation Algorithm, ” Master Thesis, Dept. of Electronic Engineering, National Chiao Tung University, June, 2001
b、 Wei-Lun Tao and Tihao Chiang, “ARM 平台的全二元動量估測架構之設計An All-Binary Motion Estimation Architecture Design on ARM-Based Platform”, Master Thesis, Department of Electronics Engineering, National Chiao Tung University, Oct. 2003.
6. MPEG contributions (19)
a、 C.-N. Wang, J.-H. Luo, and Tihao Chiang, “ISO/IEC JTC1/SC 29/WG 11 14496-2 N3674: Description of Rate Control Core Experiments Q6, ” Oct.
2000 (La Baule).
b、 J.-H. Luo, C.-N. Wang, and Tihao Chiang, “ISO/IEC JTC1/SC 29/WG 11 14496-2 M6889: Results of Rate Control Core Experiments Q6, ” Jan. 2001 (Pisa)
c、 C.-N. Wang, C.-Y. Lee, Tihao Chiang, and H.-M. Hang, “ISO/IEC JTC1/SC 29/WG 11 14496-2 M7784: Work Plan on Software Integration and
Verification for MPEG-4 14496-5 Reference Software, ” Oct. 2001 (Pattaya, Thailand).
d、 S.-H. Wang, C.-N. Wang, Tihao Chiang, and H.F. Sun, “ISO/IEC JTC1/SC 29/WG 11 14496-2 M8041: AHG report on editorial convergence of MPEG-4 reference software, ” Mar. 2002 (Jeju Island, Korea).
e、 C.-N. Wang and Tihao Chiang, “ISO/IEC JTC1/SC 29/WG 11 14496-2 M8407:
Draft Call for Proposals on Fast Motion Estimation for 14496-10 JVT, ” May 2002 (Fairfax, VA, USA).
f、 S.-H. Wang, Yao-Chung Lin, C.-N. Wang, Tihao Chiang, and H.F. Sun,
“ISO/IEC JTC1/SC 29/WG 11 14496-2 M8408: AHG report on editorial convergence of MPEG-4 reference software, ” May 2002 (Fairfax, VA, USA) g、 S.-H. Wang, C.-N. Wang, Tihao Chiang, and H.F. Sun, “ISO/IEC JTC1/SC
29/WG 11 14496-2 M8603: AHG report on editorial convergence of MPEG-4 reference software, ” July 2002.
h、 S.-H. Wang, C.-N. Wang, Tihao Chiang, and H.F. Sun, “ISO/IEC JTC1/SC 29/WG 11 14496-2 M8884: AHG report on editorial convergence of MPEG-4 reference software, ” Oct. 2002.
i、 C.-N. Wang, Tihao Chiang, and Jens-Rainer Ohm, “ISO/IEC JTC1/SC 29/WG 11 14496-2 M8885: MPEG-4 Visual: Updated List of Problems Reported, ” Oct. 2002.
j、 S.-H. Wang, C.-N. Wang, Tihao Chiang, and H.F. Sun, “ISO/IEC JTC1/SC 29/WG 11 14496-2 M8886: Proposed Text of Proposed Draft Technical Reports of ISO/IEC PDTR 14496-7 for Optimized Simple Profile Reference Software, ” Oct. 2002.
k、 S.-H. Wang, C.-N. Wang, G.-Y. Lin, Tihao Chiang, and H.F. Sun, “ISO/IEC JTC1/SC 29/WG 11 14496-2 M9073: AHG report on editorial convergence of MPEG-4 reference software, ” Dec. 2002
l、 C.-N. Wang, Y.-S. Tung, Tihao Chiang, and Jens-Rainer Ohm, “ISO/IEC JTC1/SC 29/WG 11 14496-2 M9181: MPEG-4 Visual: Updated List of Problems Reported, ” Dec. 2002.
m、 S.-H. Wang, C.-N. Wang, Yi-Shin Tung, T. Chiang, and H.F. Sun, “ISO/IEC JTC1/SC 29/WG 11 M9632: AHG report on editorial convergence of MPEG-4 reference software, ”July 2003.
n、 C.-N. Wang, Y.-S. Tung, T. Chiang, and Jens-Rainer Ohm, “ISO/IEC JTC1/SC 29/WG 11 M9484: MPEG-4 Visual: Updated List of Problems Reported, ” Mar.
2003.
o、 S.-H. Wang, C.-N. Wang, Yi-Shin Tung, T. Chiang, and H.F. Sun, “ISO/IEC JTC1/SC 29/WG 11 M9355: AHG report on editorial convergence of MPEG-4 reference software, ” Mar. 2003
p、 C.-N. Wang, Y.-S. Tung, T. Chiang, and Jens-Rainer Ohm, “ISO/IEC JTC1/SC 29/WG 11 M9763: MPEG-4 Visual: Updated List of Problems Reported, ” July 2003.
q、 C.-N. Wang and T. Chiang, “ISO/IEC JTC1/SC 29/WG 11 M9764:
Improvement of Optimized MPEG-4 14496-2 Simple Codec with EPFL SIT Analyzer, ” July 2003.
r、 S.-H. Wang, C.-N. Wang, Yi-Shin Tung, T. Chiang, and H.F. Sun, “ISO/IEC JTC1/SC 29/WG 11 M9951: AHG report on editorial convergence of MPEG-4 reference software, ” October 2003.
s、 C.-N. Wang, Y.-S. Tung, T. Chiang, and Jens-Rainer Ohm, “ISO/IEC JTC1/SC 29/WG 11 M10173: MPEG-4 Visual: Updated List of Problems Reported, ” October 2003.
7. JVT documents (1)
a、 G.-M. Lee, C.-N. Wang, and Tihao Chiang, “JVT-F079: Cross check results for JVT-F017, “ Joint Video Team (JVT) of ISO/IEC MPEG & ITU-T VCEG (ISO/IEC JTC1/SC29/WG11 and ITU-T SG16 Q.6), Dec. 2002.
可供推廣之研發成果資料表(一)
□ 可申請專利 5 可技術移轉 日期：92 年 10 月 30 日
國科會補助計畫
計畫名稱：單晶片無線多媒體資訊家電之設計與製作(3/3) -- 子計劃四 : 單晶片無線多媒體通訊系統
計畫主持人：蔣迪豪 交通大學電子工程系所 副教授
計畫編號：NSC－91-2218-E-009-005 學門領域：SoC
技術/創作名稱
All Binary Motion Estimation (ABME)發明人/創作人
羅正弘, 李鑑明, 王俊能, 蔣迪豪 中文：技術說明
英文：
1. We present a fast motion estimation algorithm using only binary representation, which is desirable for both embedded system software optimization and hardware implementation with parallel architectures.
2. Additionally, our fast motion estimation algorithm employs the other two alternative Boolean operations instead of SoD (using XOR operation) as interblock similarity measures. The new measure is Sum of One (SoO) and Sum of Zero (SoZ). The SoO uses the AND operation for similarity checking and the SoZ takes the NOR operation for similarity checking.
3. Finally, our fast motion estimation algorithm accomplishes the exhaustive search with the sequentially arranged binary data in each pyramidal level, which provides a feasible hardware implementation.
The experimental results show that the proposed algorithm is applicable for smaller picture size at low bitrates such as MPEG-4 and H.263 applications. It is also useful for the applications of larger picture size at high bitrates such as MPEG-2 applications
可利用之產業 及 可開發之產品
1. Films using MPEG or H.26X, Global motion estimation video encoding techniques
2. Surveillance
3. Multimedia like DVD, VCD, HDTV.
4. Content providers
5. MPEG video related software encoder 6. Video indexing using motion features 7. Wireless communication-based appliances 附件二
技術特點
This invention has been made to overcome the above-mentioned drawbacks of conventional motion estimation. The primary object is to provide a method for motion estimation with all binary representation for video coding. Accordingly, a binary pyramid having three binary layers of video images is constructed. The first binary layer is first searched with a criterion based on bit-wise sum of difference to find a first level motion vector. Six motion vector candidates are used to determine a motion vector in the second binary layer. Finally, a search in the third binary layer according to the second layer motion vector generates a final motion vector.
In the present invention, the construction of the binary pyramid includes filtering, binarization and decimation. The precise edge information is extracted based on the spatial variation within a small local area of an image to provide all binary edge information without having to use any integer layer. In the first level search, the search is performed within a ±3 pixel refinement window.
In the second level search, based on the spatio-temporal dependencies that exist among blocks, ABME calculates the ranges of two dimensional 8×8 motion offsets ([Rmxin,Rmxax],[Rminy ,Rmaxy ]) through the six motion vector candidates from the current and previous frames.
The refinement window in the second level has thus covered the dominant ranges of the search area with dimension(Rmaxx +Rminx )×(Rmaxy +Rminy ) around the mean vector of the six motion vectors. We then perform the full-search XOR Boolean block matching with (Rmaxx +Rminx )×(Rmaxy +Rminy ) pixels for refinement at the second level. Similarly, the resultant motion vector candidate will be passed onto the next binary level.
In the third level, the search is performed within a ±2 pixel refinement window. At each level, the search and determination of the best motion vector is based on a criterion of minimum bit-wise sum of difference using XOR block matching.
It is also an object of the invention to provide an apparatus for motion estimation for video encoding. Accordingly, the apparatus comprises a binary pyramid construction module, a first level search module, a second level search module, and a third level search module. Each level search module includes a data loading module, a bit alignment module, and an XOR block matching module. The binary pyramid construction structure further comprises a filtering module, a binarization module and a decimation module. Each XOR block matching module further includes a table lookup sub-module and a bit-wise sum of difference (SoD) sub-module.
The motion estimation of this invention is feasible for pipelined architectures. The method of motion estimation can be implemented in various architectures including general-purpose architectures such as x86, single instruction multiple data (SIMD) architectures using Intel’s MMX technology, and systolic arrays. The pipelined architecture of the invention contains three major common modules including the integrated construction, compact storage, and parallel block matching.
The invention uses a MPEG-4 reference video encoder and employs a macroblock with size 16×16 for block matching to show the performances. According to the experimental results, it not only has the benefits of low computational complexity and low memory bandwidth consumption but also is insensitive to search range increase. System designer can choose better binarization methods to further improve the visual quality. In addition, various optimization methods can be developed for specific platforms with different register size. The invention thus is more flexible than other motion estimation method.
From the operation counts, the motion estimation of this invention is very desirable for software implementation on a general-purpose processor system. It can be realized by a parallel-pipelined implementation for ASIC design and allows tradeoffs between Silicon area, power consumption and visual quality during the hardware design phase.
推廣及運用的價值
※ 1.每項研發成果請填寫一式二份，一份隨成果報告送繳本會，一份送 貴單位
研發成果推廣單位（如技術移轉中心）。
※ 2.本項研發成果若尚未申請專利，請勿揭露可申請專利之主要內容。
※ 3.本表若不敷使用，請自行影印使用。