在本論文中，一開始介紹了快閃記憶體在未來製程不斷變小，導致在快閃記 憶體在寫入會影響鄰近的資料，讓儲存資料上發生錯誤機率提高成為目前成為在 各個快閃記憶體做為軟式錯誤解碼研究背景。接下來說明了梯度下降法的理論基 礎、運作方式、JN 演算法並且將快閃記憶體控制的規格之運作背景與詳細步驟。
本論文在快閃記憶體提出的 BCH-JN 軟式解碼適用於傳輸規格在 512 位元組 編碼率底下並且以記憶體為 1 年的錯誤率作模擬，JN 軟式解碼透過回授機制會不 斷更新低信任度位置，促使在高斯消去法後的低信任度位置能夠在單位矩陣範圍 內，能夠提高梯度下降法後額外所獲得較高信任度資料，減少錯誤資料傳遞的情 況。在模擬中，在此針對 JN 所提出的其他演算法並且比較，在軟式解碼所額外增 加的解碼會對於解碼有改善，但是將會讓軟式解碼的硬體複雜度與成本將會變很 龐大。
在硬體中，將史密斯高斯消去的方法應用在硬體實現上，減少傳統 Jordan 高 斯消去法運算所需要長時間才能夠完成，另外透過定數模擬我們規範出梯度下降 法的校驗矩陣的長度以及在單位矩陣中所模擬的校驗節點排序成為 1 個，節省 Tanh 查表法在硬體的需求。在功率和硬體複雜度目前與 BCH 硬式解碼比較還要 高，BCH-JN 軟式解碼在 0.18um 製程下所需要功耗為 14.05mW 與另外一篇文獻 所提出 BCH 硬式解碼在 0.25um 所需要功耗為 8.17mW，已經差了快一倍，在硬 體複雜度軟式解碼史密斯高斯消去法已經佔去 9 成的面積，但運算時間卻也因為 疊代和梯度下降法需求運算時間會很多。
BCH-JN 軟式解碼與 LDPC 在未來上在快閃記憶體的應用，其實都是以梯度 下降法背景動作這兩個軟式解碼，同樣是越需要簡單的方式減少高斯消去法的硬 體複雜度和因為疊代和梯度下降法所需要的運算時間，另外在提高梯度下降法在 統計資料的正確性同時並且減少低信任度位置錯誤的影響，是未來在需要軟式解 碼上可以思考的課題。
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