本論文以 M. R. Lee[9]的架構為基礎，結合 Ghoreishi[11]直接在電路中以 2 補 數計算負值方法及四倍輸入化簡電路的概念，實現修改使用進位儲存加法器的以 四為基底 Montgomery 演算法，其中以四為基底比以二為基底少了一半的運算週期 數，減少 RSA 運算的時間，使用在電路中以 2 補數計算負值方法利用進位儲存加 法器 carry 為 0 的特性來擺放取 2 補數所加的 1 及進位修正項的 1 達到減少面積的 效果，可以節省兩排 512-bit 的暫存器，再搭配四倍輸入簡化電路的方法降低電路 的複雜度，使計算(t1, t0)的電路不在關鍵路徑裡，可以跟進位儲存加法器平行運算，
降低電路的關鍵路徑，修改使用進位儲存加法器的以四為基底 Montgomery 演算法 也跟 Lee 的架構一樣拆開輸入使 A 變成 A1+A2、B 變成 B1+B2 ，如此一來可以 有效率的執行模指數運算，最後我們使用改良的模乘法及模指數 H 演算法完成整 個 RSA 密碼系統的設計。
本論文實驗數據顯示 TSMC 90nm 製程合成出的電路速度最快可達 455MHz，
Gate Count 為 76K，Throughput 為 879.2K bps，與最近的文獻[9]比較起來速度改善 了 27.45%，面積改善了 37.19%，Throughput 改善了 26.78%。與其他模乘法較出 色 的兩 篇 文獻 Kuang[12] 及 Shieh[13] 在 Throughput 方面分別改善了 3.9%及 33.37%。
本論文使用三層的進位儲存加法器的架構實現 RSA 密碼系統，在相關文獻[14]
中有一個改良的 5-to-2 加法器，因為該電路是將兩個 FA 接在一起，變成一個兩位 元的加法器，有較短的關鍵路徑，如果將這樣的加法器放進我的修改使用進位儲 存加法器的以四為基底 Montgomery 演算法中，且將本論文提出的兩種改善方式應 用其中，就能夠使電路的關鍵路徑更短，且因為是將兩個 FA 由直的變成橫的，在 面積方面幾乎沒有改變，卻能達到降低關鍵路徑的效果。
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