• 沒有找到結果。

當元件的閘極氧化層持續下降至2 nm,如何增加運作的時脈與降低高 功率的消耗已經成為元件製程最具挑戰的問題。在更先進的高介電常數介 電層與金屬閘極達到簡易與具高成本效益的量產技術前,有效解決這些問題 的方法之一為引進氮進入閘極氧化層。氮的引進將使相同等效氧化層厚度 的閘極絕緣層具有較厚的物理厚度而減少其穿隧電流,並同時可有效地抑 制硼的擴散。電漿氮化製程由於具備單晶圓技術以及多製程整合能力,不 同於其他的閘極氮氧化技術,而能產生精確的氮離子分佈控制,此實驗主 要提供了一個改善此主流製程技術在量產上的問題。

經本研究利用OES 的強度來間接預測電漿氮化閘極製程反應下,二氧 化矽中氮的含量與製程最佳化。結果,獲得以下的結論:

1. 在波長337.03nm 的光譜訊號與氮濃度有著最好的相關性。

2. 此製程的氮濃度推測應該主要由波長337.03nm Nitrogen radical 所 貢獻。

3. 光譜訊號強度與電性參數如等效氧化層厚度,汲極飽和驅動電流和 臨界電壓有合理的線性關係存在。

4. 光譜訊號強度、電性參數與氮濃度在變化的趨勢上符合理論上的推 測。

5. 由於光譜訊號強度與電性參數有相關性,因此利用光譜訊號可以對

電性參數找出最佳化的區間。

6. 此預測之方法具有即時與簡單之優點。

參考文獻

[1] Nouri, F. Kher, S. Narwankar, P. Sharangpani, R. Muthukrishnan, S. Kraus, P.

Ahmed, K. Olsen, C. Thai Cheng Chua Cruse, “Trends in gate stack

engineering”. Integrated Circuit Design and Technology, pp. 275-281, 2004.

[2] G. Higashi, T. Lill, “Challenge from 90nm Front End of Line”, EETimes, 2003.

[3] International Technology Roadmap for Semiconductors, Front End Processes, pp. 70-71, 2005.

[4] J. H. Lee, Y. S. Suh, H. Lazar, R. Jha, J. Gurganus, Y. Lin, V. Misra,

“Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS”, IEDM, 2003.

[5] R. B. Beck, A. Jakubowski, “Ultrathin oxynitride films for CMOS

technology”, Journal of Telecommunications and Information Technology, pp.62-69, 2004.

[6] 余昱穎,陳經緯,簡昭欣,“在具有超薄(EOT=1.6 nm)氮化閘極氧化 層之0.13μm n 型金氧半電晶體中由熱電子所引發於閘極絕緣層內之電 子捕獲現象",奈米通訊,第十一卷,第四期,pp. 6-10,民國九十二年。

[7] E. Ibok, K. Ahmed, M. Y. Hao, B. Ogle, J. J. Wortman, and J. R. Hauser,

"Gate quality ultrathin (2.5 nm) PECVD deposited oxynitride and nitrided oxide dielectrics", IEEE Electron Device Lett., vol. 201, no. 9, pp. 442-444, Sept. 1999.

[8] C. H. Chen, Y. K. Fang, C. W. Yang, S. F. Ting, Y. S. Tsair, M. C. Yu, T. H.

Hou, M. F. Wang, S. C. Chen, C. H. Yu, and M. S. Liang,

"Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gate oxide with excellent performances in reduction of leakage current and boron diffusion", IEEE Electron Device Lett., vol. 22, pp. 378-380, Aug. 2001.

[9] Y. Wu, Y. M. Lee, and G. Lucovsky, "1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O) composites prepared by RPECVD/oxidation

process", IEEE Electron Device Lett., vol. 21, no. 3, pp. 116-118, Mar. 2000.

[10] N. Kimizuka, K. Yamaguchi, K. Imai, T.Iizuka, C. T. Liu, R. C. Keller, and T.

Horiuchi, "NBTI enhancement by nitrogen incorporation into ultrathin gate

oxide for 0.1-µm gate CMOS generation", VLSI Tech. Dig., pp. 92-93, 2000.

[11] H. S. Momose, T. Morimoto, Y. Ozawa, K. Yamabe, and H. Iwai, "Electrical characteristics of rapid thermal nitrided-oxide gate n- and p-MOSFET's with less than 1 Atom% nitrogen concentration", IEEE Trans. Electron Devices, vol. 41, no. 4, pp. 546-552, April, 1994.

[12] H.-H. Tseng, Y. Jeon, P. Abramowitz, T. Luo, L. Hebert, J. J. Lee, J. Jiang, P.

J. Tobin, G. C. F. Yeap, M. Moosa, J. Alvis, S. G. H. Anderson, N. Cave, T.

C. Chua, A. Hegedus, G. Miner, J. Jeon, and A. Sultan, "Ultra-thin decoupled plasma nitridation (DPN) oxynitride gate dielectric for 80-nm advanced technology," IEEE Electron Device Lett., vol. 23, no. 12, pp. 704-706, Dec.

2002.

[13] K. C. Chen, H. H. Shih, C. Hsueh, H. Chung, S. Pam, C.Y. Lu, C.W. Chou and S. S. Chen, "Cycle Time and Process Improvement by Single Wafer Thermal Processing in Production Environment," presented at the 10th International Conference on Advanced Thermal Processing of

Semiconductors RTP 2002, September 2002.

[14] P.A. Kraus, et. al, "Low-energy nitrogen plasmas for 65-nm node oxynitride gate dielectrics: a correlation of plasma characteristics and device

parameters", Symposium on VLSI Technology, 2003.

[15] Hegedus Andy, OLSEN Chris S. ,KUAN Nolan, Madok John, “Clustering of plasma nitridation and post anneal steps to improve threshold voltage

repeatability”, IEEE Transaction on Semiconductor Manufacture, vol. 16, pp.165-169, 2003.

[16] Edwin T. Carlen and Carlos H. Mastrangelo, “Statistical Model for Spatial Correlation in Thin Film Deposition and Reactive Growth”, IEEE

Transactions on Semiconductor Manufacturing, vol. 11, no. 3, Aug. 1998.

[17] A. M. Acevedo, G. Francisco, “On the Thermal Re-Oxidation of Silicon Oxynitride”, Material Research Society, pp. 22-28, 1998.

[18] 陳家富, “電漿與薄膜製程技術手冊”, 民國九十四年九月。

[19] 張家豪,魏鴻文,翁政輝,柳克強, “電漿源原理與應用之介紹” ,物理 雙月刊,廿八卷二期,民國九十五年四月。

[20] M. A. Lieberman and A. J. Lichtenberg, “Principles of Plasma Discharges and Materials Processing”, John Wiley & Sons, 1994.

[21] G. L. Weissler, “photoelectric emission from solids”, Handbuch der physic, 21, pp. 342-382, 1956.

[22] Hamamatsu Photonics K. K., “Photomultiplier Tube Handbook”, Feb. 2006.

[23] H. Bruining, “Physics and Application of secondary electron emission”, 1954.

[24] A. Velosol, FN Cubaynes, A. Rothschild, S. Mertensl, R. Degraevel, R.

O’Connor, “Ultra-thin Oxynitride Gate Dielectrics DPN for 65nm”,

Extended Abstracts of International Workshop on Gate Insulator, pp.140-145, 2003.

[25] 潘扶民,”半導體材料分析講義", 民國九十五年六月。

[26] H. H. Tseng, Y. Jeon, P. Abramowitz, T. Y. Luo, L. Hebert, J. J. Lee, J. Jiang, P. J. Tobin, G. C. F. Yeap, M. Moosa, J. Alvis, S. Anderson, N. Cave, T. C.

Chua, A. Hegedus, G. Miner, J. Jeon, and A. Sultan, “Ultra-thin decoupled plasma nitridation” (DPN) oxynitride gate dielectric for 80-nm advanced technology," IEEE Electron Device Lett., vol. 23, no. 12, pp. 704-706, Dec.

2002.

[27] V M Donnelly, M V Malyshev, M Schabel, A Kornblit, W Tai, I P Herman and N C M Fuller, “Optical plasma emission spectroscopy of plasma used in Si-Based semiconductor processing”, Plasma Sources Sci. Technology 11, pp.

26-30, 2002.

[28] P.A. Kraus, et. al, "Low-energy nitrogen plasmas for 65-nm node oxynitride gate dielectrics: a correlation of plasma characteristics and device

parameters", Symposium on VLSI Technology, 2003.

[29] C. H. Chen, Y. K. Fang, C. W. Yang, "Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gate oxide with excellent performances in

reduction of leakage current and boron diffusion," IEEE, pp. 124-128, 2003.

[30] C. Diaz, et. al., "Application-Dependent Scaling Tradeoffs and Optimization in the SoC Era", IEEE, pp. 475-478, Jun 2002.

[31] S.M. Sze, “Semiconductor Device Physics and Technology 2nd Edition”, 2001.

[32] Applied Material DPN process manual rev. 3, pp.36-42, 2004.

自 傳

來自嘉義縣新港鄉的小康家庭,家中成員五人,個人排行老么。早年 因父親為勞工階級所以家人皆以儉持家,現今兄弟皆已成家分居各處,但 每週末常有家庭聚會,共聚一堂。

大學就讀於中興大學機械系,在校期間除專業課目外,對校外活動也 多有參與。由於個性外向善於溝通,常代表系上參加校際公關活動與康輔 社團。工作多年後由於在職場上專業技能的需求,在公司的長官與家人的 鼓勵下進入交通大學工學院半導體學分班進修。進修期間接受恩師 陳家 富教授的薰陶與多位優秀的教授的指導,讓我在專業與工作方式有了長足 的進步。

十二年的外商職場生涯從科林研發(Lam Reserch)到應用材料(Applied Materials)大多負責新產品專案管理。由於外商的高度競爭,與實事求的文 化倒是造就了抗壓的優勢與責任感。

期待在學業完成後能有更好的升遷管道,也期盼與許多優秀的同學共 創更好的未來。

相關文件